JPS6115182A - Display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a line scanning display device capable of switching between a half-flash mode and a flashless mode.

[Technical background of the invention and its problems]

In the display device of the Rask scan method, as a means to redraw the screen (image), that is, to efficiently perform the drawing without causing visual disturbance, the display device is divided into one display cycle and one drawing cycle. Separately, there is a display control means that alternately and repeatedly executes these display cycles and drawing cycles.

However, in this conventional polar display control means,
Even if drawing in flash mode ends in a time that does not feel visually unnatural (flickering is not noticeable), the preset display time is fixed.
It was IIIW. Therefore, there was a problem in performing drawing efficiently and at high speed.

There are also display devices that can be used by switching between a flash mode that gives priority to drawing and a Franchless mode that gives priority to display, in which images are drawn during line scanning, but in conventional devices of this type, had the disadvantage that the flash mode continued at the end of the drawing, so if the drawing time was long, the screen would flicker, causing visual inconvenience.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and switches between drawing control using a flash mode and drawing control that is time-divided between a cycle that displays one cycle and a drawing cycle within a range that does not cause visual inconvenience. It is an object of the present invention to provide a display device capable of performing effective and high-speed drawing processing.

[Summary of the invention]

The present invention provides a timer circuit that performs a timer count operation according to the parameter by setting a parameter for setting the flash time, and the output of this timer circuit enables the flash mode and one cycle. By switching between the cycle that displays the image and the flashless mode that is divided into drawing cycles, drawing is performed in flash mode within a range that does not cause visual inconvenience, increasing the speed of drawing processing without causing flickering. It was measured.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention. In the figure,
This is a microprocessor (CPU) that controls the entire IVi display device. 2 welfare microprocessor 1
Data bus driver J (BD
). A data bus driver (BD) 3 is used for data transfer when the microprocessor 1 reads data from the plain memory. 4 is a plain memory (PL, ANE MORY) for storing image data. A 7-foot register (SHR) 5 converts parallel data read from the plane memory into serial data and outputs it as a video signal (VID). 6 is an address latch register (ADL) used when the microprocessor 1 accesses the plain memory 4. A CRT controller (hereinafter referred to as CRTC) 7 controls the display of the plain memory 4.

8 is a path driver (BD
). 9 is the timing of the entire device = + 7) o
- It is a timing control circuit (TC) that performs the following. 10 is a timer circuit (TM) that determines the flash mode time, and 11 is a control circuit (SC) that switches the timing of the flashless mode and flash mode depending on the presence or absence of an overflow signal 110 from the timer circuit 10. .

Also, the data bus of the 100#''i microprocessor 1,
10 is a data bus used for transferring the output data of the plain memory 4, 102 is a data bus used for transferring the write data of the plain memory 4, and 1θ3 is a serial number converted into serial by the shift register 5. This is display data, that is, a video signal (VID). 104 is an address bus of the plain memory 4, 105 is a CRT address bus of the CRTC 7 that outputs the display address of the plain memory 4, 106 is a wait signal (WAIT) to the microprocessor 1, and 107 is an enable signal (ENA) of the address latch register 6. -J), 10B is the enable signal (ENA-) of the data bus driver 2), 109 is the basic clock of the CRTC 7, an overflow signal of the 110-digit timer circuit 10, 111 is the enable signal (ENA, 3) of the path driver 8, 1121ri plain memory 4
write signal to, 113 is address latch signal, 1 to 4
is a memory request to plain memory 4, 4F<, 1
15 is the basic tarok of the microprocessor 1.

Figures 2 and 3 are time charts for explaining the operation of one embodiment, respectively, and Figure 2 shows the operation timing in flashless mode, which is time-divided into cycles that display one cycle and drawing cycles. , FIG. 3 shows the operation timing in flash mode.

Here, the operation of one embodiment will be explained. First, the operation in the flashless mode will be explained with reference to the time chart in FIG. At this time, the microprocessor 1 has set the flashless mode, and the timer circuit 10 is set with a parameter (for example, FF) that causes the overflow signal 110 to be generated. When the overflow signal 110 is generated, under the timing control of the timing control circuit 9,
Flashless mode operation is performed. That is, one cycle is divided into a display cycle and a drawing cycle, and in the display cycle, the CRTC 7
Output to T address bus 105. This display address is input to the path driver 8 and enabled-H (ENA
-3) When 111 is low level, address bus 10
4 and becomes an address signal for the plain memory 4. The display data read by this display address is
After being outputted to the data bus 1θ1 and latched into the shift register 5, it is converted into a Harareru7 real signal, and is output to the CR (not shown) as serial display data (VID) J o a.
The signal is sent to the T display section.

Next, the operation of the drawing cycle in which the microprocessor 1 writes an image to the plain memory 4 will be described. The microprocessor 1 has a basic clock 1 shown in FIG.
15, address data is output to the data bus 100 at the TI, and this is sent to the address latch signal 11.
3, it is latched into the address latch register 6.

T! Then, write data is output to the data bus 100, and a memory request signal 114 is also output. When this memory request signal 114 is input to the timing control circuit 9, a wait signal (WAIT) 1o
e is output and input to the microprocessor zK.

One microprocessor enters a wait state by the above wait signal 106. This is because when the microprocessor 1 accesses the plane memory 4, only the drawing cycle is valid, so synchronization is necessary, so the wait signal 106 is used to achieve synchronization. Furthermore, since the memory request signals 1 and 4 are also input to the control circuit 11, in the drawing cycle, the contents of the address latch register 6 are the inverted memory request signal 114 and the enable signal (ENA-3) 111. NA
NDj is output onto the address bus 104 by the enable signal 107, and becomes the address of the plain memory 4. At the same time, the data bus driver 2 also generates an enable signal (ENA-2) which is obtained by NANDing a signal obtained by inverting the memory request signal 114 and the enable signal 11.
) 708, is output onto the write data bus 102, and becomes the write data of the plain memory 4. Then, it is made into the plain memory 4 by the write signal 112.

When the wait signal 106 is released at point A during the drawing cycle, the microprocessor 1 proceeds to the next cycle T4 and completes the sequence. Point A may be any point where the write data on the data bus 102 satisfies the hold time for the write signal 112.

Next, the operation of the flash mode, which is the gist of the present invention, will be explained with reference to FIG.

For example, the micro processor 1 sets a parameter (for example, OF#) in the timer circuit 10 to enter the flash mode for 10 m5ec. To explain, address data is outputted from the microprocessor 1 to the data bus 100 at timing T1, and is clocked into the address latch register 6 by the address latch signal 113. Next, the memory request signal 114 is output at T2. When this memory request signal 114 is input to the timing control circuit 9, since the overflow signal 110 has not yet been generated from the timer circuit 10, the wait signal 106 is not generated. Furthermore, the memory request signal 114 is selected from the enable signal (ENA-1) J07 and the enable signal (ENA-2) 7os output from the control circuit 1.

(In flash mode, memory request signal 1
14 and enable signal I J 1 fcNAND L
signal was selected). Also, enable signal 1
11 is always at a high level. And Ts
, T4, and write to the plane memory 4 with Q1 and 2.

In this way, the image can be drawn in the plain memory 4 without 1 wait, thereby increasing the drawing speed. Then, after 10 mIIec, when the overflow signal 110 from the timer circuit 10 is generated, 1
It goes into flashless mode and seems to be under weight.

By adopting the display control of the embodiment by switching between the flashless mode and the flash mode as described above, when clearing the screen, there is no need to display anything on the monitor, so the screen can be cleared quickly in the flash mode. can.

Furthermore, by using the timer circuit 10, drawing can be performed in flash mode for a period of time that does not feel unnatural to the eye, thereby increasing the drawing speed.

〔Effect of the invention〕

As described in detail above, according to the display device of the present invention, by setting the flash parameter for setting the flash time, the flash mode is activated by the output of the timer circuit that performs the timer counting operation according to the flash parameter. By adopting a configuration that switches between a cycle that displays one cycle and a flashless mode that is divided into drawing cycles, flashing is minimized to the extent that it causes visual inconvenience.
By drawing according to the mode, you can increase the drawing processing speed without feeling any flickering.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
and FIG. 3 are time charts for explaining the operation of the above embodiment, respectively. 1...Micro! Rosset-f (CPU), 2. a
, s...Path driver (BD), 4...Plane memory (PLANE MEMORY) 1.5 = Shift register (SHR\6, Address latch register (A)
DLχ7...CRT controller (CRTC＼9・
...Timing control circuit (TCClO2/timer circuit, No. 1...Control circuit (SC). Representative of dispatcher Patent attorney Takehiko Suzue Director of Special γM
Manabu Shiga 1. Indication of the case Japanese Patent Application No. 59-135953 2, Indication of the name of the invention Indication W 3. Relationship with the case by the person making the amendment Patent applicant Alpha Power Toshiba Corporation 4, Agent

Claims (1)

[Claims] 1. A display device of a line scanning type that switches the access timing of a plain memory between a flash mode and a flashless mode, the display device being equipped with a timer circuit for determining a flash time.