JPS61148557A - デ−タ伝送方式 - Google Patents

デ−タ伝送方式

Info

Publication number
JPS61148557A
JPS61148557A JP59272547A JP27254784A JPS61148557A JP S61148557 A JPS61148557 A JP S61148557A JP 59272547 A JP59272547 A JP 59272547A JP 27254784 A JP27254784 A JP 27254784A JP S61148557 A JPS61148557 A JP S61148557A
Authority
JP
Japan
Prior art keywords
microcomputer
data
transfer
clock
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59272547A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0571978B2 (cg-RX-API-DMAC7.html
Inventor
Mitsuru Sato
満 佐藤
Yosuke Otsu
大津　要介
Takashi Masuda
孝 増田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59272547A priority Critical patent/JPS61148557A/ja
Publication of JPS61148557A publication Critical patent/JPS61148557A/ja
Publication of JPH0571978B2 publication Critical patent/JPH0571978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
JP59272547A 1984-12-24 1984-12-24 デ−タ伝送方式 Granted JPS61148557A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59272547A JPS61148557A (ja) 1984-12-24 1984-12-24 デ−タ伝送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59272547A JPS61148557A (ja) 1984-12-24 1984-12-24 デ−タ伝送方式

Publications (2)

Publication Number Publication Date
JPS61148557A true JPS61148557A (ja) 1986-07-07
JPH0571978B2 JPH0571978B2 (cg-RX-API-DMAC7.html) 1993-10-08

Family

ID=17515419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59272547A Granted JPS61148557A (ja) 1984-12-24 1984-12-24 デ−タ伝送方式

Country Status (1)

Country Link
JP (1) JPS61148557A (cg-RX-API-DMAC7.html)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53149706A (en) * 1977-06-02 1978-12-27 Nec Corp Serial data transfer system on timing clock control system
JPS5954355A (ja) * 1982-09-22 1984-03-29 Sanyo Electric Co Ltd デ−タ転送方式

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53149706A (en) * 1977-06-02 1978-12-27 Nec Corp Serial data transfer system on timing clock control system
JPS5954355A (ja) * 1982-09-22 1984-03-29 Sanyo Electric Co Ltd デ−タ転送方式

Also Published As

Publication number Publication date
JPH0571978B2 (cg-RX-API-DMAC7.html) 1993-10-08

Similar Documents

Publication Publication Date Title
US6282598B1 (en) PCI bus system wherein target latency information are transmitted along with a retry request
JPS61148557A (ja) デ−タ伝送方式
JP2583602B2 (ja) マルチプロセッサシステムにおけるデバッグ装置
EP0180299A2 (en) Error detection system for a data processing apparatus
JP2767990B2 (ja) マイクロプロセッサの制御方法
JP2893897B2 (ja) シリアル入出力装置
JPH01137353A (ja) インタフエース回路
JPS61190669A (ja) テレメ−タリング装置
JPS5844418Y2 (ja) 複数の信号の開始、終了検出装置
JPH10334044A (ja) シリアルインタフェース方法
JPH0756645B2 (ja) データ処理装置
JPH0540658A (ja) 磁気デイスク制御装置
JPS6252641A (ja) プログラムトレ−ス装置
JPH01161472A (ja) マルチプロセツサシステム
JPS58174734U (ja) バス使用権制御回路
JPH03286355A (ja) マイクロコンピュータ
JPS5520507A (en) Data transfer system
JPH01114230A (ja) シリアルデータ伝送方式
JPS6135460U (ja) 変復調装置試験装置
JPS61109154A (ja) 固定デ−タ・レジスタのエラ−検出方式
JPH0719233B2 (ja) 情報処理装置
JPS642972B2 (cg-RX-API-DMAC7.html)
JPS5858650U (ja) プロセッサ間情報転送装置
JPS63216161A (ja) デ−タ転送方式
JPS63198110A (ja) 電子機器の動作速度制御方式

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term