JPS61147549A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the tight adhesive strength and the electric contacting property of a high melting point metal by a method wherein, in the wiring layer of a silicon semiconductor device, an oxide-growing metal layer having the standard free energy smaller than that of SiO2 is provided on the base of the high melting point metal layer. CONSTITUTION:After a field oxide film 2 is formed on a silicon substrate 1, an N<+> layer 4 is formed by implanting arsenic 3. Then, after SiO25 is covered on the whole surface, a layer 6 of 10-500Angstrom in thickness consisting of at least a kind of berylium, magnesium, titanium, zirconium and halfnium is formed on the whole surface as the first metal layer. Also, the second layer 7 consisting of at least a kind of molybdenum, tungsten niobium and tantalum is formed thereon. As a result, the natural oxide film on a silicon semiconductor is reduced to the first layer metal, and a part of the surface of the SiO2 is also reduced, thereby enabling to obtain the excellent tight adhesive strength and the electric contacting property for a high melting point metal.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to improvements in wiring layers of silicon semiconductors.

[Technical background of the invention and its problems]

In silicon semiconductors, wiring made of aluminum-silicon alloys has been used for a long time. However, in recent years, semiconductor devices, especially integrated circuits, have become increasingly finer, and aluminum alloys have become problematic in terms of reliability. For example, in aluminum alloys, there is a problem of contact penetration to an n-type semiconductor layer having a depth of 0.15 μm or less, and there is also a problem of disconnection of aluminum or its alloy wiring layer over time due to electromigration. The reason for this is that aluminum has a low melting point (660°C).

In response, attempts have been made to use high melting point metals in place of aluminum alloys. However, due to the natural oxide film that inevitably forms on the surface of silicon semiconductors, the electrical contact between the silicon semiconductor and the high-melting point metal wiring is often poor, and it is also commonly used as an insulating film for silicon semiconductors. It is often observed that the high melting point metal layer formed on the Sin film peels off due to poor adhesion. This defect is not observed in aluminum-based alloys because the standard free energy of formation of M, 01 is small compared to sio, and therefore, natural oxide films and S10. This is because the surface of the insulating film is reduced.

[Purpose of the invention]

The object of the present invention is to improve the drawbacks of the above-mentioned high melting point metal wiring and to achieve highly reliable miniaturized wiring technology.

[Summary of the invention]

The present invention provides a metal layer that generates an oxide with a smaller standard free energy of formation under the high-melting point metal layer, thereby improving poor electrical contact and poor adhesion, which are the drawbacks of high-melting point metals. It is something. It is desirable that the first layer metal has the minimum thickness necessary to achieve the above objective. This is because these elements are extremely reactive, and since they are processed by photolithography through the upper metal layer, if the etching speed is different from that of the upper metal layer, the upper metal layer may recede or the lower metal layer may undergo so-called undercuts. This is because this is likely to occur.

Furthermore, it goes without saying that the first layer metal has strong oxidizing properties, and oxides formed on its surface cause poor electrical contact between the first and second metal layers. Therefore, in the present invention, after forming the first metal layer in vacuum, the second metal layer must be formed without contact with the air or oxidizing atmosphere.
The normal electron beam melting and evaporation method and the sputtering method are conceivable.

〔Effect of the invention〕

According to the present invention, the natural oxide film on the silicon semiconductor is reduced to the first layer metal, and good electrical contact can be obtained. Also,
On StO, a part of the surface is reduced to improve adhesion. They have the same effect as when aluminum or its alloy is used for wiring.

In addition, most of the electrical properties are determined by the upper and second metal layers, and when tungsten is used as the second metal layer, electromigration can be virtually ignored due to its high melting point (3380°C), and aluminum Although it is inferior to the system, relatively low resistance wiring can be obtained.

[Embodiments of the invention]

The steps of an embodiment of the present invention are shown in FIG. First, as a normal process, a field oxide film 2 is formed on an NFI substrate 1 (FIG. 1(a)). Next, arsenic 3 is implanted to partially form an n+ layer 4 with a surface arsenic concentration of lXl0''/crd (Fig. 1(b)).
10. Cover with 5.

Next, a part of the n+ layer was etched using photolithography.
A hole is made in layer 5 (FIG. 1(C)). As the first layer metal・
・Funium layer 6 is formed by 50X argon sputtering method, and subsequently, tungsten layer 7 of about 2000λ is formed in the same vacuum chamber (Fig. 1(d)). - A wiring layer is formed by ion etching and heat treated at 400°C for 30 minutes (Fig. 1(e)).

FIG. 2 shows an I.7 curve between an electrode (tungsten in the example) and a substrate of a prototype semiconductor device obtained through the process described above in FIG. FIG. 3 shows a measurement example of conventional tungsten-only wiring for comparison. Tungsten-n
Nonlinearity is observed, which is thought to be due to the natural oxide film at the interface of the + layer.

In addition, if hafnium has a film thickness of 101 or more, it is 8i0□
No peeling phenomenon of tungsten was observed.

Although the above-described embodiments have been shown as extremely simple examples, the present invention can be used in fine and complex integrated circuits. Further, when the present invention is applied to multilayer wiring, the same effect can be obtained on the oxide on the first layer wiring. But in this case,
When the first wiring layer of the multilayer wiring is aluminum, no effect can be expected even if titanium is used as the underlying metal layer of the second layer of the multilayer wiring. Perilimu, magnesium, titanium, zirconium, and hafnium are used for the first layer of multilayer wiring, and the second layer
Molybdenum, tungsten, niobium, tantalum can be used for the layer.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an example of the present invention, FIG. 2 is a characteristic diagram showing the IV characteristics according to the present invention, and FIG. 3 is a characteristic diagram showing the IV% characteristics of a comparative example. 0 1...n-type silicon substrate, 2...SiO□ insulating film, 3...
...Arsenic ion, 4...n"Ni%5...CVD-
810° film, 6... Hafnium layer (50λ), 7...
・Tungsten layer (2000λ) 0 Agent Patent attorney Kensuke Chika (and 1 other person) Figure 1?

Claims (2)

[Claims] (1) In forming a wiring layer of a silicon semiconductor device, the wiring layer is made of at least one of beryllium, magnesium, titanium, zirconium, and hafnium, and has a formed film thickness of 10 Å or more and 500 Å or less; , tungsten, niobium, and tantalum. (2) In the semiconductor device according to claim 1, the wiring layer is formed by forming a first layer metal in a vacuum, and then continuously forming a second layer metal in the same vacuum, with the wiring layer being exposed to air in the middle. A semiconductor device characterized in that it is provided by a formation method that does not touch the semiconductor device.