JPH0582968B2 - - Google Patents
Info
- Publication number
- JPH0582968B2 JPH0582968B2 JP61061981A JP6198186A JPH0582968B2 JP H0582968 B2 JPH0582968 B2 JP H0582968B2 JP 61061981 A JP61061981 A JP 61061981A JP 6198186 A JP6198186 A JP 6198186A JP H0582968 B2 JPH0582968 B2 JP H0582968B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- tungsten
- metal
- opening
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 57
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 30
- 239000010937 tungsten Substances 0.000 claims description 30
- 229910052721 tungsten Inorganic materials 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 239000010955 niobium Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 4
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- LNDHQUDDOUZKQV-UHFFFAOYSA-J molybdenum tetrafluoride Chemical compound F[Mo](F)(F)F LNDHQUDDOUZKQV-UHFFFAOYSA-J 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 13
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 11
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 150000002431 hydrogen Chemical class 0.000 description 6
- 229910000676 Si alloy Inorganic materials 0.000 description 5
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は、半導体装置の製造方法にかかわり、
特に半導体もしくは金属表面との接続部をタング
ステンなどの金属膜で埋め込んだ配線を有する半
導体装置の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device,
In particular, the present invention relates to a method of manufacturing a semiconductor device having wiring in which a connection portion with a semiconductor or metal surface is embedded with a metal film such as tungsten.
(従来の技術)
従来、半導体装置において、例えば、下層素子
の電極配線と上層配線を形成する方法として、ス
パツタ法で金属又は金属硅化物を被着し、行なつ
ていた。この方法を第4図を参照して説明する。
つまり、基板20に形成したN+又はP+シリコン
配線層21上に絶縁膜として例えばSiO2膜22
に開孔部23すなわちスルーホールを形成する
(第4図a)。しかる後に、D.C.マグネトロン・ス
パツタ法で、タングステン膜24を形成する(第
4図b)。スパツタ法での膜形成の場合、基本的
に膜形成速度がスパツタ粒子の供給量で律速され
るため、段差肩部のような、スパツタ粒子に対す
る見込角の大きい領域では成長速度が大きく、開
孔部内部では、見込角が小さいため成長速度が遅
い。そのため第4図bのような、オーバーハング
生じ、開孔部に空洞が生ずる。(Prior Art) Conventionally, in a semiconductor device, for example, electrode wiring of a lower layer element and upper layer wiring have been formed by depositing metal or metal silicide by a sputtering method. This method will be explained with reference to FIG.
That is, for example, a SiO 2 film 22 is formed as an insulating film on the N + or P + silicon wiring layer 21 formed on the substrate 20.
An opening 23, that is, a through hole is formed in (FIG. 4a). Thereafter, a tungsten film 24 is formed by DC magnetron sputtering (FIG. 4b). In the case of film formation using the sputtering method, the film formation rate is basically determined by the amount of sputtered particles supplied, so the growth rate is high in areas where the angle of view to the sputtered particles is large, such as at the shoulder of a step, and the pores are less likely to open. Inside the area, the growth rate is slow because the prospect angle is small. As a result, an overhang occurs as shown in FIG. 4b, and a cavity is formed in the opening.
上記問題点を克服する方法として、水素と六フ
ッ化タングステン気体を用いて化学気相堆積法で
タングステン膜を形成する方法が考えられた。こ
の方法を採用する事により第5図に示すように段
差部でのオーバーハングが生じなくなる。しかし
ながらタングステン膜25と下層酸化膜22は密
着性が弱く、タングステン膜25と基板の間の応
力に耐えられずはがれなどが、頻繁に起こり、同
図に示すような空洞26が生ずるため、タングス
テン膜25の表面形状は、平坦性を失い、その後
のパターン加工を困難にする。又、はがれが起こ
らないようにタングステンを薄膜化すると、開孔
部の中心部は、凹部となり、上層に絶縁膜を被着
して、その開孔部の直上に第2の開孔部を形成す
る場合、局所的に絶縁膜厚が異なるため、均一な
エツチングが困難であり、接続部が接触不良とな
りうる。 As a method to overcome the above problems, a method has been considered in which a tungsten film is formed by chemical vapor deposition using hydrogen and tungsten hexafluoride gas. By adopting this method, no overhang occurs at the stepped portion as shown in FIG. However, the adhesion between the tungsten film 25 and the lower oxide film 22 is weak, and the tungsten film 25 cannot withstand the stress between the substrate and peels off frequently, resulting in the formation of cavities 26 as shown in the figure. The surface shape of No. 25 loses flatness and makes subsequent pattern processing difficult. Furthermore, if the tungsten film is thinned to prevent peeling, the center of the opening becomes a recess, and an insulating film is deposited on the upper layer to form a second opening directly above the opening. In this case, since the thickness of the insulating film differs locally, it is difficult to perform uniform etching, which may result in poor contact at the connection portion.
(発明が解決しようとする問題点)
本発明は上記問題点を考慮してなされたもの
で、酸化膜等の絶縁膜に設けられたコンタクトホ
ールあるいはスルーホールのような開孔部及び前
記絶縁膜上に及ぶタングステン等の金属膜パター
ンを形成する方法において、この金属膜と酸化膜
とのはがれを生じない半導体装置の製造方法を提
供することを目的とする。(Problems to be Solved by the Invention) The present invention has been made in consideration of the above-mentioned problems. An object of the present invention is to provide a method for manufacturing a semiconductor device in which peeling of the metal film and oxide film does not occur in a method of forming a pattern of a metal film such as tungsten that extends over the top.
(問題点を解決するための手段)
本発明は上記目的を達成するために半導体若し
くは、金属表面上に絶縁膜を形成し、該絶縁膜に
前記半導体若しくは、金属の一部が露出するよう
に開孔部を設ける工程と、その後前記絶縁膜と密
着性の良い第1の金属膜を前記開孔部及び絶縁膜
上に化学気相堆積法で被着する工程と、続いて第
2の金属膜を前記第1の金属膜上の全面に化学気
相堆積法で形成して前記開孔部を埋め込む工程
と、しかる後に前記第1及び第2の金属膜を配線
パターンに加工する工程とを具備する半導体装置
の製造方法を提供する。
(Means for Solving the Problems) In order to achieve the above object, the present invention forms an insulating film on the surface of a semiconductor or metal, and exposes a part of the semiconductor or metal to the insulating film. a step of providing an aperture, then a step of depositing a first metal film having good adhesion to the insulating film on the aperture and the insulating film by a chemical vapor deposition method; forming a film on the entire surface of the first metal film by chemical vapor deposition to fill the opening; and then processing the first and second metal films into a wiring pattern. A method of manufacturing a semiconductor device is provided.
(作用)
本発明によれば酸化膜等の絶縁膜に形成した開
孔部に埋め込むタングステン等の第2の金属膜と
前記絶縁膜との間にこの絶縁膜と密着性の良い第
1の金属膜を介在させるので絶縁膜表面の金属膜
のはがれや開口部の隙間が生ずることがない。(Function) According to the present invention, a first metal having good adhesion to the insulating film is placed between the second metal film, such as tungsten, and the insulating film, which is embedded in the opening formed in the insulating film, such as an oxide film. Since the film is interposed, peeling of the metal film on the surface of the insulating film and gaps between the openings will not occur.
また、本発明によれば第1及び第2の金属膜を
化学気相堆積法により形成するため、段差部での
オーバーハングが生じなくなり、したがつて開孔
部を埋めるに十分な膜厚の金属膜を堆積しても、
その金属膜の表面を平坦化することができ、この
ためこれを配線パターンに加工することができ
る。 Further, according to the present invention, since the first and second metal films are formed by chemical vapor deposition, overhangs do not occur at stepped portions, and therefore the film thickness is sufficient to fill the openings. Even if a metal film is deposited,
The surface of the metal film can be flattened, and therefore it can be processed into a wiring pattern.
一方、開口部側壁に金属膜を形成し、埋めるべ
き開孔部寸法を縮小することにより、埋め込みに
必要な最小金属膜厚が減少し、したがつて配線間
容量も減少する。 On the other hand, by forming a metal film on the side wall of the opening and reducing the size of the opening to be filled, the minimum metal film thickness required for filling is reduced, and therefore the capacitance between wirings is also reduced.
(実施例)
以下、本発明による半導体装置の製造方法の実
施例について説明する。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device according to the present invention will be described.
まず本発明の第1の実施例を第1図を参照して
説明する。第1図aの如く5ΩcmのP型(100)シ
リコン基板16に形成したヒ素(As)高濃度ド
ーピング層10の上に絶縁膜として約1.2μmのSi
O2膜11を常圧CVD法で形成した後、反応性イ
オンエツチング等により所望の場所に直径0.4μm
の開孔部15を設ける。次に第1図bの如く650
℃の減圧CVD装置内において分圧0.15Torrで水
素(H2)を、分圧0.05TorrでTic4を導入し、
約200Åの第1の金属膜であるチタン(Ti)膜1
2を被着し、続いて装置内を排気した後、基板温
度400℃,分圧0.2Torrで水素(H2)を、分圧
0.03Torrで六フツ化タングステン(WF6)を導
入し第2の金属膜であるタングステン膜13を
0.2〜0.3μm堆積して開孔部15を埋め込んだ。こ
の後、チタン膜12、タングステン膜13を所望
の配線パターンに加工する事によつて上層配線及
び埋込部配線の同時形成が実現される(第1図
b)。 First, a first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1a, an approximately 1.2 μm Si insulating film is formed on the arsenic (A s ) heavily doped layer 10 formed on a 5 Ωcm P-type (100) silicon substrate 16 .
After forming the O 2 film 11 by atmospheric pressure CVD method, it is etched at a desired location with a diameter of 0.4 μm by reactive ion etching, etc.
An opening 15 is provided. Next, 650 as shown in Figure 1 b.
Hydrogen (H 2 ) was introduced at a partial pressure of 0.15 Torr and Tic 4 was introduced at a partial pressure of 0.05 Torr in a reduced pressure CVD device at ℃.
Titanium (Ti) film 1 which is the first metal film with a thickness of about 200 Å
2, and after evacuating the inside of the device, hydrogen (H 2 ) was applied at a substrate temperature of 400°C and a partial pressure of 0.2 Torr.
Tungsten hexafluoride (WF 6 ) is introduced at 0.03 Torr to form the tungsten film 13, which is the second metal film.
The openings 15 were filled by depositing 0.2 to 0.3 μm. Thereafter, by processing the titanium film 12 and the tungsten film 13 into a desired wiring pattern, simultaneous formation of the upper layer wiring and the buried wiring is realized (FIG. 1b).
シリコン基板とのコンタクト抵抗を測定すると
1×10-6Ωcm2で電流−電圧特性は良好なオーミツ
ク性を示した。 When the contact resistance with the silicon substrate was measured, it was 1×10 -6 Ωcm 2 and the current-voltage characteristics showed good ohmic properties.
尚、上述した実施例では、第1の金属膜として
チタン膜12を形成した例を示したが、これに代
えてタングステン−シリコン合金膜を形成するこ
ともできる。この合金膜は、上記実施例に於い
て、第1図aに示すようにSiO2膜11の所望の場
所に開孔部15を形成した後、減圧CVD装置内
において、400℃のシリコン半導体基板に分圧
0.06Torrで水素(H2)を、0.12TorrでSiH4を、
0.001Torrで六フツ化タングステン(WF6)を導
入し、シリコン成分が過剰なタングステン−シリ
コン合金膜を500Å被着することにより形成され
る。この後は、第1の実施例と同様に分圧
0.2Torrで水素(H2)を、0.03Torrで六フッ化タ
ングステン(WF6)を導入することにより第2
の金属膜としてタングステン膜13を0.3μm堆積
する。この後配線加工を行なえば、前述チタン膜
の場合と同様な効果が得られる。 In the above embodiment, the titanium film 12 was formed as the first metal film, but a tungsten-silicon alloy film may be formed instead. In the above embodiment, after forming the openings 15 at desired locations in the SiO 2 film 11 as shown in FIG. Partial pressure on semiconductor substrate
Hydrogen (H 2 ) at 0.06 Torr, SiH 4 at 0.12 Torr,
It is formed by introducing tungsten hexafluoride (WF 6 ) at 0.001 Torr and depositing a 500 Å tungsten-silicon alloy film with an excessive silicon content. After this, the partial pressure is changed as in the first embodiment.
By introducing hydrogen (H 2 ) at 0.2 Torr and tungsten hexafluoride (WF 6 ) at 0.03 Torr, the second
A tungsten film 13 with a thickness of 0.3 μm is deposited as a metal film. If wiring is processed after this, the same effect as in the case of the titanium film described above can be obtained.
上述したように、本発明による方法を用いれば
膜はがれ及び膜はがれによるSiO2膜11の凹凸は
なく、スルーホール又はコンタクトホール等の開
孔部15にも隙間はなく信頼性良く開孔部15を
埋め込むことができた。 As mentioned above, if the method according to the present invention is used, there will be no film peeling or unevenness of the Si O 2 film 11 due to film peeling, and there will be no gaps in the openings 15 such as through holes or contact holes, and the holes can be opened with good reliability. I was able to embed part 15.
次に本発明の第2の実施例としてSiO2膜に開孔
部を形成した後、この開孔部にフツ化物気体で反
応させた金属層を形成する工程を含む製造方法を
第2図を用いて説明する。 Next, as a second embodiment of the present invention, a manufacturing method including a step of forming an opening in a Si O 2 film and then forming a metal layer reacted with a fluoride gas in the opening is performed. This will be explained using figures.
まず、第2図aの如く、5ΩcmのP型(100)シ
リコン基板1にヒ素(As)を30KeVで3×1015
cm-2注入し、900℃で40分の熱処理を行ないN+拡
散層2を形成した後、六フツ化タングステン
(WF6)とアルゴン(Ar)を用いて基板温度400
℃、圧力0.2Torrの圧力下で約500Åのタングス
テン配線層3を化学気相堆積法により形成する。
次に0.35Torrの圧力下でSiH4とN2Oを用いて約
1.2μmの絶縁膜としてSiO2膜11を被着して、そ
の後直径0.4μmの開孔部15を反応性イオンエツ
チング等により形成する。その後、基板1の温度
600℃で0.1μmの多結晶シリコン膜4を減圧化学
気相堆積法(CVD法)を用いて開孔部15及び
SiO2膜11上に被着する。しかる後、第2図bの
如くBBr3−C2等の塩素系気体を用いた反応性
イオンエツチングで異方的に多結晶シリコン4を
全面エツチングして、開孔部15側壁にシリコン
膜4aを残す。続いて圧力0.2Torr、基板1の温
度400℃でタングステンのフツ化物気体である六
フツ化タングステン(WF6)とアルゴン(Ar)
を流し、前記シリコン膜4aで六フツ化タングス
テン(WF6)を還元し、側壁部シリコン膜4a
をすべて第2図cに示す如くタングステン膜5に
置換する。0.1μmのシリコン膜4aがすべて六フ
化タングステン(WF6)と反応すると約500Åの
タングステン膜5が形成される。 First, as shown in Figure 2a, arsenic (As) is applied to a 5Ωcm P-type (100) silicon substrate 1 at 30KeV in a 3×10 15
After implanting cm -2 and performing heat treatment at 900°C for 40 minutes to form the N + diffusion layer 2, the substrate temperature was increased to 400°C using tungsten hexafluoride (WF 6 ) and argon (Ar).
A tungsten wiring layer 3 of about 500 Å is formed by chemical vapor deposition at a temperature of 0.2 Torr.
Next, using S i H 4 and N 2 O under a pressure of 0.35 Torr, approx.
A SiO 2 film 11 is deposited as an insulating film with a thickness of 1.2 μm, and then an opening 15 with a diameter of 0.4 μm is formed by reactive ion etching or the like. After that, the temperature of the substrate 1 is
A polycrystalline silicon film 4 with a thickness of 0.1 μm is deposited on the openings 15 and 4 using low pressure chemical vapor deposition (CVD) at 600°C.
It is deposited on the S i O 2 film 11 . Thereafter, as shown in FIG. 2b, the entire polycrystalline silicon 4 is anisotropically etched by reactive ion etching using a chlorine gas such as BBr 3 -C 2 to form a silicon film 4a on the side wall of the opening 15. leave. Next, tungsten hexafluoride (WF 6 ), which is a tungsten fluoride gas, and argon (Ar) were heated at a pressure of 0.2 Torr and a substrate 1 temperature of 400°C.
The silicon film 4a is used to reduce tungsten hexafluoride (WF 6 ), and the side wall silicon film 4a is reduced.
are all replaced with a tungsten film 5 as shown in FIG. 2c. When all of the 0.1 μm silicon film 4a reacts with tungsten hexafluoride (WF 6 ), a tungsten film 5 of about 500 Å is formed.
しかる後に、第2図dに示すように減圧CVD
装置内において基板温度を400℃にして分圧
0.06Torrで水素(H2)を、0.12TorrでSiH4を、
0.001Torrで六フツ化タングステン(WF6)を導
入し、第1の金属膜である500Åのシリコン成分
過剰のタングステン−シリコン合金膜12を、続
いて分圧0.2Torrで水素(H2)を、0.03Torrで六
フツ化タングステン(WF6)を導入して0.1μmの
第2の金属膜、ここではタングステン膜13を堆
積する。そしてこの積層膜12,13をパターニ
ングする。 After that, reduced pressure CVD is performed as shown in Figure 2d.
Temperature of the substrate is 400℃ inside the device and partial pressure is applied.
Hydrogen (H 2 ) at 0.06 Torr, S i H 4 at 0.12 Torr,
Tungsten hexafluoride (WF 6 ) was introduced at a pressure of 0.001 Torr, and a tungsten-silicon alloy film 12 with an excess silicon content of 500 Å was formed as the first metal film, followed by hydrogen (H 2 ) at a partial pressure of 0.2 Torr. Tungsten hexafluoride (WF 6 ) is introduced at 0.03 Torr to deposit a 0.1 μm second metal film, here the tungsten film 13. Then, the laminated films 12 and 13 are patterned.
この実施例によれば第1の金属膜であるタング
ステン−シリコン合金膜12、第2の金属膜であ
るタングステン膜13の膜厚を金属膜5の膜厚分
薄くすることができるので、パターニングの際に
エツチングが容易であり、又、膜はがれ及びこの
膜はがれによるSiO2膜11の凹凸はみられず、開
孔部15にも隙間は見られず、信頼性良く開孔部
15の埋め込みを行なうことができた。 According to this embodiment, the thickness of the tungsten-silicon alloy film 12, which is the first metal film, and the tungsten film 13, which is the second metal film, can be made thinner by the thickness of the metal film 5. Etching is easy, and there is no peeling of the film or unevenness of the S i O 2 film 11 due to peeling of the film, and no gaps are found in the openings 15, so the openings 15 can be reliably etched. I was able to embed it.
タングステン配線層3と高濃度ヒ素(As)ド
ーピングシリコン層2との接触抵抗は5×10-7Ω
cm2と良好なオーミツク特性を示した。 The contact resistance between the tungsten wiring layer 3 and the highly concentrated arsenic (As) doped silicon layer 2 is 5×10 -7 Ω.
cm 2 and showed good ohmic properties.
以上説明した様に本発明によれば金属膜にはが
れが生じないので配線のパターン加工が確実であ
る。また、表面が平坦であるのでプロセス信頼性
にも優れている。例えば全体にCVD酸化膜を形
成し、前記コンタクトホールに重ねてスルーホー
ルを形成して更に上層配線層を設けても、下層配
線12,13との間で接触不良を起すことはな
い。また、開孔部15側壁に金属膜5を形成すれ
ば、埋込みに必要な金属膜の膜厚が小さくて済む
ため配線のパターン加工が容易で、配線間容量も
減少できる。 As explained above, according to the present invention, the metal film does not peel off, so that wiring pattern processing can be performed reliably. Furthermore, since the surface is flat, process reliability is also excellent. For example, even if a CVD oxide film is formed on the entire surface, through holes are formed over the contact holes, and an upper wiring layer is further provided, contact failure with the lower wirings 12 and 13 will not occur. Furthermore, if the metal film 5 is formed on the side wall of the opening 15, the thickness of the metal film required for embedding can be reduced, making it easy to pattern the wiring and reducing the capacitance between the wirings.
尚、上述した第2の実施例において、タングス
テン配線層3を形成しない場合、即ち、N+拡散
層2上に直接SiO2膜11が形成される場合でも、
同様な効果が得られる。この場合、最終的に得ら
れる構造は第3図に示される。ここで第2図と同
一部分は同一符号で示されている。 In the second embodiment described above, even when the tungsten wiring layer 3 is not formed, that is, even when the S i O 2 film 11 is formed directly on the N + diffusion layer 2,
A similar effect can be obtained. In this case, the final structure obtained is shown in FIG. Here, the same parts as in FIG. 2 are indicated by the same symbols.
上記各実施例において、第1の金属としてチタ
ンあるいはタングステン−シリコン合金、第2の
金属としてタングステンを用いたが、本発明はこ
れらに限定されるものではなく第1の金属として
はチタン(Ti)、ジルコニウム(Zr)、ハフニウ
ム(Hf)、ニオブ(Nb)、タンタル(Ta)、及び
これらの硅化物(シリコンとの合金)、窒化物、
又はモリブデン(Mo)、タングステン(W)の
硅化物であつてもよく、第2の金属としては、タ
ングステン(W)以外にモリブデン(Mo)ある
いはそれらの硅化物であつても同様の効果が得ら
れる。又、第2図及び第3図に示される実施例で
は開孔部15側壁に形成する金属としてタングス
テンを用いたがモリブデンであつてもよい。 In each of the above examples, titanium or a tungsten-silicon alloy was used as the first metal, and tungsten was used as the second metal, but the present invention is not limited to these, and titanium (Ti) was used as the first metal. , zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), and their silicides (alloys with silicon), nitrides,
Alternatively, it may be a silicide of molybdenum (Mo) or tungsten (W), and the same effect can be obtained even if the second metal is molybdenum (Mo) or a silicide thereof in addition to tungsten (W). It will be done. Further, in the embodiment shown in FIGS. 2 and 3, tungsten is used as the metal formed on the side wall of the opening 15, but molybdenum may also be used.
更に、SiO2膜11の下層はN+あるいはP+のシ
リコン基板もしくはチタン,ジルコニウム,ハフ
ニウム,ニオブ,タンタル,クロム,モリブデ
ン,タングステン及びこれらの硅化物又は窒化
物、あるいは、ニツケル,パラジウム,プラチナ
及びこれらの硅化物、あるいはアルミニウム,銅
を主成分とする金属膜のいずれでもよい。 Further, the lower layer of the Si O 2 film 11 is made of an N + or P + silicon substrate, titanium, zirconium, hafnium, niobium, tantalum, chromium, molybdenum, tungsten and their silicides or nitrides, or nickel, palladium, It may be a metal film mainly composed of platinum and silicides thereof, or aluminum or copper.
以上、述べてきたように本発明によれば絶縁膜
に形成したコンタクトホールあるいはスルーホー
ル等の開孔部をタングステン等の金属膜で埋め込
むに際し、この金属膜と前記絶縁膜との間にこの
絶縁膜と密着性の良い第1の金属膜を介在させる
ので金属膜のはがれが生ぜずパターン加工が確実
に行なえる。
As described above, according to the present invention, when filling an opening such as a contact hole or a through hole formed in an insulating film with a metal film such as tungsten, an insulating film is formed between the metal film and the insulating film. Since the first metal film having good adhesion to the film is interposed, the metal film does not peel off and pattern processing can be performed reliably.
又、開孔部にも隙間は生じないので平坦性も良
好である。 Furthermore, since no gaps are formed in the openings, the flatness is also good.
一方、開孔部側壁に金属膜を形成し、埋めるべ
き開孔部の面積を縮小させる事により、埋込みに
必要な最小金属膜厚が減少し、従つてパターニン
グが容易となり、また配線間容量も減少する。 On the other hand, by forming a metal film on the side wall of the opening and reducing the area of the opening to be filled, the minimum metal film thickness required for filling is reduced, making patterning easier and reducing the capacitance between interconnects. Decrease.
第1図は本発明の一実施例を示す工程断面図、
第2図及び第3図は本発明の他の実施例を示す工
程断面図、第4図及び第5図は従来例を示す工程
断面図である。
1,16,20……シリコン基板、2,10,
21……N+又はP+拡散層、3……下層金属配
線、11,22……絶縁膜、12……第1の金属
膜、13……第2の金属膜、15,23……開口
部、4,4a……導電体膜、5……金属膜、2
4,25……金属膜。
FIG. 1 is a process sectional view showing an embodiment of the present invention;
2 and 3 are process sectional views showing another embodiment of the present invention, and FIGS. 4 and 5 are process sectional views showing a conventional example. 1, 16, 20... silicon substrate, 2, 10,
21...N + or P + diffusion layer, 3... Lower metal wiring, 11, 22... Insulating film, 12... First metal film, 13... Second metal film, 15, 23... Opening Part, 4, 4a... Conductor film, 5... Metal film, 2
4,25...Metal film.
Claims (1)
成し、該SiO2膜に前記半導体若しくは、金属の
一部が露出するように開孔部を設ける工程と、次
に該開孔部及びSiO2膜上にシリコン膜を化学気
相堆積法で被着し、該シリコン膜を異方性エツチ
ングで前記開孔部の側壁に自己整合して残置し、
しかる後タングステン又はモリブデンのフッ化物
気体と反応させて前記シリコン膜をタングステン
又はモリブデンの金属膜に置換する工程と、その
後、前記開孔部及びSiO2膜上にチタン、ジルコ
ニウム、ハフニウム、ニオブ、タンタル及びこれ
らの硅化物,窒化物又はタングステン或いは、モ
リブデンの硅化物のいずれかで構成される第1の
金属膜を化学気相堆積法で被着する工程と、続い
てタングステン又は、モリブデン及びこれらの硅
化物のいずれかで構成される第2の金属膜を前記
第1の金属膜上の全面に化学気相堆積法で形成し
て前記開孔部を埋め込む工程と、しかる後に前記
第1及び第2の金属膜を配線パターンに加工する
工程を含むことを特徴とする半導体装置の製造方
法。 2 SiO2膜下の金属が、チタン、ジルコニウム、
ハフニウム、ニオブ、タンタル、クロム、モリブ
デン、タングステン及びこれらの硅化物、又は窒
化物、或はニツケル、パラジウム、プラチナ及び
これらの硅化物或は、アルミニウム、銅を主成分
とする金属のいずれかである特許請求の範囲第1
項記載の半導体装置の製造方法。[Claims] 1. A step of forming an SiO 2 film on the surface of a semiconductor or metal, and providing an opening in the SiO 2 film so that a part of the semiconductor or metal is exposed; depositing a silicon film on the opening and the SiO 2 film by chemical vapor deposition, leaving the silicon film self-aligned with the sidewall of the opening by anisotropic etching;
Thereafter, a step of replacing the silicon film with a tungsten or molybdenum metal film by reacting with a tungsten or molybdenum fluoride gas, and then a step of replacing the silicon film with a tungsten or molybdenum metal film, and then applying titanium, zirconium, hafnium, niobium, tantalum on the opening and the SiO 2 film. and a step of depositing a first metal film composed of any of these silicides, nitrides, tungsten, or molybdenum silicides by chemical vapor deposition, and then a step of depositing tungsten or molybdenum and any of these silicides. forming a second metal film made of one of silicides on the entire surface of the first metal film by chemical vapor deposition to fill the opening; 1. A method for manufacturing a semiconductor device, comprising the step of processing a metal film into a wiring pattern according to step 2. 2 The metal under the SiO 2 film is titanium, zirconium,
Either hafnium, niobium, tantalum, chromium, molybdenum, tungsten and their silicides or nitrides, or nickel, palladium, platinum and their silicides, or metals whose main components are aluminum or copper. Claim 1
A method for manufacturing a semiconductor device according to section 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6198186A JPS62219945A (en) | 1986-03-22 | 1986-03-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6198186A JPS62219945A (en) | 1986-03-22 | 1986-03-22 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62219945A JPS62219945A (en) | 1987-09-28 |
JPH0582968B2 true JPH0582968B2 (en) | 1993-11-24 |
Family
ID=13186865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6198186A Granted JPS62219945A (en) | 1986-03-22 | 1986-03-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62219945A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5149672A (en) * | 1988-08-01 | 1992-09-22 | Nadia Lifshitz | Process for fabricating integrated circuits having shallow junctions |
US4999317A (en) * | 1989-09-29 | 1991-03-12 | At&T Bell Laboratories | Metallization processing |
US5084415A (en) * | 1989-10-23 | 1992-01-28 | At&T Bell Laboratories | Metallization processing |
US5700716A (en) | 1996-02-23 | 1997-12-23 | Micron Technology, Inc. | Method for forming low contact resistance contacts, vias, and plugs with diffusion barriers |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57208161A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Semiconductor device |
JPS61147549A (en) * | 1984-12-21 | 1986-07-05 | Toshiba Corp | Semiconductor device |
JPS61248442A (en) * | 1985-04-26 | 1986-11-05 | Hitachi Ltd | Fine electrode wiring for semiconductor element |
-
1986
- 1986-03-22 JP JP6198186A patent/JPS62219945A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57208161A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Semiconductor device |
JPS61147549A (en) * | 1984-12-21 | 1986-07-05 | Toshiba Corp | Semiconductor device |
JPS61248442A (en) * | 1985-04-26 | 1986-11-05 | Hitachi Ltd | Fine electrode wiring for semiconductor element |
Also Published As
Publication number | Publication date |
---|---|
JPS62219945A (en) | 1987-09-28 |
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