TW388938B - Method for increasing etch selectivity of metal wire - Google Patents

Method for increasing etch selectivity of metal wire Download PDF

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Publication number
TW388938B
TW388938B TW87114178A TW87114178A TW388938B TW 388938 B TW388938 B TW 388938B TW 87114178 A TW87114178 A TW 87114178A TW 87114178 A TW87114178 A TW 87114178A TW 388938 B TW388938 B TW 388938B
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Taiwan
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layer
metal
photoresist layer
etching
metal layer
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TW87114178A
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Chinese (zh)
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Jau-Cheng Chen
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Taiwan Semiconductor Mfg
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Abstract

In an ordinary etching procedure in a production process of an IC metal wire, the photoresist layer used as the mask will be damaged and reduced in thickness during the etching process because the etch selectivity between the metal layer and the photoresist layer is not high. In the past, the size of the device is higher, therefore the properties of the IC will not be affected significantly. However, with the miniaturization of the devices, the thickness of the photoresist layer decreases as well. Gradually, the photoresist layer is no longer capable of providing sufficient anti-etching power. Therefore, the present invention provides an improved method of producing an IC metal wire, which comprises applying a nitrogen plasma treatment procedure on the photoresist layer prior to the etching procedure in order to increase the etch selectivity between the metal layer and the photoresist layer. As a result, the photoresist layer, regardless of a decrease in the thickness thereof along with the miniaturization of the device, can still provide a sufficient etch mask function without affecting the etching effect of the metal wire.

Description

五、發明說明(1) --- 本發明係有關於半導體積體電路的製造,且特別 關於一種積體電路金屬導線的改良製程,利用一氮氣 處理程序以增強光阻層的抗蝕刻能力,可提昇金屬導 刻程序的蝕刻選擇性,適用於尺寸縮小化元件之製程。 眾所皆知,只要是電子元件必然少不了傳輸電流的 屬導線,半導體積體電路亦然,眾多元件必須藉由適當内 連導線的連接方能發揮應有之功效。在半導體積體電路製 程中,鋁金屬由於本身的電阻率(resistivity)頗低且 對氧化矽層的附著情形良好,因此普遍用來作為元件的主 要導電材料’以降低RC時間延遲’並提昇元件的開關 (switching)頻率。不過由於以濺鍍法所沈積的鋁,經回 火(anneal)處理之後,通常是以複晶(p〇ly_crystalUne) 形式存在’而當電流通過鋁金屬時,因為電場的影攀鋁原 子會沿著晶粒境界(grain boundary)移動,造成所謂電致 遷移(electromigration)現象,嚴重者往往造成鋁金屬導 線的斷路。因此目前的製程通常會在鋁中加入少量的銅以 為防制’含量約在0. 5到4%之間,而成為鋁銅合金 (AlCu)。接著,利用一光阻層圖案當作罩幕,對上述鋁銅 合金層施行一蚀刻程序以定義其圖案,即形成所需的内連 導線。 不過,上述傳統钱刻方法存有金屬層與光阻層間的蝕 刻選擇性並不大的潛在問題,並不利於尺寸縮小化元件的 製程。為了進一步了解其問題所在,以下即參照第丨人和⑺ 圖,詳細說明一般形成金屬導線的製程。首先,如第丨九圖V. Description of the invention (1) --- The present invention relates to the manufacture of semiconductor integrated circuits, and in particular to an improved process for metal wires of integrated circuits. A nitrogen treatment process is used to enhance the anti-etching ability of the photoresist layer. It can improve the etching selectivity of the metal guiding process, and is suitable for the process of reducing the size of the component. As everyone knows, as long as the electronic components are inevitable, they must be metal wires that carry current, and so are semiconductor integrated circuits. Many components must be properly connected by connecting the wires to achieve their proper functions. In the process of semiconductor integrated circuits, aluminum metal has a low resistivity and good adhesion to the silicon oxide layer. Therefore, it is generally used as the main conductive material of the component 'to reduce the RC time delay' and improve the component. Switching frequency. However, due to the aluminum deposited by sputtering, after annealing, it usually exists in the form of polycrystalline crystal (polily_crystalUne). When the current passes through the aluminum metal, the aluminum atoms will Moving to the grain boundary causes the so-called electromigration phenomenon. In severe cases, the aluminum metal wire is often broken. Therefore, the current process usually adds a small amount of copper to aluminum in order to prevent the content of about 0.5 to 4%, and it becomes an aluminum-copper alloy (AlCu). Then, using a photoresist layer pattern as a mask, an etching process is performed on the above-mentioned aluminum-copper alloy layer to define its pattern, that is, a required interconnecting wire is formed. However, the above conventional money engraving method has a potential problem that the etching selectivity between the metal layer and the photoresist layer is not large, which is not conducive to the process of reducing the size of the device. In order to further understand the problem, the following is a detailed description of the general process of forming metal wires with reference to Figures 丨 and ⑺. First, as shown in Figure 9

C:\PrograraFiles\Patent\0503-3692-e. ptd第 4 頁 五、發明說明(2) 所示者,提供一半導體基底1〇,例如是一矽晶圓,其上方 可以形成必須的半導體元件,而此處為了簡化起見僅以 一平整的基底10表示之。接著,利用一物理氣相沈積 (PVD)技術’例如是電子束蒸鍵(eiectr〇I1 beam evaporation)程序或是減錄(SpUtterjng)程序,形成一銘 銅合金層11覆蓋於基底1〇上。然後’以旋轉塗佈方法形成 一光阻層12覆蓋在鋁銅合金層11表面上,並以一微影成像 程序定義出覆蓋導線部分的圖案。 接下來’請參見第1B圖’利用上述光阻層12的圖案當 作罩幕’對鋁銅合金層11施行一蝕刻程序,例如是使用含 氣氣體的活性離子蝕刻(RIE)程序,以形成所需的金屬導 線11a。其中,由於鋁銅金屬層與光阻層12間的蝕刻選 擇性不大’因此用來當作罩幕的光阻層也會在蝕刻過程 中耗損’而成為如圖中所示的構造12a。在以往由於元件 的尺寸較大,加上部分被蝕刻的光阻層會反應形成高分子 薄膜13而保護金屬導線11a的側壁,因此尚可彌補光阻層 12抗蚀刻能力的不足,不致於影響元件的性質。然而,隨 著元件尺寸日益縮小化’光阻層12的厚度亦隨之減小,漸 漸地已不能提供足夠的抗蝕刻能力。 第2 A圖和第2 B圖的剖面示意圖,即用以說明此一問 題6首先,如同第1A圖中所述者,以物理氣相沈積技術形 成一鋁銅金屬層21,覆蓋在一半導體基底21上《接著,在 鋁銅金屬層21表面上塗佈一光阻層22,並以一微影成像程 序定義出覆蓋導線部分的圖案》此處為了定義較小尺寸的C: \ PrograraFiles \ Patent \ 0503-3692-e. Ptd page 4 V. Invention description (2) Provide a semiconductor substrate 10, such as a silicon wafer, on which necessary semiconductor elements can be formed For the sake of simplicity, only a flat substrate 10 is used here. Next, a physical vapor deposition (PVD) technique is used, such as an electron beam evaporation (eiectr0I1 beam evaporation) process or a SpUtterjng process, to form a copper alloy layer 11 overlying the substrate 10. Then, a photoresist layer 12 is formed on the surface of the aluminum-copper alloy layer 11 by a spin coating method, and a pattern for covering the wire portion is defined by a lithography imaging program. Next, please refer to FIG. 1B, using the pattern of the photoresist layer 12 as a mask, to perform an etching process on the aluminum-copper alloy layer 11 such as a reactive ion etching (RIE) process using a gas containing gas to form The required metal wire 11a. Among them, since the etching selectivity between the aluminum-copper metal layer and the photoresist layer 12 is not so great ', the photoresist layer used as a mask will also be consumed during the etching process' to become the structure 12a shown in the figure. In the past, due to the large size of the element, and the partially etched photoresist layer will react to form a polymer film 13 to protect the side wall of the metal wire 11a, so it can still make up for the lack of resistance of the photoresist layer 12 to the etch, without affecting the Element properties. However, the thickness of the photoresist layer 12 has been reduced as the size of the device has been reduced, and it has gradually failed to provide sufficient etching resistance. Figures 2A and 2B are schematic cross-sectional views to illustrate this problem. 6 First, as described in Figure 1A, an aluminum-copper metal layer 21 is formed by a physical vapor deposition technique to cover a semiconductor. On the substrate 21 "Next, a photoresist layer 22 is coated on the surface of the aluminum-copper metal layer 21, and a pattern covering the wire portion is defined by a lithography imaging program" Here, in order to define a smaller size

0:\?1*〇£3*3111卩1168\?816111\0503-3692-6.卩七(1第5頁 五、發明說明(3) 金屬導線囷案,光阻層22的厚度也配合減小許多,如第2A 圖所示者。接下來,請參見第2B圖,利用上述光阻層22的 圖案當作罩幕,對鋁銅合金層21施行一蚀刻程序,例如是 使用含氯氣體的活性離子蝕刻(RIE)程序,以期能形成所 需的金屬導線《然而,由於縮小厚度的光阻層22並無法提 供足夠的抗蝕刻能力’因此當蝕刻程序進行到後段時所 有光阻層22已被耗盡,使得剩餘的鋁銅合金層21a無法形 成所需的金屬導線構造。 為了改善上述問題,曾有人提出一種改良的蝕刻方 法’如第2C圓所示者,其在蝕刻氣體中添加所謂的「鈍化 氣體」(passivation gas),例如是HC1、HBr、或CHF3 等 等,藉以減緩光阻層22的損耗,並可形成高分子薄膜來保 護金屬導線2 la的側壁,從而達到提昇蝕刻選擇性的功 效。然而’這些鈍化氣體所形成的高分子並不同於以往由 光阻層被蚀刻物所形成者,往往因此改變了反應槽的條 件’不僅有可能影響產品元件的性質,也增加了製程的複 雜度,導致生產效率的降低。是以,為了往後更細微尺寸 之精體電路的製程需要,實有必要謀求其他解決之道。 有鑑於此’本發明之一個目的,在於提供一種積體電 路金屬導線的改良製程,其可增強光阻層的抗蝕刻能力, 提昇金屬層與光阻層間的蝕刻選擇性,以符合尺寸縮小化 元件的製程需求。 本發明另一個目的,在於提供一種積體電路金屬導線 的改良製程’其可利用原位(in_situ)處理方式來提昇金0: \? 1 * 〇 £ 3 * 3111 卩 1168 \? 816111 \ 0503-3692-6. 卩 VII (1 page 5 5. Description of the invention (3) Metal wire case, the thickness of the photoresist layer 22 is also matched Reduce a lot, as shown in FIG. 2A. Next, referring to FIG. 2B, using the pattern of the photoresist layer 22 as a mask, an etching process is performed on the aluminum-copper alloy layer 21, for example, using chlorine A reactive ion etching (RIE) process of the gas in order to form the required metal wires. However, the reduced thickness of the photoresist layer 22 does not provide sufficient resistance to etching. Therefore, when the etching process proceeds to the next stage, all the photoresist layers 22 has been depleted, so that the remaining aluminum-copper alloy layer 21a cannot form the required metal wire structure. In order to improve the above problem, an improved etching method has been proposed 'as shown in circle 2C, which is in an etching gas The so-called "passivation gas" is added, such as HC1, HBr, or CHF3, etc., to reduce the loss of the photoresist layer 22, and a polymer film can be formed to protect the sidewall of the metal wire 2la, thereby achieving improvement Efficacy of etch selectivity. However 'The polymers formed by these passivation gases are different from those formed by the photoresist layer etched in the past, which often changes the conditions of the reaction tank'. Not only may it affect the properties of the product components, but it also increases the complexity of the process. This leads to a decrease in production efficiency. Therefore, in order to further process the finer size of the fine body circuit, it is necessary to seek other solutions. In view of this, one object of the present invention is to provide a metal circuit for a integrated circuit The improved process can enhance the anti-etching ability of the photoresist layer, and enhance the etching selectivity between the metal layer and the photoresist layer, so as to meet the process requirements of the downsizing device. Another object of the present invention is to provide a integrated circuit metal Improved process of wires' which can use in_situ processing method to improve gold

C:\Program Files\Patent\0503-3692-e.ptd第 6 頁C: \ Program Files \ Patent \ 0503-3692-e.ptd page 6

:層與光阻層間的蝕刻選擇性,#以簡化製程並 響反應槽的條件,從而確保產品it件的性質。 " 嫂制述之目的’本發明提出-種積體電路金屬導 -氮氣電进虎ϊί皮序之前增加對光阻層施行 理程序’以增強光阻層的抗鞋刻能力藉此 與光阻層間的蚀刻選㈣,即使當光阻層厚 ^兀件尺寸縮小“減小肖,仍可充分提供㈣軍 功能’而不會影響金屬導線的蝕刻效果。 根據本發明的一個實施例’一種可提昇金屬層與光阻 層間蚀刻選#性的積艘電路金屬冑㈣造方法,適用於尺 寸縮小化元件之製程,該方法包括下列步驟:(a)形成一 金屬層於一半導體基底上;(b)塗佈一光阻層覆蓋在金屬 層的表面上,並以微影成像程序定義出覆蓋導線部分的圖 案,其中光阻層的厚度小於金屬層者;(c)對光阻層的圖 案施行一氮氣電漿處理程序,用以增強其抗蝕刻能力;以 及(d)利用經氮氣電漿處理的光阻層圖案當作罩幕,而對 該金屬層施行一不含鈍化氣體(passvation gas)之乾蝕刻 程序’用以形成金屬導線圖案。 根據本發明另一個實施例,一種可提昇金屬層與光阻 層間蚀刻選擇性的積體電路金屬導線製造方法,適用於尺 寸縮小化元件之製程,該方法包括下列步驟··( a)形成包 含一播散阻障層(diffusion barrier layer)、一金屬 層、和一抗反射層(anti-reflection layer)之疊層於一 半導體基底上;(b)塗佈一光阻層覆蓋在抗反射層的表面: Etch selectivity between the layer and the photoresist layer, # to simplify the process and affect the conditions of the reaction tank, thereby ensuring the properties of the product it. " The purpose of the description is "The present invention proposes-a kind of integrated circuit metal guide-nitrogen electricity into the tiger's skin sequence to increase the implementation of a photoresist layer before the sequence" to enhance the anti-shoe engraving ability of the photoresist Etching selection between the resist layers, even when the photoresist layer is thicker and the size of the element is reduced, "reducing the shaw can still provide sufficient military functions" without affecting the etching effect of the metal wire. According to an embodiment of the present invention, a A method of metal fabrication of a foundry circuit capable of improving the etching selectivity between a metal layer and a photoresist layer is suitable for the process of reducing the size of a component. The method includes the following steps: (a) forming a metal layer on a semiconductor substrate; (B) Applying a photoresist layer to cover the surface of the metal layer, and defining a pattern covering the wire portion by a lithography imaging program, wherein the thickness of the photoresist layer is smaller than that of the metal layer; (c) A nitrogen plasma treatment process is applied to the pattern to enhance its resistance to etching; and (d) a photoresist layer pattern treated with a nitrogen plasma is used as a mask, and a passivation-free gas is applied to the metal layer. gas) The dry etching process is used to form a metal wire pattern. According to another embodiment of the present invention, a method for manufacturing a metal circuit of a integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer is suitable for a process of reducing the size of a component, The method includes the following steps: (a) forming a stack including a diffusion barrier layer, a metal layer, and an anti-reflection layer on a semiconductor substrate; (b) ) Coating a photoresist layer on the surface of the anti-reflection layer

C:\PrograraFiles\Patent\0503-3692-e.ptd第 7 頁 五、發明說明(5) 1 亡’並以微影成像程序定義出覆蓋導線部分的圖案,其中 光阻層的厚度小於上述疊層者;(c)對光阻層的圖案施行 一氮氣電漿處理程序,用以增強其抗蝕刻能力;以及(d) 利用經氮氣電漿處理的光阻層圖案當作罩幕,而對抗反射 層、金屬層、和擴散阻障層之疊層施行一不含鈍化氣體之 乾姓刻程序,用以形成金屬導線囷案。 其中’上述氮氣電漿處理程序,係在氮氣流量約100 seem、壓力约12 mTorr、系統功率(source p〇wer)約 450W、偏壓功率(bias powerL@15〇w條件下進行電漿處理 約10秒鐘《此外,上述氮氣電漿處理程序與不含鈍化氣體 之乾姓刻程序係於同一反應槽中進行者。 為了讓本發明之上述和其他目的、特徵、及優點能更 明顯易僅’下文特舉若干較佳實施例,並配合所附圖式’ 作詳細說明如下: 圖式之簡單說明 第1A和1B圖之剖面圖,係顯示傳統較大尺寸元件之金 屬導線製程; 第2A和2B圖之剖面囷’係顯示當光阻層厚度隨元件尺 寸縮小化而減小時,已無法提供足夠的抗蝕刻能力; 第2C圖之剖面圖’係顯示一習知的金屬導線改良製 程’其藉由在蝕刻氣體中添加鈍化氣體,以提昇金屬層間 與光阻層蝕刻選擇性;以及 第3A和3B圖之剖面囷,係續·示依據本發明製造方法一 實施例的製造流程;以及C: \ PrograraFiles \ Patent \ 0503-3692-e.ptd Page 7 V. Description of the invention (5) 1 'and define the pattern covering the part of the wire with the lithography imaging program, where the thickness of the photoresist layer is less than the above-mentioned stack (C) implement a nitrogen plasma treatment process on the pattern of the photoresist layer to enhance its resistance to etching; and (d) use the pattern of the photoresist layer treated with nitrogen plasma as a mask to counteract The stack of the reflective layer, the metal layer, and the diffusion barrier layer performs a dry-engraving process without passivation gas to form a metal wire scheme. Among them, the above-mentioned nitrogen plasma treatment process is performed under the conditions of nitrogen flow of about 100 seem, pressure of about 12 mTorr, system power (source power) of about 450W, and bias power (bias powerL @ 15〇w). 10 seconds "In addition, the above-mentioned nitrogen plasma treatment process and the dry name engraving process without passivation gas are performed in the same reaction tank. In order to make the above and other objects, features, and advantages of the present invention more obvious, 'Hereinafter, several preferred embodiments are given, and the drawings are described in detail.' The detailed description is as follows: Brief description of the drawings The cross-sectional views of Figures 1A and 1B show the traditional metal wire manufacturing process of larger components; Section 2A The cross section of Figure 2B 'shows that when the thickness of the photoresist layer decreases as the size of the device decreases, it cannot provide sufficient resistance to etching; the cross section of Figure 2C' shows a conventional metal wire improvement process' By adding a passivation gas to the etching gas, the etching selectivity between the metal layer and the photoresist layer is improved; and the cross-sections in FIGS. 3A and 3B are continued and shown in accordance with an implementation of the manufacturing method of the present invention. Manufacturing process; and

C:\ProgramFiles\Patent\0503-3692-e. ptd第 8 頁 五、發明說明(6) 第4A和4B圖之剖面圈,係繪示依據本發明製造方法另 一實施例的製造流程。 實施例一 以下請參照第3A和3B圖,詳細說明本發明改良方法的 第一個實施例。首先,如第3A圖所示者,提供一半導體基 底30,例如是一矽晶圓,其上方可以形成必須的半導體元 件’而此處為了簡化起見,僅以一平整的基底3〇表示之。 接著’利用一物理氣相沈積(PVD)技術,例如是電子束蒸 鍍程序或是濺鍍程序,形成一鋁銅合金層31復蓋於基底30 上。然後,以旋轉塗佈方法形成一光阻層32覆蓋在鋁銅合 金層31表面上,並以一微影成像程序定義出覆蓋導線部分 的圊案。 接下來,將基底30移入一反應槽中,進行製作金屬導 線構造的製程。不同於習知技術者,此處先對上述光阻層 32的圖案施行一氮氣電漿處理程序,例如是在氮氣流量約 100 seem、麼力約12 mTorr、系統功率約45 0W、偏磨功率 約150W條件下進行電漿處理約10秒鐘,藉此可増強光阻層 32的抗蝕刻能力。應注意者,此一步驟並不需變更現有設 備即可達成,事實上現有製程中當金屬導線圖案製作完成 後,即係利用一氮氣電漿處理程序來中和基底上的帶電電 荷,藉此取下(de_chuck)被吸附的破晶圓,因此本發明只 是充分利用此一步驟達成額外的效果’並不會增加製程的 複雜度。C: \ ProgramFiles \ Patent \ 0503-3692-e. Ptd page 8 V. Description of the invention (6) The cross-section circles in Figures 4A and 4B show the manufacturing process according to another embodiment of the manufacturing method of the present invention. Embodiment 1 Hereinafter, a first embodiment of the improved method of the present invention will be described in detail with reference to Figs. 3A and 3B. First, as shown in FIG. 3A, a semiconductor substrate 30 is provided, for example, a silicon wafer, on which a necessary semiconductor element can be formed. 'For simplicity, here is represented by a flat substrate 30 only. . Next, a physical vapor deposition (PVD) technique, such as an electron beam evaporation process or a sputtering process, is used to form an aluminum-copper alloy layer 31 and cover the substrate 30. Then, a photoresist layer 32 is formed on the surface of the aluminum-copper alloy layer 31 by a spin coating method, and a lithography process is used to define a scheme for covering the lead portion. Next, the substrate 30 is moved into a reaction tank, and a manufacturing process of a metal wire structure is performed. Different from those skilled in the art, here a nitrogen plasma treatment program is first performed on the pattern of the photoresist layer 32, for example, at a nitrogen flow rate of about 100 seem, a power of about 12 mTorr, a system power of about 45 0W, and a bias power Plasma treatment is performed at about 150 W for about 10 seconds, thereby enhancing the etching resistance of the photoresist layer 32. It should be noted that this step can be achieved without changing existing equipment. In fact, when the metal wire pattern is completed in the existing process, a nitrogen plasma processing program is used to neutralize the charged charge on the substrate, thereby The sucked broken wafer is removed (de_chuck), so the present invention just makes full use of this step to achieve additional effects' and does not increase the complexity of the process.

C:\Program Files\Patent\0503-3692-e.ptd第 9 頁 五、發明說明(7) 請參見第3B圖’在同一反應槽中,利用上述經氮氣電 漿處理過的光阻層32圈索杳妆* κ , ^ »1累當作罩幕(mask),對鋁銅合金層 31施行一#刻程序,你丨如j甚蚀田及& ,Λτη、 Α 例如是使用含氣氣體的活性離子蝕刻 (RIE)程序’以形成所需的金屬導線3U。其中,雖然光阻 層32在㈣過程中有所損耗’但由於其抗蚀刻能力經氣氣 電漿處理而增強許多,因此所剩餘光阻層32a的厚度仍大 於習知技術者,可充分提供蝕刻罩幕之功能。 如此’藉由氮氣電聚處理程序,在不添加HC1、HBr、 或CHF3等鈍化氣體的情況下,也能提昇鋁銅金屬層31與光 阻層32間的蝕刻選擇性,從而定義出細微尺寸的金屬導線 31a。此外’由於不使用上述鈍化氣體,在蝕刻過程中將 不會形成其他種類的高分子薄膜’因而可防止反應槽的條 件被改變而影響產品元件的性質。再者,由於上述氮氣電 漿處理程序與含氣氣體的活性離子蝕刻程序係於同一反應 槽中依序施行的,因此並不會增加製程複雜度。 實施例二 隨著元件尺寸縮小化的發展,微影成像程序的施行條 件也曰益嚴苛’特別是在具有高反射性質的金屬層上方定 義導線圖案時,利用抗反射層(anti-reflection layer) 來消除光學反射造成的干擾,進而提昇微影成像精確度之 改良製程已逐漸普遍。以下配合第4A和4B圖所作的說明’ 即係將上述改良方法應用於含有抗反射層之導線構造的另 一實施例。首先,在一半導體基底30上,依序形成一擴散C: \ Program Files \ Patent \ 0503-3692-e.ptd Page 9 V. Description of the invention (7) Please refer to Figure 3B 'In the same reaction tank, use the above-mentioned photoresist layer treated with nitrogen plasma 32杳 索 杳 妆 * κ, ^ »1 is used as a mask, and a #carving procedure is performed on the aluminum-copper alloy layer 31. For example, if you use etch field and & Λτη, Α A reactive ion etching (RIE) process of gas' to form the required metal wire 3U. Among them, although the photoresist layer 32 is lost during the process, but because its anti-etching ability is greatly enhanced by the gas-gas plasma treatment, the thickness of the remaining photoresist layer 32a is still greater than that of a skilled person, which can fully provide The function of etching mask. In this way, by using a nitrogen electropolymerization processing program, the etching selectivity between the aluminum-copper metal layer 31 and the photoresist layer 32 can be improved without adding a passivation gas such as HC1, HBr, or CHF3, thereby defining a fine size. Of metal wires 31a. In addition, 'the above-mentioned passivation gas is not used, and other types of polymer films will not be formed during the etching process', thereby preventing the conditions of the reaction tank from being changed to affect the properties of the product components. Furthermore, since the nitrogen plasma treatment process and the reactive ion etching process containing a gas are sequentially executed in the same reaction tank, the process complexity is not increased. Embodiment 2 With the development of the reduction in the size of components, the implementation conditions of the lithography imaging program are also becoming more severe. Especially when defining a wire pattern over a metal layer with high reflection properties, an anti-reflection layer is used. ) Improved processes to eliminate interference caused by optical reflections and thus improve the accuracy of lithography imaging have become common. The following description with reference to Figs. 4A and 4B 'is another embodiment in which the above-mentioned improved method is applied to the structure of a wire including an anti-reflection layer. First, a diffusion is sequentially formed on a semiconductor substrate 30

C:\ProgramFiles\Patent\0503-3692-e.ptd第 10 頁 五、發明說明(8) 阻陣層(diffusion barrier layer)37、一金屬層 31、和 一抗反射層38 ’例如分別是一氮化鈦(TiN)層37、一鋁銅 合金層31、和另一氮化鈦層38,以形成如第4A圖所示之疊 層構造。 接著’以旋轉塗佈方法形成一光阻層32覆蓋在抗反射 層上3 8表面上’並以一微影成像程序定義出覆蓋導線部分 的圖案。接下來,將基底30移入一反應槽中,進行製作金 屬導線構造的製程。同樣地,此處先對上述光阻層32的圖 案施行一氮氣電漿處理程序,例如是在氮氣流量約1〇〇 seem、壓力約12 mTorr、系統功率約450W、偏壓功率約 150W條件下進行電漿處理約秒鐘,藉此可增強光阻層32 的抗蝕刻能力。 請參見第4B圖’在同一反應槽中,利用上述經氮氣電 襞處理過的光阻層32圖案當作罩幕,對抗反射層38、金屬 層31、和擴散阻障層37之疊層施行一蝕刻程序,例如是使 用含氣氣艘的活性離子蚀刻(RIE)程序,以形成所需的金 屬導線構造(38a、31a、和37a)。其中,雖然光阻層μ在 姓刻過程中有所損耗,但由於其抗蝕刻能力經氮氣電浆處 理而增強許多,因此可充分提供蝕刻罩幕之功能而定義出 細微尺寸的金屬導線。 再一次地,藉由氮氣電漿處理程序提昇鋁銅金屬層31 與光阻層32間的蝕刻選擇性,適用於製造細微尺寸的金屬 導線31a。此外,由於不使用上述鈍化氣體,在蚀刻過程 中將不會形成其他種類的高分子薄膜,因而可防止反應槽C: \ ProgramFiles \ Patent \ 0503-3692-e.ptd page 10 V. Description of the invention (8) Diffusion barrier layer 37, a metal layer 31, and an anti-reflection layer 38 ' A titanium nitride (TiN) layer 37, an aluminum-copper alloy layer 31, and another titanium nitride layer 38 are formed to form a laminated structure as shown in FIG. 4A. Next, a photoresist layer 32 is formed on the antireflection layer over the surface of the antireflection layer by spin coating, and a pattern for covering the lead portion is defined by a lithography process. Next, the substrate 30 is moved into a reaction tank, and a manufacturing process of a metal wire structure is performed. Similarly, a nitrogen plasma treatment program is first performed on the pattern of the photoresist layer 32, for example, under the conditions of a nitrogen flow of about 100 seem, a pressure of about 12 mTorr, a system power of about 450 W, and a bias power of about 150 W. The plasma treatment is performed for about a second, whereby the etching resistance of the photoresist layer 32 can be enhanced. Please refer to FIG. 4B. In the same reaction tank, the above-mentioned pattern of the photoresist layer 32 treated with nitrogen gas is used as a mask, and the anti-reflection layer 38, the metal layer 31, and the diffusion barrier layer 37 are laminated. An etching process is, for example, a reactive ion etching (RIE) process using a gas-containing vessel to form a desired metal wire structure (38a, 31a, and 37a). Among them, although the photoresist layer μ is lost during the engraving process, but its anti-etching ability is greatly enhanced by the nitrogen plasma treatment, so it can fully provide the function of the etching mask and define a fine-sized metal wire. Once again, the etching selectivity between the aluminum-copper metal layer 31 and the photoresist layer 32 is improved by a nitrogen plasma treatment process, which is suitable for manufacturing fine-sized metal wires 31a. In addition, since the above-mentioned passivation gas is not used, other kinds of polymer films will not be formed during the etching process, so the reaction tank can be prevented

C:\ProgramFiles\Patent\0503-3692-e.ptd 第 11 頁C: \ ProgramFiles \ Patent \ 0503-3692-e.ptd page 11

五、發明說明(9) 的條件被改變而影響產品元件的性質。再者,μa a 淋 , 上迷氣氣電 衆處理程序與含氣氣體的活性離子蝕刻程序係於同一反應 槽中依序施行的,因此並不會增加製程複雜度。 ·' 本發明雖已藉較佳實施例的說明揭露如上,然其並非 用以限定本發明,任何熟習此技藝者,在不脫離本發明之 精神和範圍内,當可作些許之更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。5. Description of the invention (9) The conditions are changed to affect the properties of product components. In addition, the μa a shower, the upper gas and gas processing procedures and the gas-containing active ion etching procedures are sequentially performed in the same reaction tank, so the process complexity is not increased. · 'Although the present invention has been disclosed as above by the description of the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

C:\Program Files\Patent\0503-3692-e.ptd第 12 頁C: \ Program Files \ Patent \ 0503-3692-e.ptd page 12

Claims (1)

六、申請專利範園 1. 一種可提昇金屬層與光阻層間蚀刻選擇性(etching selectivity)的積體電路金屬導線製造方法,適用於尺寸 縮小化元件之製程,該方法包括下列步驟: (a) 形成一金屬層於一半導體基底上; (b) 塗佈一光阻層覆蓋在該金屬層的表面上,並以微 影成像程序定義出復蓋導線部分的圖案,其中該光阻層的 厚度小於該金屬層者; (c) 對該光阻層的圖案施行一氮氣電漿處理程序,用 以增強其抗蝕刻能力;以及 (d) 利用經氮氣電漿處理的該光阻層圖案當作罩幕, 而對該金屬層施行一不含鈍化氣艘(passvation gas)之乾 蚀刻程序’用以形成金屬導線囷案。 2·如申請專利範圍第1項所述一種可提昇金屬層與光 阻層間蝕刻選擇性的積體電路金屬導線製造方法,其中步 称(a)該金屬層係一銘銅合金層(AlCu layer)。 3. 如申請專利範圍第1項所述一種可提昇金屬層與光 阻層間蝕刻選擇性的積體電路金屬導線製造方法,其中步 驟(c)該氮氣電漿處理程序,係在氮氣流量約1〇〇 seem、 壓力約12 mTorr、系統功率(source power)約450W、偏磨 功率(bias power)約150W條件下進行電漿處理約10秒鐘。 4. 如申請專利範圍第1項所述一種可提昇金屬層與光 阻層間蝕刻選擇性的積體電路金屬導線製造方法,其中步 驟(d)該不含鈍化氣體之乾蝕刻程序係一使用含氣氣體的 活性離子姓刻程序。6. Application for Patent Fan Yuan 1. A method for manufacturing integrated circuit metal wires capable of improving the etching selectivity between the metal layer and the photoresist layer, which is suitable for the process of reducing the size of the component. The method includes the following steps: (a ) Forming a metal layer on a semiconductor substrate; (b) coating a photoresist layer on the surface of the metal layer, and defining a pattern covering the wire portion by a lithography imaging program, wherein the photoresist layer Those with a thickness smaller than that of the metal layer; (c) performing a nitrogen plasma treatment process on the pattern of the photoresist layer to enhance its resistance to etching; and (d) using the pattern of the photoresist layer treated with nitrogen plasma to As a mask, a dry etching process is performed on the metal layer without a passvation gas to form a metal wire scheme. 2. A method for manufacturing a metal circuit of an integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer as described in item 1 of the scope of the patent application, wherein the step is (a) the metal layer is an AlCu layer ). 3. The method for manufacturing integrated circuit metal wires capable of improving the etching selectivity between the metal layer and the photoresist layer as described in item 1 of the scope of the patent application, wherein the step (c) of the nitrogen plasma treatment process is performed at a nitrogen flow rate of about 1 〇〇seem, the pressure of about 12 mTorr, the system power (source power) of about 450W, bias power (bias power) of about 150W plasma treatment for about 10 seconds. 4. A method for manufacturing a metal circuit of an integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer as described in item 1 of the scope of patent application, wherein step (d) the dry etching process without passivation gas is a Engraving procedure for the active ion surname of the gas. C:\ProgramFiles\Patent\0503-3692-e.ptd第 13 頁 六 申請專利範面 5. 如申請專利範圍第1項所述一種可提昇金屬層與光 阻層間姓刻選擇性的積體電路金屬導線製造方法,其中步 驟(d)該鈍化氣體係HC1、HBr、或CHf3。 、 ’ 6. 如申請專利範圍第1項所述一種可提昇金屬層與光 阻層間蚀刻選擇性的積體電路金屬導線製造方法,其中步 驟(c)和步驟(d)係於同一反應槽中進行者。 7. —種可提昇金屬層與光阻層間蝕刻選擇性的積艘電 路金屬導線製造方法,適用於尺寸縮小化元件之製程該 方法包括下列步驟: (a) 形成包含一擴散阻障層(diffusion barrier Uyer)、一金屬層、和一抗反射層(anti-reflection layer)之疊層於一半導體基底上; (b) 塗佈一光阻層覆蓋在該抗反射層的表面上,並以 微影成像程序定義出覆蓋導線部分的圖案,其中該光阻層 的厚度小於該疊層者; ' (c)對該光阻層的圖案施行一氮氣電漿處理程序,用 以增強其抗蝕刻能力;以及 (d)利用經氮氣電漿處理的該光阻層圖案當作罩幕, 而對該抗反射層、該金屬層、和該擴散阻障層施行一不含 鈍化氣體之乾蝕刻程序,用以形成金屬導線囷案。 8. 如申請專利範圍第7項所述一種可提昇金屬層與光 阻層間蝕刻選擇性的積想電路金屬導線製造方法,其中步 称(a)該擴散阻障層係一氮化鈦(TiN)層。 9. 如申請專利範圍第7項所述一種可提昇金屬層與光C: \ ProgramFiles \ Patent \ 0503-3692-e.ptd page 13 6. Patent application scope 5. As described in item 1 of the scope of patent application, a integrated circuit can improve the selectivity between the metal layer and the photoresist layer A method for manufacturing a metal wire, wherein step (d) the passivation gas system HC1, HBr, or CHf3. , '6. As described in item 1 of the scope of the patent application, a method for manufacturing a metal circuit of an integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer, wherein step (c) and step (d) are in the same reaction tank Proceeder. 7. —A method for manufacturing a metal wire for a foundry circuit which can improve the etching selectivity between a metal layer and a photoresist layer, and is suitable for the process of reducing the size of the component. The method includes the following steps: (a) forming a diffusion barrier layer (diffusion) A barrier Uyer, a metal layer, and an anti-reflection layer are stacked on a semiconductor substrate; (b) a photoresist layer is coated on the surface of the anti-reflection layer, and The shadow imaging program defines a pattern covering the wire portion, wherein the thickness of the photoresist layer is smaller than that of the laminate; '(c) A nitrogen plasma treatment process is performed on the pattern of the photoresist layer to enhance its resistance to etching ; And (d) using the photoresist layer pattern treated with nitrogen plasma as a mask, and performing a dry etching process without passivation gas on the anti-reflection layer, the metal layer, and the diffusion barrier layer, Used to form metal wire cases. 8. As described in item 7 of the scope of the patent application, a method for manufacturing a metal circuit for an integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer, wherein the step (a) the diffusion barrier layer is a titanium nitride (TiN )Floor. 9. A metal layer and light can be improved as described in item 7 of the scope of patent application 六、申請專利範圍 阻層間蚀刻選擇性的積體電路金屬導線製造方法,其中步 驟(a)該金屬層係一鋁銅合金層(A1Cu iayer)。 10. 如申請專利範圍第7項所述一種可提昇金屬層與光 阻層間蚀刻選擇性的積體電路金屬導線製造方法,其中步 驟(a)該抗反射層係一氮化鈦(TiN)層。 11. 如申請專利範圍第7項所述一種可提昇金屬層與光 阻層間蚀刻選擇性的積體電路金屬導線製造方法,其中步 驟(c)該氮氣電漿處理程序,係在氮氣流量約1〇〇 sccm、 壓力約12 mTorr '系統功率約450W、偏壓功率約150W條件 下進行電漿處理約1 〇秒鐘。 12. 如申請專利範圍第7項所述一種可提昇金屬層與光 阻層間蝕刻選擇性的積體電路金屬導線製造方法,其中步 称(d)該不含鈍化氣逋之乾蝕刻程序係一使用含氯氣體的 活性離子蚀刻程序。 13. 如申請專利範圍第7項所述一種可提昇金屬層舆光 阻層間蝕刻選擇性的積體電路金屬導線製造方法,其中步 驟(d)該鈍化氣體係HC1、HBr、或CHF3。 14. 如申請專利範圍第7項所述一種可提昇金屬層與光 阻層間蝕刻選擇性的積體電路金屬導線製造方法,其中步 驟(c)和步驟(d)係於同一反應槽中進行者。6. Scope of patent application Method for manufacturing integrated circuit metal wires with selective etching between resist layers, wherein step (a) the metal layer is an aluminum-copper alloy layer (A1Cu iayer). 10. The manufacturing method of integrated circuit metal wire capable of improving the etching selectivity between the metal layer and the photoresistive layer as described in item 7 of the scope of patent application, wherein in step (a), the anti-reflection layer is a titanium nitride (TiN) layer . 11. As described in item 7 of the scope of the patent application, a method for manufacturing integrated circuit metal wires capable of improving the etching selectivity between a metal layer and a photoresist layer, wherein the step (c) of the nitrogen plasma treatment process is performed at a nitrogen flow rate of about 1 The plasma treatment was performed at a pressure of about 12 mTorr ', a system power of about 450 W, and a bias power of about 150 W for about 10 seconds. 12. As described in item 7 of the scope of patent application, a method for manufacturing a metal circuit of integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer, wherein step (d) the dry etching process without passivation gas is a Reactive ion etching procedure using chlorine gas. 13. A method for manufacturing a metal circuit of an integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer as described in item 7 of the scope of the patent application, wherein step (d) the passivation gas system HC1, HBr, or CHF3. 14. A method for manufacturing a metal circuit of an integrated circuit capable of improving the etching selectivity between a metal layer and a photoresist layer as described in item 7 of the scope of patent application, wherein steps (c) and (d) are performed in the same reaction tank . C:\Program Files\Patent\0503-3692-e.ptd第 15 頁C: \ Program Files \ Patent \ 0503-3692-e.ptd page 15
TW87114178A 1998-08-27 1998-08-27 Method for increasing etch selectivity of metal wire TW388938B (en)

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