JPS61145652A - Program debug device - Google Patents

Abstract

PURPOSE:To intermit the execution of a program at plural stop addresses by writing in advance an interruption signal to a desired address corresponding to a stop address location of the program among an address of a RAM. CONSTITUTION:In order to set a stop address of a program by a CPU1, an address signal 17 is outputted to set ROM selection signal 18a, b and a data signal 16, and an interruption signal is written to an address corresponding to any stop address of address brake RAMs 11, 12. Further, the signal 17 is used to set a gate selection signal 18c and the signal 16 and a gate signal 19c. Then the state is in the stop address signal detection wait state. A debug program is executed by the CPU1 and when the signal 17 is coincident with the stop address, an interruption signal is read from the RAM11 or 12. Then the signal is latched by a circuit 14a, and becomes an interruption signal 19a for the CPU1. The CPU1 sets a selection signal 18d to recognize the interruption signal and reports the occurrence of an event.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a program debugging device for checking whether a program to be executed by a processor runs as designed.

[Background of the invention]

Conventionally, in this type of device, a latch circuit stores a program stop address, and a comparison circuit compares whether or not the execution address of the program by the processor matches the stop address stored in the latch circuit. For example, it is configured to input an interrupt signal to the processor, interrupt the execution of the processor, and notify the operator of the results of data processing up to the stop address.

However, if the stop address is stored in a latch circuit in advance in this way, a latch circuit with the same number of bits as the address signal is required, and if the execution of the program is to be stopped at multiple stop addresses, had the disadvantage that the structure of the latch circuit became more complicated.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a program debugging device that can suspend program execution at a plurality of stop addresses with a simple configuration.

[Summary of the invention]

The present invention provides a random access memory that corresponds one-to-one with the address of the program memory and is accessed by the same signal as the address signal of the program memory, and a program stop address position among the addresses of the random access memory is provided. An interrupt signal is written in advance at a corresponding nine desired address, and when the execution address of the processor indicates this stop address position, the interrupt signal is successively output and supplied to the interrupt input of the processor.

[Embodiments of the invention]

FIG. 1 is a schematic diagram showing an embodiment of the present invention.
(b) Arithmetic processing instructed by the program, (b) Address break detection processing that receives an interrupt signal when a stop address is detected and reports the detection of a stop address, (c) Command that receives debugging commands via communication means. A CPU 1 that executes each process such as reception processing, a memory 2 that serves as a storage section for arithmetic processing data, a program that executes each process of (A) to Pi above, and a debug program that is executed in a simulated manner using a debug device. ROMs 3 and 4 that store
A communication unit 5 receives debug commands from the console CRT 9, stores an interrupt signal at an address corresponding to the program stop address, and outputs the interrupt signal when the address signal 17 of the CPUI indicates the storage address of the interrupt signal. address break RAM II and 12, a decoder unit 1G that receives the address signal 17 and selects one of the memory blocks in the system, and receives the output signal of the address break RAM II and 12 and outputs it as an interrupt signal 111 to the CPUI. It consists of a status circuit 14 and a gate circuit 13 that turns on and off the transmission of the interrupt signal 19a. In addition, the CPU
I and each circuit block are connected by an address signal 17 and a data signal 16. On the other hand, the communication unit 5 is connected to a connector 8 via a driver 6 and a receiver 7, and further connected to a connector 9b of a CRT 9 via a communication line 2o. Further, the ROM selection signal 18 of the decoding section 10
m and 1s bi'! , ROM3, and address break AMII, are connected to the selection signal of 12 so as to overlap with the address of ROM3 and number. Address break RAMII
.

12 output terminal Do is a pull-down resistor r l 5 F
Connected to +r15G, the signal output from here is OR
It is input to the data input of latch 14a via gate 14b. When the gate signal 19C, which is the output of the wrap 13a, is ON, the latch 14a receives the output signal 19d of the address break ordinary person Mll, 12, and the buffer 14D
The interrupt signal 150 is turned ON via the . Interrupt signal 1
A pull-up resistor 15H is connected to the pin 9a. Gate signal 4) To turn on x9c, turn on the gate signal 18C, select the solanchi circuit 13a, and then turn on the data signal 16.
This is done by turning on. Interrupt signal 19
a is read into the CPUI via the data signal 16 by turning on the status selection signal 180 and opening the buffer 14E.The interrupt signal 192 is reset by turning on the reset selection signal 18E. It is done.

Figure 2 shows a signal transition diagram. In the above configuration, C
PUI is for setting the program stop address.
An address signal 17 corresponding to this stop address is output, and an OM selection signal 18a is output.

18b is turned ON (LOW). At the same time, the data signal 16 is turned on, and the address break RAM II
An interrupt signal is written to an address corresponding to one of the 12 stop addresses. Next, the CPU 1 uses the address signal 17 to turn on the gate selection signal 18c, and at the same time turns on the data signal 1.
6 is turned on to turn on the gate signal 19c. This results in a state of waiting for detection of a stop address signal. Therefore, the debug program is executed by CPUIK,
When the address signal 17 coincides with the stop address, an interrupt signal is read from the address amplifier λMllt or 12. This interrupt signal is latched by the latch circuit 14a and becomes an interrupt signal 19a for the CPU1. By turning on the status selection signal 18Dt, the CPU 1 detects that it is an interrupt signal from the latch circuit 14a and reports the occurrence of an event.

FIG. 3 shows a flowchart of a program for executing debug processing. Commands for love bag processing are inputted via the communication unit 5 by keystrokes in the CBr 4. As shown in FIG. The execution results are also sent to the CRT 9' via the communication unit 5.
displayed on the display section.

When the input of command data from the Ml unit 5 is completed, the type of command is next determined. First, it is determined whether the command is a program execution command, and if it is an execution command, a permission code [come] is output to the CT via the communication unit 5, and the program is executed in order from the address specified by CBr4. Next, it is determined whether it is a cancellation command for the stop address detection operation, and if it is a cancellation command, the interrupt signal stored in the address break 8 Mll, 12 is cleared and the status circuit 14 is reset. Next, it is determined whether it is a stop address setting command or not, and if it is a setting command, the address break is set to ``1°'' in the corresponding address of 12 (in other words, an interrupt signal is stored), and then the gate circuit 1
Set 3 to ON state. Next, it is determined whether or not it is a read command for the memory contents, and if it is a read command, processing data is retrieved from the memory 2 and output to the CR'r9 via the communication unit 5. Next, it is determined whether or not it is a write command for the memory contents, and if it is a write command, memory 2
Write the data input from CBr4 to. Once any of the above processes are completed, change the permission “Ki” symbol to CB.
Output to r4.

On the other hand, when the interrupt signal 19a is input, the interrupt processing (
10Q processing) is executed, and the CB
The occurrence of the event is reported to r4.

FIG. 4 shows commands used in the depacking device of this embodiment, and FIG. 5 shows an example of displaying input/output results to the KCRT 9. The following commands are prepared: program execution command G1 stop address (address break) setting command v1 atto V splake release command U1 memory 2 data read command 几 and memory 2 data write command W. For example, with command V, address
- address 5400400. And the command −
Execute the program from address 5000 on G. Then, the display (3) shows 540040 when the program is executed.
It is displayed that the address 0 has been reached.Next, the data at the memory address 20100 at that time is read at the display section (4), and the result is displayed at the position (5) that there are two people.

Furthermore, at display position (6), "01" is placed in memory address 100.
It is displayed that the data is written, detected at display position (7), and the program continues from the 9th address. Also(
At step 8), it is detected that an address has been generated again, and at step (9), it is displayed that the detection of the stop address has been canceled.

〔Effect of the invention〕

As explained above, according to the present invention, a stop address can be detected with an extremely simple configuration, and there is an excellent effect that debugging of a program is facilitated.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing one embodiment of the present invention, and FIG.
3 is a flow diagram of a debugging program, FIG. 4 is a diagram showing types of commands, and FIG. 4 is a diagram showing an example of command input/output. 1...CPU, 3.4...ROM, 11.12...
・Address break RAM, 13...gate circuit, 1
4...Sheath mouth

Claims (1)

[Claims] 1. Generates an interrupt signal when the execution address of a processor that executes a predetermined process according to a program stored in a program memory reaches a preset stop address position; In a program debugging device that interrupts processing, a random access memory is provided which has a one-to-one correspondence with the address of the program memory and is accessed by the same signal as the address signal of the program memory, An interrupt signal is written in advance to a desired address corresponding to the stop address position of the processor, and when the execution address of the processor indicates the stop address position, the interrupt signal is generated to interrupt the processing of the processor. Program debugging equipment. 2. Program debugging that generates an interrupt signal to interrupt the processing of the processor when the execution address of a processor that executes predetermined processing according to a program stored in the program memory reaches a preset stop address position. In the apparatus, a random access memory is provided which corresponds one-to-one with the address of the program memory and is accessed by the same signal as the address signal of the program memory, and corresponds to the stop address position of the program among the addresses of the random access memory. The interrupt signal is written in advance at a desired address of the processor, and when the execution address of the processor indicates the stop address position, the interrupt signal is generated to interrupt the processing of the processor, and the generated interrupt signal is A program debugging device comprising a gate circuit for selectively inputting data to a processor.