JPS6235947A - Controller - Google Patents

Abstract

PURPOSE:To make easily a chip small-dized and to facilitate debugging of a microprogram by using a terminal of the chip whose frequency in use is low for memory address output. CONSTITUTION:A sequencer 1 refers to the contents of a micro instruction register 4 to find whether n numbers of terminals led out of the chip from an operation system 5 are used or not. The sequencer 1 is provided with a decoder to decode contents of the micro instruction register 4, and a circuit, which outputs logical '1' to an information line 7 if the logical value is '0', that is, information is not outputted to the terminal 14, is provided. Thus, an AND circuit 8 is operated and an AND circuit 9 is made unoperated to output a control memory address 2 to the output terminal 14 of the chip through the AND circuit 8, an OR circuit 10, and an output buffer 12. The signal on the information line 7 is outputted simultaneously to an output terminal 13 of the chip through an output buffer 11 to indicate that the signal outputted from the terminal 14 is the control memory address 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a device for facilitating debugging of a microprogram in an integrated microprogram control device having a built-in control memory.

(Summary of the Invention) The present invention provides an integrated microprogram controlled device with a built-in control memory, in which a selector is provided in front of an input/output terminal that is rarely used in normal times, and when the input/output terminal is not used, the control memory This control device outputs the access address of the microprogram, making it easy to debug the microprogram without increasing the size of the chip or increasing the cost due to an increase in the number of terminals.

(Prior Art and Problems to be Solved by the Invention) Conventionally, debugging of a microprogram in a microprogram controlled device has been carried out by tracing read addresses and read data of a control memory using a device such as a logic analyzer.

Advances in integration technology have made it possible to integrate control devices into a single chip, but initially the control memory was attached outside the chip. In this case, there is no problem because the execution state of the microprogram can be traced, but as the integration becomes higher and higher, the control memory is converted to RAM (sometimes it cannot be used as ROM because it cannot be completely debugged) and built into the chip. It has become impossible to easily output trace information outside the chip for program debugging.

In this case, 331. Most debugging is possible by creating a hardware simulator that implements the same logic using MS Rubel and debugging it using this, but the problem arises that a new hardware simulator must be created.

Additionally, if a terminal is provided outside the chip to output trace information, the chip area, case size, etc. will increase, leading to an increase in cost, and since these terminals are not normally used, there will be a lot of waste. there were.

(Means for Solving the Problems) In order to solve these problems, the present invention uses input/output terminals that are infrequently used in normal times, and when these terminals are not used, traces necessary for debugging microprograms are provided. This is designed to output information outside the chip, and will be explained in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a sequencer that controls the execution of a microprogram, 2 is a control memory address (access address) that is the output of the sequencer 1, and 3 is where microinstructions are stored. controlled memory,
4 is a microinstruction register that stores microinstructions read from the control memory 3; 5 is a microinstruction register 4;
6 is an information line that is rarely used and outputs the execution status of the arithmetic system 5 to the outside. 7 is an information line that has no information on the information line 6 and outputs the control memory address 2 outside the chip. Instructing information lines, 8 and 9 are AND circuits,
10 is an OR circuit, 11.12 is an output buffer for outputting a signal to the outside of the chip, and 13.14 is an output terminal of the chip. Note that the AND circuits 8, 9 . OR circuit 10
constitutes a so-called selector. Further, the signal indicated by 0n means that there are n lines and circuits. That is, if the number of control memory addresses 2 is n, the number of information lines 6 is n, and the AND circuits 8, 9 . OR circuit 1
0. Output buffer 12. There are n sets of output terminals 14.

Here, since the operation of the microprogram is well known, it will not be explained in detail, but the operation system 5 is operated according to the contents of the microinstruction register 4.
Alternatively, the sequencer 1 determines the address of the next microinstruction depending on the state of the arithmetic system 5, outputs the control memory address 2, and drives the control memory 3. Here, sequencer 1
By looking at the contents of the microinstruction register 4, it is possible to know whether or not the n terminals 14 output from the arithmetic system 5 to the outside of the chip are being used. That is, by decoding the contents of the microinstruction register 4, it is possible to know that the information is to be output to the terminal 14. To decode this, the sequencer 1 is provided with a decoder, which decodes the contents of the micro-instruction register 4.
A circuit is provided which outputs a logic "1"' to the information line 7 when no information is output to the information line 4.

Note that the configuration of the decoder in the sequencer 1 is not shown because it is clear from the description.

As a result, the AND circuit 8 is activated, the AND circuit 9 is disabled, and the control memory address 2 is set to the AND circuit 8. OR circuit 10. Output terminal 14 of the chip through output buffer 12
Output to. At the same time, the signal on the information line 7 is also output through the output buffer 11 to the output terminal 13 of the chip, indicating that the signal being output from the output terminal 14 is the control memory address 2.

With this configuration, the address of the control memory can be output outside the chip without increasing the number of terminals on the chip.

(Effects of the Invention) As explained above, since the terminals of the infrequently used chip, which are not always used, are used for control memory address output, You can easily debug microprograms from here.

(b) There is no increase in the chip area or the number of case terminals, and there is no increase in the cost of the integrated device for Depagu.

There are advantages such as

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

Claims (1)

[Claims] In an integrated microprogram controlled device with a built-in control memory, a selector is provided in front of an input/output terminal that is rarely used in normal times, and when the input/output terminal is not used, it outputs an access address of the control memory, and A control device characterized in that the input/output terminal is provided with another output terminal for displaying that the access address is output, so that the execution state of the built-in microprogram can be observed from outside the integrated device.