KR200175057Y1 - An apparatus for debugging an error of a computer - Google Patents

Abstract

The present invention relates to a device for error correction of a computer using a Peripheral Component Interconnect (PCI) Bus signal, comprising: a PC system 20 having a PCI slot 21; An address decoding logic unit 30 which receives address / data signals and control signals through the bus of the PCI and decodes them to interpret a write command of a specific input / output port; And a data latch for displaying through the plurality of electroluminescent elements 50 a value written in the input / output port based on a signal decoded by the address decoding logic unit 30 and a data signal through the PCI bus. In particular, the address decoding logic unit 30 includes a plurality of latches 32 and 33 for latching the address signal and the command signal in accordance with the control signal, and the latched address signal and command. And a plurality of decoders 34-36 for interpreting write commands of the specific input / output ports based on the signals, and logic circuits 37 and 38 for logically combining and outputting the output signals of the plurality of decoders. It is widely applicable to any PC system with a PCI bus, such as a PC system without an ISA bus, as well as a notebook PC with a mini PCI socket.

Description

An apparatus for debugging an error of a computer}

The present invention relates to an error correction device of a computer, and more particularly, to an error correction device of a computer using a Peripheral Component Interconnect (PCI) bus signal.

In general, in order to develop a computer program and / or debug an error, an error correction apparatus as shown in FIG. 1 is used.

1 is a block diagram of a conventional computer error correcting apparatus, comprising: an ISA slot 11 provided in a PC system 10; Of the Isa slot 11 ?? An address decoding logic 12 for receiving address signals SA0-9 and control signals IOW #, AEN from the bus and performing address decoding; And receiving the signal 80PortWR # decoded by the address decoding logic unit 12 and the data SD0-7 from the ISA slot 11 and writing to the input / output port (mainly 80Hex Port). It consists of a latch portion 13 for displaying the data value through the electroluminescent elements (LED 0-3 and LED 4-7) (14).

Such a conventional computer error correcting apparatus decodes and uses a specific input / output port (mainly 80 Hex Port) by using Isa interface signals of a PC system. Self test after powering on BIOS (Basic Input / Output System) When one byte of the data is written to the input / output port (80Hex) designated during the Power ON Self Test) process, the data is displayed as a value on the LED, and then the self-testing process is performed after the BIOS is powered on. It is used as a very useful tool during PC development and problem solving process by letting the user know whether or not an error has occurred.

However, as described above, the computer error device according to the prior art is a device using an ISA bus signal, and since the current PC system tends not to support the Isa bus, it does not support the Isa bus. Many PC systems do not have the disadvantage of using the conventional computer error devices.

In addition, in the conventional notebook PC to use the error correction device as shown in Figure 1 to specify a connector for the transfer of the IAS bus signal separately, many notebook PCs are currently produced as described above Because it does not support the bus, there was a disadvantage that the conventional error correction device can not be used.

The present invention has been made to solve the conventional problems as described above, the purpose of the error correction device (Debug Board) using an electroluminescent device (LED), the bus signal of PCI basically provided in the PC system By configuring the error correction device using the above, it can be applied to any PC system having the PCI bus, such as a PC system without an ISA bus or a notebook PC with a mini PCI socket. The aim is to provide an error correction device for the computer.

1 is a block diagram of a conventional computer error correction apparatus,

2 is a block diagram of an error correction apparatus of a computer according to an embodiment of the present invention;

3 is a detailed block diagram illustrating an embodiment of the address decoding logic unit of FIG. 2.

※ Explanation of code for main part of drawing

20: PC SYSTEM 21: Fish Slot (PCI SLOT)

22: PCI bus 30: address decoding logic

31,37,38: OR gate 32,33: Latch

34, 35, 36: decoder 40: data latch

50: electroluminescent element

In order to achieve the above object, an error correction apparatus for a computer according to the present invention includes a peripheral device connection means such as PCI provided in a computer system; Receives an address and control signal (FRAME #, IRDY #, TRDY #, PCICLK, CBE # 0-3 #) among address / data (AD0-10) signals through the bus of the fisheye and decodes the address. Address decoding means for interpreting a write command of a specific input / output port by doing so; And a data latch for displaying, through a plurality of electroluminescent elements, a value written to the input / output port based on the signal 80PortWR # decoded by the address decoding means and the data signal through the fisheye bus. And the address decoding means includes a plurality of latches for latching the address signal and the command signal according to the control signal, and the specific input / output based on the latched address signal and the command signal. And a plurality of decoders for analyzing the write command of the port, and a logic circuit for logically combining and outputting the output signals of the plurality of decoders.

Hereinafter, an error correction apparatus of a computer according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an error correction apparatus of a computer according to an embodiment of the present invention, A PC system 20 having a PCI slot 21 as a peripheral connection device; Adress / Data (AD0-10) signal and control signal FRAME #, IRDY #, TRDY #, PCICLK, CBE # 0-3 # via bus 22 connected to the fisheye slot 21 Address Decoding Logic (30) for receiving address decoding and interpreting a write command of a specific input / output port (here, 80 Hex Port); And a value written in the input / output port based on the signal (80PortWR #) decoded by the address decoding logic unit 30 and the data signal through the fish bus 22. 0-3 and LED 4-7), and a data latch (Data Latch) unit 40 for displaying through the (50).

FIG. 3 is a detailed block diagram illustrating an embodiment of the address decoding logic unit 30 of FIG. 2, and includes a first logical logic output signal of a PCICLK signal and a frame FRAME # signal among the control signals. An OR gate 31; A first latch (32) for latching a CBE0-3 # signal and an address signal AD0-3 through the fisheye bus among the control signals based on an output signal of the first oragate 31; A second latch (33) for latching an address signal (AD4-11) via the fish bus based on an output signal of the first oragate (31); A first decoder (34) for inputting and decoding the latched address signal (LAD0), the latched clock signals (LCBE0, 2, 3 #), and a TDD signal among the control signals (TRDY #); A second decoder (35) for inputting and decoding the latched address signal (LAD1-5) and the latched clock signal (CBE1 #); A third decoder (36) for decoding the latched address signal (LAD6-11); The second decoder 35 A second orifice (37) for ORing the signal decoded by and the signal decoded by the third decoder; And a third orifice 38 for ORing the signal ORed by the second orifice 37 and the signal decoded by the first decoder 34.

Next, the operation of the present invention will be described.

First, when a 1 byte value is written to a specific input / output (I / O) address (here, 80 Hex) in the BIOS of the PC system 20, the PCI bus connected to the PCI slot 21 ( 22), 80Hex I / O Write Cycle occurs. The first I / O write cycle of the PCI bus is FRAME #, AD (0:31) is the address 80 Hex, CBE # 3-0 has the value of Command (0011 for I / O Write), PCICLK It is synchronized by the output. At this moment, the address and command values are latched using the first and second latches 32 and 33. The latched address signal 80hex and a command and a signal of CBE (3: 0) # are input to the first to third decoders 34,35,36. The decoders 34, 35, and 36 have an address value of 080hex and a CBE # (3: 0) value of 0011 and a data ready signal, IRDY # and TRDY #, when the signal is low. The signal goes low. As such, when the I / OPortWR # signal is low, the AD (31: 0) signal of the PCI bus is changed to a data value, which is latched by the data latch 40, and the latched value is The value transmitted to the electroluminescent device 50 and written is displayed on the electroluminescent device 50.

As described in detail above, the error correcting apparatus of the computer according to the present invention can be applied to any PC system having a PCI bus, such as a PC system without an ISA bus, as well as a notebook PC with a mini PCI socket. In particular, since the present invention uses the PCI bus that is basically provided in a computer, there is an effect that can be easily applied to a very wide range of PC systems.

Claims (2)

Peripheral connection means provided in the computer system; Address decoding means for inputting and address decoding an address signal and a control signal through a bus of the peripheral device connecting means to interpret a write command of a specific input / output port; And And data latch means for displaying, via a plurality of electroluminescent elements, a value written to the input / output port based on a signal decoded by the address decoding means and a data signal through the bus. Error correction device of the computer. The method of claim 1, The address decoding means, A plurality of latches for latching the address signal and the command signal according to the control signal; A plurality of decoders for interpreting a write command of the specific input / output port based on the latched address signal and a command signal; And And a logic circuit for logically combining and outputting the output signals of the plurality of decoders.