JPS61144038A - Manufacture of semiconductor wafer - Google Patents
Manufacture of semiconductor waferInfo
- Publication number
- JPS61144038A JPS61144038A JP26795784A JP26795784A JPS61144038A JP S61144038 A JPS61144038 A JP S61144038A JP 26795784 A JP26795784 A JP 26795784A JP 26795784 A JP26795784 A JP 26795784A JP S61144038 A JPS61144038 A JP S61144038A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- semiconductor
- insulating film
- manufacturing
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体ウエーノ・の製造方法、特に素子間分
離を必要とする集積回路装置、殊に大規模集積回路装置
（ＬＥＩ工）用に適した半導体ウエーノ・の製造方法に
関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is suitable for a method of manufacturing a semiconductor wafer, especially an integrated circuit device that requires isolation between elements, and especially for a large-scale integrated circuit device (LEI process). The present invention relates to a method for manufacturing semiconductor wafers.
第２図は従来の通常の一枚の半導体ウエーノ・を用いて
形成したバイポーラデバイスの一例を示す断面図で、（
１）はｐ形基板、（２）は分離酸化喚、（３）はｎ＋形
領領域（４）はｎ−影領域、（５）はフローティングコ
レクタ、（６）はｐ＋形領領域ある。Figure 2 is a cross-sectional view showing an example of a bipolar device formed using a single conventional semiconductor wafer.
1) is a p-type substrate, (2) is an isolated oxidation layer, (3) is an n+ type region, (4) is an n- shadow region, (5) is a floating collector, and (6) is a p+ type region.
このように、従来の一枚のウェーハでバイホーラトラン
ジスタを形成した場合、分離耐圧を得るために、第２図
のような構造が一般的に最も広く用いられている。すな
わち、ｐ形番板（１）を用いた場合、ｎ＋形領領域３）
−ｎ−影領域（４）−フローティングコレクタ（５）
−ｐ＋形領領域６）−フローティングコレクタ（５）
−ｎ−影領域（４） ＝ｎ＋杉領域（３）のラテラル構
造のｎｐｎ トランジスタを形成し、ｐ＋形領領域６）
の長さとｐ形不純物の濃度制御によって、実質的に両ｎ
＋形領域（３）相互間の分離を保っていた。As described above, when a conventional bihole transistor is formed using a single wafer, the structure shown in FIG. 2 is generally most widely used in order to obtain isolation breakdown voltage. That is, when using the p-type number plate (1), the n+ type area 3)
-n-shadow area (4) -floating collector (5)
-p+ shape area 6) - floating collector (5)
-n- shadow area (4) = n+ cedar area (3) lateral structure npn transistor is formed, p+ type area 6)
By controlling the length of n and the concentration of p-type impurity, substantially both n
+-shaped area (3) Separation between each other was maintained.
ところが、従来のこのような構造では、分離酸化嘆（２
）を形成すると、分離酸化１ＩＩＩ（２）とフローティ
ングコレクタ（５）およびｐ＋形領領域６）との界面に
おいて、ストレスに伴う欠陥を生じ、結果的に両ｎ＋形
領域（３）相互間が導通してしまうという不良がよく発
生するという問題点があった。However, in this conventional structure, separation oxidation (2
), defects occur due to stress at the interfaces between the isolated oxide 1III (2), the floating collector (5), and the p+ type region 6), resulting in conduction between both n+ type regions (3). There was a problem in that defects often occurred.
この発明はかかる問題点を解消するためになされたもの
で、素子間分離が簡単かつ確実に行なえる半導体ウェー
ハを得る方法を提供すること金目的としている。The present invention has been made to solve these problems, and its primary purpose is to provide a method for obtaining a semiconductor wafer in which elements can be easily and reliably separated.
この発明に係る半導体ウエーノ・の製造方法では２枚の
半導体基板の対向面に絶縁膜を形成し、この絶縁膜を互
いに接着させることによって１枚の半導体ウェーハを得
る。In the method for manufacturing a semiconductor wafer according to the present invention, insulating films are formed on opposing surfaces of two semiconductor substrates, and the insulating films are adhered to each other to obtain one semiconductor wafer.
上述のようＫして得られた半導体ウエーノ１は表面から
所定深さの位置にウェーハ全域にわたって絶縁層が形成
されるので、任意の部分に表面からこの絶縁層に達する
分離絶縁膜を形成するのみで、この分離絶縁膜に囲まれ
た部分は他の部分と完全に分離することが極めて容易で
ある。In the semiconductor wafer 1 obtained by K as described above, an insulating layer is formed over the entire wafer at a predetermined depth from the surface, so it is only necessary to form an isolation insulating film reaching this insulating layer from the surface at any desired part. It is extremely easy to completely separate the portion surrounded by this isolation insulating film from other portions.
第１図（、）〜（ｄ）はこの発明の一実施例の主要段階
における状態を示す断面図で、まず、ｐ形番板（１）と
ｎ形番板（７）との各対向面にそれぞれ酸化−（８ａ）
および（８１））を形成し、その酸化−（８ａ）の上に
液体カラス（８０Ｇ ニスビン拳オンｅガラス）（９）
を塗布する〔第１図（ａ） ） 、そして、両基板（１
）及び（７）をＳＯＧ（９）を介してはり合わせ、焼き
しめて、ＩＮＩＩの酸化嘆（８）で結合された形にする
〔第１図（ｂ）〕。次に、ｎ形番板（７）側をその表面
から研磨してデバイス形成に必要な厚さのみ残す〔第１
図（Ｃ）〕。このようにして得られた半導体ウエーノ為
にｎ形番板（７）側表面から上記酸化＠ （８） Ｋ達
する分離酸化１１１（２）を形成し、これらの酸化嘆で
分離されたｎ形番板（７）の各領域にｎ＋形領領域３）
で代表されるデバイスを形成する〔第１図（ｄ）〕。こ
の場合各領域相互間は全く酸化−で距てられているので
、分離は完全である。Figures 1(,) to (d) are cross-sectional views showing the main stages of an embodiment of the present invention. respectively oxidized to - (8a)
and (81)) and its oxidation - liquid glass (80G Nisbin fist on e glass) on top of (8a) (9)
[Fig. 1(a)], and both substrates (1
) and (7) are glued together via SOG (9) and baked to form a bonded form with INII oxidation (8) [Figure 1(b)]. Next, the surface of the n-type number plate (7) is polished to leave only the thickness necessary for device formation [first
Figure (C)]. For the semiconductor wafer obtained in this way, isolated oxidation 111 (2) reaching the above oxidation @ (8) K is formed from the surface of the n-type number plate (7), and the n-type number separated by these oxidation layers is formed. n+ shape area 3) in each area of plate (7)
A device typified by is formed [FIG. 1(d)]. In this case, the regions are completely separated by oxidation, so that the isolation is complete.
なお、以上実施例ではパイポーラエ０の素子間分離につ
いてのみ記したが、他のいかなるＺＣについても、素子
間分離にこの発明は適用できる。In the above embodiments, only the isolation between elements of bipolar AE 0 was described, but the present invention can be applied to isolation between elements of any other ZC.
また、基板の導電形は任意に選択可能であることは勿論
である。また、更に多くのウェー／Ｓを重ね合わせ、多
層状に上述の方法を繰返して用いると、三次元的なＬＳ
Ｉ用ウェーハにも応用可能である。Furthermore, it goes without saying that the conductivity type of the substrate can be arbitrarily selected. In addition, if more wafers/S are stacked and the above method is repeated in a multilayered manner, three-dimensional LS
It can also be applied to I wafers.
なお、絶縁膜には酸化整の他にシリコン窒化侠（５１１
３Ｎ４１またはアルミナ（Ａ／２０３）などでもよい。In addition to oxidation, silicon nitride (511) is used for the insulating film.
3N41 or alumina (A/203) may also be used.
以上説明したように、この発明では、拳に絶縁膜を形成
した基板をはり合わせ研磨するのみで、素子間分離の確
実に可能な半導体ウェーハが容易に得られる。As described above, according to the present invention, a semiconductor wafer in which elements can be reliably separated can be easily obtained by simply bonding and polishing substrates each having an insulating film formed thereon.
第１図（５Ｌ）〜（ｄ）はこの発明の一実施例の主要段
階における状態を示す断面図、第２図は従来の一枚の半
導体ウェー７１を用いて形成したノ（イポーラデバイス
の一例を示す断面図である。
図において、（１） 、 （７）は半導体基板、（ｓａ
）、（ａｂ）は絶縁膜、（９）は絶縁性結合物質である
。
なお、各図中同一符号は同一または相当品分を示す。FIGS. 1(5L) to (d) are cross-sectional views showing the main stages of an embodiment of the present invention, and FIG. It is a sectional view showing an example. In the figure, (1) and (7) are semiconductor substrates, (sa
), (ab) are insulating films, and (9) is an insulating binding substance. Note that the same reference numerals in each figure indicate the same or equivalent parts.
Claims (5)
向面に絶縁膜を形成する工程、上記少なくとも一方の半
導体基板上の絶縁膜の表面上に液体状をなし熱処理によ
つて硬化する絶縁性結合物質を塗布し、上記２枚の半導
体基板をはり合わせる工程、このはり合わせた２枚の半
導体基板に熱処理を施して１枚の半導体ウェーハとする
工程、及びこの半導体ウェーハを構成する上記半導体基
板の一方を当該半導体基板内に半導体デバイスを形成す
るに必要な厚さにまで薄くする工程を備えた半導体ウェ
ーハの製造方法。(1) A step of forming an insulating film on each opposing surface of two semiconductor substrates facing each other, and an insulating film formed in a liquid state on the surface of the insulating film on at least one of the semiconductor substrates and hardened by heat treatment. a step of applying a bonding substance and gluing the two semiconductor substrates together; a step of heat-treating the bonded two semiconductor substrates to form one semiconductor wafer; and the semiconductor substrate constituting the semiconductor wafer. A method for manufacturing a semiconductor wafer comprising the step of thinning one of the semiconductor wafers to a thickness necessary to form a semiconductor device within the semiconductor substrate.
ラス：ＳＯＧ）を用いることを特徴とする特許請求の範
囲第１項記載の半導体ウェーハの製造方法。(2) The method for manufacturing a semiconductor wafer according to claim 1, characterized in that liquid glass (spin-on glass: SOG) is used as the insulating bonding material.
る特許請求の範囲第１項または第２項記載の半導体ウェ
ーハの製造方法。(3) A method for manufacturing a semiconductor wafer according to claim 1 or 2, characterized in that a silicon dioxide film is used as the insulating film.
特許請求の範囲第１項または第２項記載の半導体ウェー
ハの製造方法。(4) A method for manufacturing a semiconductor wafer according to claim 1 or 2, characterized in that a silicon nitride film is used as the insulating film.
許請求の範囲第１項または第２項記載の半導体ウェーハ
の製造方法。(5) A method for manufacturing a semiconductor wafer according to claim 1 or 2, characterized in that an alumina film is used as the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26795784A JPS61144038A (en) | 1984-12-17 | 1984-12-17 | Manufacture of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26795784A JPS61144038A (en) | 1984-12-17 | 1984-12-17 | Manufacture of semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61144038A true JPS61144038A (en) | 1986-07-01 |
Family
ID=17451943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26795784A Pending JPS61144038A (en) | 1984-12-17 | 1984-12-17 | Manufacture of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61144038A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225154B1 (en) | 1993-07-27 | 2001-05-01 | Hyundai Electronics America | Bonding of silicon wafers |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48100081A (en) * | 1972-03-29 | 1973-12-18 |
-
1984
- 1984-12-17 JP JP26795784A patent/JPS61144038A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48100081A (en) * | 1972-03-29 | 1973-12-18 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225154B1 (en) | 1993-07-27 | 2001-05-01 | Hyundai Electronics America | Bonding of silicon wafers |
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