JPS61154142A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61154142A JPS61154142A JP27590484A JP27590484A JPS61154142A JP S61154142 A JPS61154142 A JP S61154142A JP 27590484 A JP27590484 A JP 27590484A JP 27590484 A JP27590484 A JP 27590484A JP S61154142 A JPS61154142 A JP S61154142A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- epitaxial layer
- substrate
- type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は半導体装置の製造方法に関し、特に素子間分
離を必要とする半導体装置の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that requires isolation between elements.
[従来の技術]
第2図は、従来方法で何も加工処理が施されていないウ
ェハから製造されたバイポーラトランジスタの構造を示
す断面図である。図において、D−形基板4上にn+形
ラフローティングコレクタ5形成されており、また基板
上でこれらコレクタ間にp+形領領域6形成されている
。n+形フローティングコレクタ5上にn−形エピタキ
シャル層31が形成されており、このエピタキシャル層
上の一部にn+形領領域2形成されている。ざらに、p
4形領域6上に酸化膜である分離絶縁膜1が形成されて
いる。[Prior Art] FIG. 2 is a cross-sectional view showing the structure of a bipolar transistor manufactured from a wafer that has not undergone any processing by a conventional method. In the figure, an n+ type rough floating collector 5 is formed on a D-type substrate 4, and a p+ type region 6 is formed between these collectors on the substrate. An n- type epitaxial layer 31 is formed on the n+-type floating collector 5, and an n+-type region 2 is formed on a part of this epitaxial layer. Zarani, p.
An isolation insulating film 1, which is an oxide film, is formed on the 4-type region 6.
何も加工処理が施されていないウェハからバイポーラト
ランジスタを形成した場合、分離耐圧をとるためには上
図に示すような構造が一般的に最もよく使用されている
。すなわち、D−形基板4を利用した場合、nゝ形領領
域2n−形エピタキシャル層31−n”形フローティン
グコレクタ5−p+形領域5−n+形ラフローティング
コレクタ5n−形エピタキシャル層31−n+形領域2
のラテラル構造のnpn トランジスタを形成し、p÷
形領領域6長さとp+濃度を制御することにより実質的
に01形領域2の相互の分離を保つている。When a bipolar transistor is formed from a wafer that has not undergone any processing, the structure shown in the above figure is generally most often used to ensure a high isolation voltage. That is, when using the D-type substrate 4, the n-type region 2n-type epitaxial layer 31-n'' type floating collector 5-p+ type region 5-n+ type rough floating collector 5n-type epitaxial layer 31-n+ type Area 2
form an npn transistor with a lateral structure of p÷
By controlling the length of the shape region 6 and the p+ concentration, the mutual separation of the 01 shape regions 2 is substantially maintained.
【発明が解決しようとする問題点]
ところで、従来の何も加工処理が施されていないウェハ
からこのようなラテラル構造の半導体装置を製造する場
合、分離絶縁l11を作ると、分離絶縁1111とn+
形ラフローティングコレクタ5p1形領域6との界面で
ストレスに伴う欠陥ができ、結果的にn+形領域2同士
が導通してしまうという問題点があった。[Problems to be Solved by the Invention] By the way, when manufacturing a semiconductor device with such a lateral structure from a conventional wafer that has not undergone any processing, when the isolation insulation l11 is made, the isolation insulation 1111 and n+
There is a problem in that defects occur due to stress at the interface between the rough floating collector 5p1 and the type region 6, resulting in conduction between the n+ type regions 2.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、素子間分離を必要とするバイポー
ラトランジスタなどの半導体装置に対して簡易に有効な
素子間分離を作ることができる半導体装置の製造方法を
提供することを目的とるる
[問題点を解決するための手段]
この発明に係る半導体装置の製造方法は、第1導電形の
第1W板上に、その予め定めた領域を露出させて絶縁膜
を選択的に形成し、次に、露出した第1基板上に第2導
電形エピタキシャル層を形成し、次に、絶縁膜およびエ
ピタキシャル層上に熱硬化性絶縁物質を設け、次に、第
1導電形の第211板を熱硬化性絶縁物質を介して絶縁
膜およびエピタキシャル層上に重ね、次に、これら複合
物を加熱して絶縁膜および熱硬化性絶縁物質からエピタ
キシャル層を分離する分離絶縁膜を形成し、次に、半導
体装置形成可能な程度のエピタキシャル層を残すように
第1基板、分離絶縁膜およびエピタキシャル層の一部を
除去する。This invention was made in order to eliminate the drawbacks of the conventional devices as described above, and it provides a semiconductor that can easily create effective isolation for semiconductor devices such as bipolar transistors that require isolation between elements. [Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a predetermined area on a first W plate of a first conductivity type. selectively forming an insulating film through exposure, then forming a second conductivity type epitaxial layer on the exposed first substrate, and then providing a thermosetting insulating material on the insulating film and the epitaxial layer; Next, a 211th plate of the first conductivity type is layered on the insulating film and the epitaxial layer via the thermosetting insulating material, and then the composite is heated to form the epitaxial layer from the insulating film and the thermosetting insulating material. Then, the first substrate, the isolation insulating film, and a portion of the epitaxial layer are removed so as to leave enough of the epitaxial layer to form a semiconductor device.
[作用]
、この発明においては、選択的に形成された第1基板上
の絶縁膜と、この絶縁膜およびエピタキシャル層と第2
基板間の熱硬化性絶縁物質とから加熱によって分離絶縁
膜を形成し、この躾によって第2基板上でエピタキシャ
ル層を分離する。[Function] In the present invention, an insulating film selectively formed on a first substrate, this insulating film and an epitaxial layer, and a second
A separation insulating film is formed from the thermosetting insulating material between the substrates by heating, and the epitaxial layer is separated on the second substrate by this process.
[実施例] 以下、この発明の実施例を図によって説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
第1図(a)〜(iは、この発明の実施例である半導体
装置の製造方法における各工程段階の状態を示す断面図
である。まず、第1図(a )に示すように、p−形基
板41金上面にSt 02.リンをドープしたSiO2
.81 m N4 、A庭20、のいずれかからなる絶
縁膜11を形成する。次に、第1図(b)に示すように
、半導体素子を形成する領域の絶縁膜を選択的にエツチ
ングして基板表面を露出する、言い換えれば半導体素子
を分離するために絶縁膜111を残して他の絶縁膜をエ
ツチングする。次に、第1図(C)に示すように、n−
形エピタキシャル層32を形成する。このときn−形エ
ピタキシャル層32は絶縁膜1111IlのO−形基板
41の露出している表面にしか形成されず、結果的にn
−形エピタキシャル層32が選択的に形成さ、れる。次
に、第1図(d )に示すように、選択エピタキシャル
層32および絶縁膜111上に液体状の熱硬化性絶縁物
質、たとえば液体ガラス(SOGニスピン、オン、ガラ
ス)を一様に塗布する。またこの熱硬化性絶縁物質てし
てはポリイミドであってもよい。次に、最終的な基板と
なる別のp−形基板42を液体ガラス12を介して絶縁
l1111およびn−形選択エビタキシャル層32上に
重ね、それらの表面同士を貼り合わせる。次に、これら
複合物を熱処理すると、第1図(e)に示すように、液
体ガラス12が硬化して絶縁膜111と液体ガラス12
から2枚のp″″形基板基板412に挾まれた分離絶縁
1110が形成され、この膜によって選択エピタキシャ
ル層32が完全に分離される。次に、D−形基板41側
を研磨して、第1図<f>に示すように選択エピタキシ
ャル層32および分離絶縁膜10を露出させる。次に、
n−形選択エビタキシャル層32上の一部にn+形領領
域20形成すると、素子間が完全に分離された半導体装
置ができあがる。FIGS. 1(a) to 1(i) are cross-sectional views showing the state of each process step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), p - shaped substrate 41 St02.SiO2 doped with phosphorus on top of gold
.. An insulating film 11 made of either 81 mN4 or A 20 is formed. Next, as shown in FIG. 1(b), the insulating film in the area where the semiconductor element is to be formed is selectively etched to expose the substrate surface. In other words, the insulating film 111 is left in order to separate the semiconductor element. Then, the other insulating film is etched. Next, as shown in FIG. 1(C), n-
A shaped epitaxial layer 32 is formed. At this time, the n-type epitaxial layer 32 is formed only on the exposed surface of the O-type substrate 41 of the insulating film 1111Il, and as a result, the n-type epitaxial layer 32 is
A -type epitaxial layer 32 is selectively formed. Next, as shown in FIG. 1(d), a liquid thermosetting insulating material such as liquid glass (SOG Nispin, ON, Glass) is uniformly applied on the selective epitaxial layer 32 and the insulating film 111. . Further, this thermosetting insulating material may be polyimide. Next, another p-type substrate 42, which will become the final substrate, is stacked on the insulating l1111 and n-type selective epitaxial layer 32 via the liquid glass 12, and their surfaces are bonded together. Next, when these composites are heat-treated, the liquid glass 12 hardens and the insulating film 111 and the liquid glass 12
An isolating insulator 1110 sandwiched between two p'''' type substrates 412 is formed, and the selective epitaxial layer 32 is completely isolated by this film. Next, the D-type substrate 41 side is polished to expose the selective epitaxial layer 32 and the isolation insulating film 10 as shown in FIG. 1<f>. next,
When the n+ type region 20 is formed on a portion of the n- type selective epitaxial layer 32, a semiconductor device in which elements are completely isolated is completed.
なお、第1図(f)のみ、説明の都合上第1図(a)〜
(+))までと上下を逆にしである。For convenience of explanation, only FIG. 1(f) is shown in FIG. 1(a) to FIG.
(+)) and upside down.
上記実施例ではバイポーラLSIの素子間分離について
説明したが、分離の必要なLSIであれば、他のいかな
るものにもこの発明は応用できる。Although the above embodiment describes isolation between elements of a bipolar LSI, the present invention can be applied to any other LSI that requires isolation.
また、上記実施例ではp形基板について説明したが、n
形基板であってもよくこの場合についても上記実施例と
同様の効果を賽する。Furthermore, in the above embodiment, a p-type substrate was explained, but an n-type substrate was explained.
A shaped substrate may also be used, and in this case, the same effects as in the above embodiment can be obtained.
また、上記実施例では2枚のウェハを重ね合わせる場合
について説明したが、複数のウェハに対し上記方法を多
層状に繰返し用いれば、3次元構造のLSIに対しても
この発明は応用できる。Further, in the above embodiment, the case where two wafers are stacked is explained, but if the above method is repeatedly applied to a plurality of wafers in a multilayered manner, the present invention can also be applied to LSIs having a three-dimensional structure.
[発明の効果]
以上のようにこの発明によれば、選択的に形成された絶
縁膜によって第1基板上にエピタキシャル層を形成し、
第21板を熱硬化性絶縁物質を介して絶縁膜およびエピ
タキシャル層上に重ね、これら複合物を加熱して絶縁膜
および熱硬化性絶縁物質からエピタキシャル層を分離す
る分離絶縁膜を形成し、半導体装置可能な程度のエピタ
キシャル層を残すように第1基板1分離絶縁躾およびエ
ピタキシャル層の一部を除去するので、素子間分離を必
要とするパイポートランジスタ等の半導体装置に対して
簡易に有効な素子間分離を作ることができる。[Effects of the Invention] As described above, according to the present invention, an epitaxial layer is formed on a first substrate using a selectively formed insulating film,
A 21st plate is placed over the insulating film and the epitaxial layer via the thermosetting insulating material, and the composite is heated to form a separation insulating film that separates the epitaxial layer from the insulating film and the thermosetting insulating material, and the semiconductor Since the first substrate 1 isolation insulation layer and part of the epitaxial layer are removed so as to leave as much epitaxial layer as possible in the device, it is easily and effectively applied to semiconductor devices such as bipolar transistors that require isolation between elements. It is possible to create isolation between elements.
第1図(a)〜(f)は、この発明の実施例である半導
体装置の製造方法における各工程段階の状態を示す断面
図である。
第2図は、従来方法で製造されたバイポーラトランジス
タの構造を示す断面図である。
図において、10は分離絶縁膜、11,111は絶縁膜
、12は液体ガラス(SOG)、20はn+形領領域3
2はn−形選択エビタキシャル層、41.42はp−形
基板である。
なお、各図中同一符号は同一または相当部分を示す。FIGS. 1(a) to 1(f) are cross-sectional views showing the state of each process step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of a bipolar transistor manufactured by a conventional method. In the figure, 10 is an isolation insulating film, 11 and 111 are insulating films, 12 is liquid glass (SOG), and 20 is an n+ type region 3.
2 is an n-type selective epitaxial layer, and 41.42 is a p-type substrate. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (3)
させて絶縁膜を選択的に形成するステップと、 前記露出した前記第1基板上に、第1導電形と逆の第2
導電形エピタキシャル層を形成するステップと、 前記絶縁膜および前記エピタキシャル層上に熱硬化性絶
縁物質を設けるステップと、 第1導電形の第2基板を前記熱硬化性絶縁物質を介して
前記絶縁膜および前記エピタキシャル層上に重ねるステ
ップと、 これら複合物を加熱して前記絶縁膜および前記熱硬化性
絶縁物質から前記エピタキシャル層を分離する分離絶縁
膜を形成するステップと、 半導体装置形成可能な程度の前記エピタキシャル層を残
すように前記第1基板、前記分離絶縁膜および前記エピ
タキシャル層の一部を除去するステップとを備えた半導
体装置の製造方法。(1) preparing a first substrate of a first conductivity type; selectively forming an insulating film on the first substrate by exposing a predetermined region of the first substrate; and the exposing a second conductivity type opposite to the first conductivity type.
forming a conductive type epitaxial layer; providing a thermosetting insulating material on the insulating film and the epitaxial layer; and attaching a second substrate of the first conductive type to the insulating film via the thermosetting insulating material. and overlying the epitaxial layer; heating these composites to form an isolation insulating film that separates the epitaxial layer from the insulating film and the thermosetting insulating material; A method of manufacturing a semiconductor device, comprising: removing a portion of the first substrate, the isolation insulating film, and the epitaxial layer so as to leave the epitaxial layer.
ポリイミドからなる特許請求の範囲第1項記載の半導体
装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the thermosetting insulating material is made of liquid glass or polyimide.
iO_2、Si_3N_4、またはAl_2O_3から
なる特許請求の範囲第1項または第2項記載の半導体装
置の製造方法。(3) The insulating film is SiO_2, phosphorus-doped S
A method for manufacturing a semiconductor device according to claim 1 or 2, which comprises iO_2, Si_3N_4, or Al_2O_3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27590484A JPS61154142A (en) | 1984-12-27 | 1984-12-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27590484A JPS61154142A (en) | 1984-12-27 | 1984-12-27 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61154142A true JPS61154142A (en) | 1986-07-12 |
Family
ID=17562054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27590484A Pending JPS61154142A (en) | 1984-12-27 | 1984-12-27 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61154142A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051378A (en) * | 1988-11-09 | 1991-09-24 | Sony Corporation | Method of thinning a semiconductor wafer |
JPH0496348A (en) * | 1990-08-13 | 1992-03-27 | Sharp Corp | Manufacture of perfect dielectric isolation substrate |
-
1984
- 1984-12-27 JP JP27590484A patent/JPS61154142A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051378A (en) * | 1988-11-09 | 1991-09-24 | Sony Corporation | Method of thinning a semiconductor wafer |
JPH0496348A (en) * | 1990-08-13 | 1992-03-27 | Sharp Corp | Manufacture of perfect dielectric isolation substrate |
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