JPH025544A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable an element to be micronized and highly integrated by a method wherein a wiring layer is made not only to extend from a low resistance region to the surface of a base along an element isolating region but also to be covered with an insulating layer to be isolated from a semiconductor region. CONSTITUTION:A silicon oxide film 2 is formed on a silicon substrate 1 so as to constitute an insulating base, and a semiconductor region 4 elementally isolated by an element isolating region 3 is provided thereon. A buried layer 8 of a low resistance region is formed of an N<+> type impurity diffusion layer, and a polysilicon layer 7 of a wiring layer is provided under the buried layer 8 but above the silicon oxide film 2 or between them. A silicon oxide film 6 is formed on the side of a semiconductor region 4 as an insulating film so as to make the semiconductor region 4 surrounded with the side wall of a groove 5. The buried l layer is connected with a collector wiring electrode 15c through the intermediary of the polysilicon layer 7. By a constitution mentioned above, a region, used for leading out a collector, can be made sufficiently small, so that an element can be micronized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor region on an insulating substrate is separated into elements and a low resistance region is provided in the semiconductor region, and a method for manufacturing the same. The present invention relates to a semiconductor device, such as a bipolar transistor, in which a low resistance region such as a buried layer is formed in a semi-conductor region, and a method for manufacturing the same.

[Summary of the invention]

The invention according to the present application includes a semiconductor region which is separated by an element isolation region on an insulating substrate and in which a low resistance region is provided in the former substrate region. In the semiconductor device, by providing a wiring layer that extends from the low resistance region to the surface of the substrate along the element isolation region and is covered with an insulating film that is separated from the semiconductor region, This is to realize miniaturization of the element. Furthermore, another invention according to the present application is to easily manufacture a miniaturized semiconductor device by using a bonding technique (1115) in manufacturing the semiconductor device.

[Conventional technology]

In semiconductor devices such as bipone transistors,
A low-resistance region such as a buried layer (coder region) may be provided in a portion deeper than the surface of the substrate. In such a low resistance region located deep in the substrate, a necessary lead-out portion is provided between the low resistance region and the substrate surface for electrical connection.

Conventionally, as a collector extraction technique for bipolar I transistors, a buried layer is extended under the field oxide film, and a collector extraction region is separated from the region where the base and emitter are provided by a field 1' oxide film. There is. Also known are collector removal techniques described in Japanese Patent Publication No. 47-25191 and Japanese Patent Publication No. 50-23277. Tokuko Sho 47-251
The technique described in Publication No. 91 is to simultaneously form a polycrystalline region from polycrystalline growth nuclei during epitaxial growth, and make the polycrystalline region and its surroundings a high concentration impurity region.
/ This is to take out the kuku. In addition, special public service in the 1970s
The technology described in Japanese Patent No. 23277 utilizes a trench for forming an element isolation region, and forms a high concentration impurity region h1 by diffusing impurities to the sidewall of the trench, and takes out the ':j tractor. Go to my house. There is also a prior art technique in which an electrode is taken out from an impurity diffusion region along the side of an element isolation region made of magnesia spinel or the like, and is described in, for example, Japanese Patent Laid-Open No. 146250/1983.

[Problem to be solved by the invention]

However, when trying to achieve high integration of elements, it is difficult to achieve sufficient miniaturization using the above-mentioned technology, and the parasitic 8-drop C,...
'F+Yorino [low 111. The speedup was hindered by r*c.

Co1/
In the technique of using the vector extraction area, Hess, Eminter? ■Even if the area is miniaturized by matching technology, a separate collector extraction area is required! Miniaturization is difficult because of the parasitic capacitance CC! l and parasitic resistance 2/6. In addition, in the techniques described in each of the above-mentioned publications, diffusion of impurities, etc. is essential, and when higher integration is attempted, it becomes an obstacle to miniaturization. Therefore, the present invention is directed to the above-mentioned In view of technical issue 8, electrode extraction from the low resistance region 1. The purpose of this invention is to provide a semiconductor device and its manufacturing method that improves miniaturization and achieves miniaturization.

[Failure to solve the problem]

In order to achieve the object mentioned above, the semiconductor device of the present invention has semiconductor regions separated from each other by an element isolation region on an insulating substrate, and a low resistance region in the base region of the semiconductor region. have.

In the semiconductor device bib, a first impurity diffusion region of the first conductivity type and a second impurity diffusion region Wi of the second conductivity type may be provided adjacent to each other. The insulating substrate may be an insulating substrate such as a glass substrate or a ceramic substrate, or may be a silicon substrate or other semiconductor substrate with an insulating film formed on the surface.

The semiconductor device of the present invention is provided with a wiring layer extending from this low resistance region to the substrate surface along the above-mentioned wiring region, and the wiring layer is provided with an insulating layer for separating it from the semiconductor region. 'M' on the membrane! , the recording line 6L to be corrected extends across the element isolation Tfi region, but especially when forming a low resistance region in contact with the diagonal green μ body, its It can also be drawn out from between the low resistance region and the insulating substrate.In the above-mentioned one forming the first and second impurity diffusion regions, the low resistance region is a buried layer of the first conductivity type, and the wiring layer is formed as a buried layer of the first conductivity type. J-2 is formed, in which J-layer is used as the electrode extraction layer of the buried layer.

Next, the method for manufacturing a semiconductor device of the present invention includes the steps of: forming a groove in a region of the semiconductor substrate where an element isolation region is to be formed; and forming an insulating film on at least the sidewalls of the groove; forming a low resistance region in the region of 1, forming a wiring layer formed along at least the sidewalls of the trench and connected to the low resistance fir region;
forming a rectangular edge layer in the groove where the wiring layer is formed;
1-1 The semiconductor substrate is attached to the support from the surface facing the insulating layer, and the semiconductor substrate is polished from the opposite side of the support to expose the wiring layer on the surface of the substrate. It is characterized by

Examples of the material for the insulating film and insulating layer include silicon oxide and other insulating materials. In addition, examples of the wiring layer include a polysilicon layer, a silicide layer, a polycide layer, and the like.

[Effect]

Since the electrode is taken out from the low resistance region in the semiconductor region base using the wiring layer interposed between the insulating film and the element isolation region, electrical connection is possible only with M in the element isolation region. Then, the brace 1 (,
There is no need to take the trouble to provide an area for extraction, such as an area for extracting the data.

Therefore, it is suitable for miniaturization of elements. In addition, the distribution layer is covered with an insulating film Q, and is provided along the insulating layer in the -n1> element P4 area, so there is no problem such as impurity diffusion, and it can be used for devices such as bipolar transistors. It becomes possible to arrange a highly integrated V.

Next, in the method for manufacturing a semiconductor device described above, the support is laminated to the insulating layer side of the semiconductor substrate using wafer lamination (wafer lamination technique). Therefore, by forming the wiring layer in advance so as to be in contact with the low resistance region, for example, by providing the wiring layer so as to extend on the surface, each layer will be attached to the substrate after bonding M'. Internal 35 area 4: Wiring layer 1 that connects, can be done, and can be done.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

1st Embodiment In this embodiment, the removal of CO1/Kuku 1-7 is done by the poly/recon layer installed on the side wall Q of the separation area.
This is an example of a bipolar transistor of N P N i ν, which has a value of 1'). Semiconductor area is polished after bonding.
1. The emick is formed in the semiconductor region of 1.

There are two structures, see Figure 1.1. i
I will explain from A.

In the semiconductor device of this embodiment, a silicon-non-oxide film 2 is provided on a silicon substrate 1 to constitute an insulating base. The silicon oxide film 2 is formed on the entire surface, and when the device is manufactured using the bonding technique, the silicon oxide film 2 is bonded together.

A semiconductor region 4 41 is provided in the silicon oxide film 2 and is isolated by a device isolation region 3 . An element isolation region 7 is formed using a groove 5 formed in the substrate r by anisotropic etching such as RIE method, and has a substantially rectangular cross section, and the silicon oxide is formed at the bottom of the element isolation region 3. membrane 2
The L portion surrounds the semiconductor region 4 while facing the substrate surface 6, 2. Element isolation region 3 (J, formed from a silicon oxide film, but has a structure in which a polysilicon layer is filled in the silicon oxide film), I'L! :stomach. Its critical component S; 6 semiconductor regions 4 (upper and 6 semicircular regions 4), which are separated from the upper region r (with a low resistance region embedded at the bottom)
The buried layer 13, which is formed by 8, is composed of an N'' type impurity diffusion region.

At the bottom of this buried layer 8, there is - the above silicon oxide 1
A polysilicon layer 7, which is a wiring layer, is formed between the first and second layers. Therefore, buried layer 8 is electrically connected sufficiently to polysilicon N7. On the side of the semiconductor region 4, a silicon oxide film 6 is formed with an insulating film and 1. It is formed by Polysilicon N7 drawn out from the bottom of the buried layer 8 is interposed between the silicon oxide film 6 and the element isolation region 3. That is, the polysilicon layer 7 is connected to the buried layer 8 at the bottom of the semiconductor region 4, is drawn out from there to the element isolation region 3 in a plane parallel to the main surface of the substrate, and is further extended in a plane parallel to the main surface of the substrate. It extends along the vertical sidewalls to the substrate surface. In a portion extending along the substantially vertical sidewall, the polysilicon layer 7 is interposed with silicon oxide l116 between it and the semiconductor region 4, and the polysilicon layer 7, except for the buried layer 8, is connected to the semiconductor region 4. It is insulated from the

In the semiconductor region 4, a base region 6, 11, which is a P-type impurity diffusion region 6N, and an emitter region 10, which is an N-type impurity diffusion region, are formed. The base region 9 consists of a graft base region 9g and an intrinsic base region 91. Graft base region 98 is formed in a consistent manner by diffusion of impurities from polysilicon layer 11 formed on the surface of the substrate, and is formed under polysilicon layer 11 facing the surface of the substrate. Intrinsic base? Region 91 is formed by introducing impurities through the opening provided in the interlayer latent film 12, and once formed in the region surrounded by the graft base region 9g, the emitter region 10 also uses the opening. It is formed so as to face the surface of the substrate in an aligned manner. The emitter region 10 is connected to the emitter wiring electrode 15e through the thin polysilicon layer 14, and the graft base region 9g is connected to the heath wiring electrode 15b through the polysilicon layer 11.

The buried layer 8 is connected to the collector wiring electrode 15c via a polysilicon layer 7 formed along the side wall of the element isolation region 3.

In the semiconductor device of this embodiment having such a structure, the collector can be taken out from the buried layer 8 through the sidewall of the element isolation region 3 (through the polysilicon layer 7 formed along the sidewall and covered with the silicon oxide film 6). Therefore, the area for extracting the collector can be made sufficiently small, and the device can be miniaturized.The parasitic capacitance cc and parasitic resistance rlc can also be kept small. The polysilicon N7 is surrounded only by the element isolation region 3 and the silicon oxide film 6 within the base, and the diffusion of impurities in the lead-out portion 1-7 is suppressed.

Note that although the semiconductor device of this embodiment is an NPN type bipolar transistor, it may also be a PNP type. Further, the device is not limited to a bipolar transistor, and other elements may be used.

Second Embodiment This embodiment is a method for manufacturing a semiconductor device, and in particular a method using a bonding technique. Hereinafter, this example will be explained according to its steps with reference to FIGS. 2A to 2C.

First, as shown in FIG.
form. The trench 22 is formed by, for example, RIE to have sidewalls substantially perpendicular to the surface of the silicon substrate 21, and then a silicon oxide film 23 as an insulating film is formed on the sidewalls and bottom of the trench 22. If a silicon oxide film is not formed on the surface of the silicon substrate 21, this is for connection with a low resistance region to be formed next. In order to expose the silicon substrate 21 on the surface thereof, a silicon nitride film is formed in advance on the surface of the silicon substrate 21, and selectively oxidized to form a silicon oxide film 23 only inside the groove 22.
Alternatively, after forming the silicon oxide film 23 on the entire surface, only the trench 22 may be filled with resist, and the silicon oxide film 23 other than the trench 22 may be removed.

Next, as shown in Figure 2, the exposed silicon substrate 2
A low resistance region 24 is formed on the surface of 1.

This low resistance region 24 functions as a buried layer of the collector in the case of a bipolar I transistor.

Next, a polysilicon layer 25 is formed over the surface of the low resistance region 24 and the inside of the silicon oxide film 23. This polysilicon layer 25 functions as a wiring layer. Formation of polysilicon layer 25 can be performed by CVD method. Note that the low resistance region 24 can also be formed by diffusion from the polysilicon layer 25, and the low resistance region 24 does not necessarily have to be formed first.

Next, as shown in FIG. 2C, a silicon oxide layer 26 as an insulating layer is formed over the entire surface including the trench 22 in which the silicon oxide film 23 and the polysilicon layer 25 are formed. This silicon oxide layer 26 functions as an element isolation region inside the iM section 22.

In particular, inside the trench 22, a polysilicon layer 25 as a wiring layer is formed between the silicon oxide layer 26 and the silicon oxide film 23.
The structure is such that the two are sandwiched in between. Moreover, the silicon oxide layer 26 is
The parts formed on the entire surface also function as an adhesive layer with the support. Note that the insulating layer is not limited to the silicon oxide layer 26, and may be a structure consisting of a combination of a silicon nitride layer and a silicon oxide layer, or a structure in which the inner wall of a silicon oxide layer is filled with polysilicon. In addition, the low resistance region 24
- 25 kl of polysilicon layer 7) 5) The silicon oxide layer 26 does not necessarily need to be covered, and may be a separate layer or a structure in which the support itself is positioned during lamination.

Next, another silicon substrate 30 is prepared j7, and a silicon oxide film 31 is formed on the entire surface of the silicon substrate 30.

On the other hand, the side of the silicon substrate 21 on which the silicon oxide layer 2G has been subjected to the two series of micromachining is attached to the silicon oxide film 31 of the silicon substrate 30. Then, as shown in FIG. 2d, the silicon oxide film 31 and the silicon oxide layer 26 are bonded together.

The bonded substrates 21 and 30 are polished from the silicon substrate 21 side. As shown in FIG. 2, the polishing is stopped when the polishing surface reaches the silicon oxide layer 26L.Then, the area that was the silicon substrate 21 is separated into elements using the silicon oxide 1i26 as an element isolation region. This results in a semiconductor region 27.

In addition, the silicon oxide layer 26 and the silicon oxide film 23
The polysilicon layer 25 formed between the low resistance regions 2
4 and extend along the silicon oxide layer 2G to the substrate surface, and are separated into individual elements by polishing. Therefore, the polysilicon layer 25 is isolated and functions as a wiring layer occupying a sufficiently small area. In addition,
The polishing may be stopped at a time when the polysilicon layer 25 is exposed, and in that case, by oxidizing the polysilicon layer 25, the polysilicon layer 25 itself is isolated between elements. Thereafter, necessary parts such as a space region, an emitter region, wiring electrodes, etc. are formed to complete the device.

In the method for manufacturing a semiconductor device of this embodiment, the semiconductor region 27 is formed using a wafer bonding technique, so it has excellent crystallinity and is suitable for three-dimensionalization. Furthermore, in the bonding technique, one of the substrates is turned over, but by forming the polysilicon layer 25, which will become a wiring layer, before that, it is possible to effectively take out the electrodes. Since the wiring layer is formed along the insulating layer functioning as an element isolation region, its area can be reduced, which is advantageous for speeding up, etc.

Note that the semiconductor device and the method for manufacturing a semiconductor device of the present invention include:
The embodiments are not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the embodiments.

〔Effect of the invention〕

Since the semiconductor device of the present invention has a wiring layer extending along the element isolation region from the low resistance region to the substrate surface, a region for taking out the electrode from the low resistance region is provided. This makes it possible to take out the electrodes without any problems, and it is possible to achieve miniaturization and high integration of devices.

In addition, in the method for manufacturing a semiconductor device of the present invention, by combining the bonding technique, the electrodes can be taken out from the low resistance region reliably, making it possible to easily manufacture the above-mentioned semiconductor device. Ru.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts of an example of the semiconductor device of the present invention, and FIG.
FIGS. 1A to 2C are process cross-sectional views for explaining an example of the method for manufacturing a semiconductor device according to the present invention according to its steps. 1.21.30...Silicon diffusion 2.6, 23.31...Silicon oxide film 3...Element isolation region 4.27...Semiconductor region 5.22...Groove portion 7.25 ... Polysilicon layer 8 ... Buried area 24 ... Low resistance region

Claims (3)

[Claims] (1) In a semiconductor device having semiconductor regions separated from each other by an element isolation region on an insulating substrate, and having a low resistance region within the base region of the semiconductor region, from the low resistance region to the surface of the substrate, A semiconductor device comprising a wiring layer extending along an element isolation region and covered with an insulating film for isolation from the semiconductor region. (2) A first impurity diffusion region of the first conductivity type and a second impurity diffusion region of the second conductivity type are formed adjacent to each other in the semiconductor region, and the low resistance region is a buried layer of the first conductivity type. 2. The semiconductor device according to claim 1, wherein the wiring layer is an electrode extraction layer of the buried layer. (3) forming a groove in a region of the semiconductor substrate where an element isolation region is to be formed, and forming an insulating film on at least the sidewalls of the groove; forming a low resistance region in a region of the semiconductor substrate other than the groove; a step of forming a wiring layer formed along at least a side wall of the trench and connected to the low resistance region; a step of forming an insulating layer in the trench in which the wiring layer is formed; A method for manufacturing a semiconductor device, comprising: bonding the semiconductor substrate to a support; and polishing the semiconductor substrate from the opposite side of the support to expose the wiring layer on the surface of the substrate.