JPS61143866A - Data transfer system - Google Patents

Abstract

PURPOSE:To attain the transfer of data between two devices having the different modes of transfer of data by providing two flip-flop trains to a data transfer device. CONSTITUTION:A memory control unit 1 is connected to an input/output controller 4 via a channel processor 2 and a data transfer device 3. The processor 2 contains a data buffer 5 and a signal control part 6. While the device 3 contains flip-flops 9-14, a selection means 15, a flip-flop 16 and a control signal control part 7. The flip-flops 9 and 10 are used for CHP interface; while flip- flops 11 and 12 are used for data waiting purposes. Furthermore the flip-flops 13 and 14 are used for conversion of the bus width with the flip-flop 16 used for IOC interface respectively. The means 15 connects the flip-flop 13 or 14 to the flip-flop 16 by an indication of the part 7.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides two devices that perform data transfer in different manners:
For example, it relates to a data transfer method in which a data transfer device is provided between a channel processing device and an input/output control device, and the data transfer device is used to transfer data between two devices that transfer data in different ways. It is something.

[Prior art and problems] In the conventional technology, for example, the data transfer mode of the channel and the data transfer mode of the input/output control device are the same, but the data transfer mode is not the same when the channel is already installed. Even if an attempt was made to install an input/output control device whose aspect is different from that of the channel, it was impossible to install it with the conventional technology.

[Purpose of the invention]

The present invention is based on the above consideration, and an object of the present invention is to provide a data transfer method that allows data transfer between two devices having different data transfer modes.

[Means to achieve the purpose]

Therefore, the data transfer method of the present invention requires device A, a data transfer device, device B, and two n-byte wide data transfer devices installed between device A and the data transfer device.
an n-byte wide data bus installed between the data transfer device and device B; a control signal bus installed between the device A and the data transfer device; The data transfer system includes a control signal bus installed between the device B and the device B, and the data transfer device includes two flip-flops each consisting of a plurality of n-byte wide flip-flops connected in series. A flip-flop array and one of the two flip-flop arrays are connected to the above device A.
and the data transfer device, and the other of the two flip-flop arrays is installed between the device A and the data transfer device. an n-byte wide device connected to the n-byte wide data bus installed between the data transfer device and device B; A B-side flip-flop, a selection means installed between the two flip-flop arrays and the B-side flip-flop of the device, and a control signal controller, the control signal controller comprising: When transferring data from device A to device B, if the value of the byte count section that counts the number of data transferred to device B is an even number, the data in one flip-flop column is transferred to the flip-flop on device B side. The selecting means is controlled so that the data is output to the flop, and if the value of the byte count section is an odd number, the selecting means is controlled so that the data of the other flip-flop column is output to the flip-flop on the device B side. In addition to controlling
When transmitting a data request signal to the device A and transferring data from the device B to the device A, on the condition that the flip-flops on the device A side of the two flip-flop arrays are both empty. controls the selection means so that if the value of the byte count section that counts the number of data received from the device B is an even number, the data of the flip-flop on the device B side is output to one flip-flop column. If the value of the byte count section is an odd number, the selection means is controlled so that the data of the flip-flop on the device B side is output to the other flip-flop row, and the two flip-flop rows are output. The device A is characterized in that it is configured to send a data sending signal to the device A on the condition that both flip-flops on the device A side are satisfied.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram illustrating the present invention in detail. In FIG. 1, l is a memory control unit, 2 is a channel processing device, 3 is a data transfer device, 4 is an input/output control device, 5 is a data buffer of the channel processing device, 6 is a signal control device of the channel processing device, 7 is a control signal controller of the data transfer device, 8 is a data buffer of the input/output control device, 9 to 14 are 1-byte wide flip-flops, 15 is a selection means, and 16 is a flip that can hold 1-byte wide data.・
Flops, 17 and 18 are 1 byte wide data bus, 1
9 also indicates a 1-byte wide data bus, and 20 indicates a control signal control section of the input/output control device. The channel processing device 2 includes a data buffer 5 and a signal control section 6. The signal control unit 6 transmits control signals to the data transfer device 3 and receives control signals from the data transfer device 3. Between the channel processing device 2 and the data transfer device 3 a data bus 17, 18 and a control signal bus are provided. The data transfer device 3 includes flip-flops 9 to 14, selection means 15, a flip-flop 16, and a control signal controller 7. Flip-flops 9 and 10 are for the CHP interface, flip-flops 11 and 12 are for data waiting, flip-flops 13 and 14 are for bus width conversion, and flip-flop 16 is for the IOC interface. . When sending data from the channel processing device 2 to the input/output control device 4, the data in the flip-flop 9 is transferred to the flip-flop 11 on the condition that the flip-flop 11 is empty;
data is transferred to flip-flop 13 on the condition that flip-flop 13 is empty. The same goes for flip-flops 10, 12 and 14.

When sending data from the input/output control device 4 to the channel processing device 2, the data in the flip-flop 13 is transferred to the flip-flop 11 on the condition that the flip-flop 11 is empty, and the data in the flip-flop 13 is transferred to the flip-flop 11, The data in flop 11 is transferred to flip-flop 13 provided flip-flop 9 is empty. The same goes for flip-flops 10, 12 and 14. The selection means 15 selects the channels from the channel processing device 2 to the input/output control device 4.
When data is to be transferred from the input/output control device 4 to the channel processing device 2, the data from the flip-flop 13 or 14 is sent to the flip-flop 16 according to instructions from the control signal controller 7. The data in the flip-flop 16 is sent to the flip-flop 13 or 14 according to instructions from the signal control section 7. The control signal control unit 7 controls the selection means 15, receives control signals from the channel processing device 2, transmits control signals to the channel processing device 2, receives control signals from the input/output control device 4, and receives input/output signals. It transmits control signals to the output control device 4, etc. A data bus 19 and a control signal bus are provided between the data transfer device 8 and the human output control device 4. The input/output control device 4 has a data buffer 8 and a control signal control section 20. The control signal control unit 20 receives control signals from the data transfer device 8, transmits control signals to the data transfer device 8, and the like.

If the data transfer rate on data bus 17 is 1 byte per unit time, the data transfer rate on data bus 19 is 2 bytes per unit time.

The data transfer rate on data bus 18 is the same as the data transfer rate on data bus 17.

FIG. 2 is a diagram showing a data transfer sequence between the channel processing device and the data transfer processing device and a data transfer sequence between the data transfer processing device and the input/output control device. Second
Figure (a) shows a data transfer sequence between a channel processing device and a data transfer processing device. In the case of reading, when the data transfer device 3 puts the data on the data buses 17 and 18 and turns on the service-in signal (data sending or data request), the channel processing device 2 transfers the data.
The data on the data buses 17 and 18 are taken in for service.
Turn on the out signal. When the service-out signal is turned on, the data transfer device 3 turns off the service-in signal, and when the service-in signal is turned off, the channel processing device 2 turns off the service-out signal. service·
When the OUT signal is turned off, the data transfer device 3 puts the data on the data buses 17 and 18 and turns on the service in signal. Thereafter, similar operations are repeated.

In the case of writing, when the data transfer device 3 turns on the service in signal, the channel processing device 2 puts data on the data buses 17 and 18 and turns on the service out signal. When the service out signal is turned on, the data transfer device 3 takes in the data on the data buses 17 and 18 and turns off the service in signal, and when the service in signal is turned off, the channel processing device 2 takes in the data on the data buses 17 and 18 and turns off the service in signal. Turn off the out signal. When the service out signal is turned off, the data transfer device 3 turns on the service in signal. Thereafter, similar operations are repeated.

FIG. 2 (bl is a diagram showing the data transfer sequence between the data transfer device and the input/output control device. In the case of reading,
The input/output control device 4 puts data on the data bus 19 and turns on the service-in signal. When approximately X time has elapsed, the input/output control device 4 turns off the service-in signal, and after approximately 7 hours, puts the next data on the data bus 19 and turns on the service-in signal. Thereafter, similar operations are repeated. When the service in signal is turned on, the data transfer device 3 takes in the data on the data bus 19 and turns on the service out signal. Thereafter, the same operation is performed every time the service-in signal is turned on. In the case of writing, the input/output control device 4 turns on the service-in signal, turns off the service-in signal after approximately X time, and turns on the service-in signal after approximately 7 hours.

When the service in signal is turned on, the data transfer device 3 puts data on the data bus 19 and turns on the service out signal. Thereafter, the same operation is performed every time the service-in signal is turned on.

After performing a series of data transfers, the input/output control device 4
The number of service-in signals and the number of service-out signals are compared to check whether a series of data transfers has been performed correctly.

FIG. 3 is a diagram illustrating data movement between flip-flops 9 to 14 and 16. FIG. 3(a) explains the case where data is sent from the input/output control device 4 to the channel processing device 2. At clock #1, the data
Data a on bus 19 is set in flip-flop 13. At clock #2, data b on data bus 19 is set in flip-flop 14, and data a in flip-flop 13 is transferred to flip-flop 11. At clock #3, data bus 19
The above data C is sent to flip-flop 13,
Data b of flip-flop 14 is transferred to flip-flop 12, and data a of flip-flop 11 is transferred to flip-flop 9. At clock #4,
Data d on data bus 19 is in flip-flop 1
4, data C in flip-flop 13 is transferred to flip-flop 11, data a in flip-flop 12 is transferred to flip-flop 10, and data in flip-flops 9 and 10 is transferred to data bus 1.
7 and 18.

At clock #5, data d of flip-flop 14
is transferred to flip-flop 12. At clock #6, data d of flip-flop 12 is transferred to flip-flop 10, data C of flip-flop 11 is transferred to flip-flop 9, and data d, c of flip-flops 9 and 10 are transferred to flip-flop 10.・Bus 17 and 1
8.

FIG. 3(b) explains the case where data is sent from the channel processing device 2 to the input/output control device 4.

At clock #1, data a,b on data buses 17 and 18 are transferred to flip-flops 9,10. At clock #2, data a, b on flip-flops 9 and 10 are transferred to flip-flops 11 and 12. At clock #3, flip-flops 11 and 1
2 data a and b are flip-flops 13 and 1
4, data a of flip-flop 13 is output onto data bus 19, and data a is transferred to data buses 17 and 18.
The above data c, d are transferred to flip-flop 9.10. At clock #4, data b on flip-flop 14 is output onto data bus 19 and data C2d on flip-flops 9 and 10 are transferred to flip-flops 11 and 12.

At clock #5, data c, d from flip-flops 11 and 12 are transferred to flip-flops 13 and 14, and data C from flip-flop 13 is output onto data bus 19. At clock #6, data d from flip-flop 14 is output onto data bus 19.

FIG. 4 shows one of the main parts of the control signal controller 7 of the data transfer device.
This shows an example configuration. In FIG. 4, 21 to 26 indicate gates, and 27 indicates a byte count section, respectively. FIG. 4(a) shows a portion that is effective when data is transferred from the channel processing device 2 to the input/output control device 4. Note that in FIG. 4(a), flip-flops 1 to 14 are omitted. Part-Time Job·
When the value of the byte count section 27 is an even number, the gate 21 is opened and the data of the flip-flop 13 is transferred to the flip-flop 16, and when the value of the byte count section 27 is an odd number, the gate 22 is opened and the data of the flip-flop 13 is transferred to the flip-flop 16. 1
4 data is transferred to flip-flop 16. Further, when data is transferred from the channel processing device 2 to the input/output control device 4, the first power of the gate 23 is turned on. Then, when both flip-flops 9 and 10 are empty and are off due to the service out signal, the gate 23 outputs an on service in signal.

FIG. 4 (bl is the part that becomes effective when transferring data from the input/output control device 2 to the channel device 4.
Also in FIG. 4(b), flip-flops 11 to 14 are omitted. When the value of the byte count section 27 is an even number, the gate 24 is opened and the data in the flip-flop 16 is transferred to the flip-flop 13;
When the value of the byte count section 27 is an odd number, the gate 2
5 is opened and the data in flip-flop 16 is transferred to flip-flop 14. In addition, the human output control device 4
When transferring data from to the channel device 2, the first power of the gate 26 is turned on. When flip-flops 9 and 10 both indicate data present and the service out signal indicates off, the gate 26 outputs an on service in signal.

In the embodiment shown in FIG.
Flops 9.11 and 13 and flip-flops 10.12 and 14 connected in series in three stages are provided for the following reasons. data bus 1
When the flip-flop 9.10 on the 7.18 side is empty or not full, the data transfer device 3 transfers the channel processing device 2
does not send a service-in signal to Furthermore, there are also variations in the time taken by the channel processing device 2 to respond upon receiving this service-in signal. Therefore, due to slight variations in the response time of the channel processing device 2, the data transfer device 3
There may be a delay in sending data from the channel processing device 2 to the channel processing device 2 or in receiving data from the channel processing device 2 in the data transfer device 3, and a control signal may arrive from the input/output control device 4 during that time. In such cases, flip
If only flops 9 and 10 exist, the data transfer device 3 cannot respond to the control signal from the input/output control device 4, which causes an overrun. In order to prevent such a situation as much as possible, in the embodiment shown in FIG. This makes it difficult for the input/output control device 4 to see variations in the response.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, data can be transferred between devices with different data transfer modes without being aware of data transfer on the other side.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the present invention in detail, FIG. 2 is a diagram showing a data transfer sequence between a channel processing device and a data transfer processing device, and a data transfer sequence between a data transfer processing device and an input/output control device. FIG. 3 is a diagram illustrating data movement between flip-flops 9 to 14 and 16;
FIG. 4 shows one of the main parts of the control signal controller 7 of the data transfer device.
It is a figure showing the composition of Example ti. DESCRIPTION OF SYMBOLS 1... Memory control unit, 2... Channel processing device, 3... Data transfer device, 4... Input/output control device, 5... Data buffer of channel processing device, 6...
...Signal control section of channel processing device, 7.. Control signal control section of data transfer device, 8.. Data buffer of input/output control device, 10 to 14.. 1-byte wide flip-flop, 15...Selection means, 16...1
Flip-flop that can hold byte-wide data, 1
7 to 19...1-byte wide data bus, 20...
...Control signal control unit of input/output control device, 21 to 26
...gate, 27...byte count section.

Claims (1)

[Claims] A device A, a data transfer device, a device B, two n-byte wide data buses installed between the device A and the data transfer device, and between the data transfer device and device B. An n-byte wide data bus installed, a control signal bus installed between the device A and the data transfer device, and a control signal bus installed between the data transfer device and device B. The data transfer system includes two flip-flop rows, each consisting of a plurality of n-byte wide flip-flops connected in series, and the two flip-flop rows. one of the two n installed between the device A and the data transfer device.
A byte-wide data bus is connected to one side of the byte-wide data bus, and the other of the two flip-flop arrays is connected to two n-byte-wide data busses installed between the device A and the data transfer device.
means for connecting to the other side of the bus, and an n-byte wide device B side flip-flop connected to the n-byte wide data bus installed between the data transfer device and device B;
It has a selection means installed between the two flip-flop arrays and the flip-flop on the device B side, and a control signal control section, and the control signal control section is configured to control the control signal from the device A to the device B. When transferring data, if the value of the byte count section that counts the number of data transferred to device B is an even number, the data in one flip-flop column will be transferred to device B.
The selection means is controlled so that the data is output to the side flip-flop of the device, and if the value of the byte count section is an odd number, the data of the other flip-flop column is output to the device B side flip-flop. In addition to controlling the selection means, a data request signal is sent to the device A on the condition that the flip-flops on the device A side of the two flip-flop arrays are both vacant, and the device B sends a data request signal to the device A. When transferring data to the device B, if the value of the byte count section that counts the number of data received from the device B is an even number, the data in the flip-flop on the device B side is output to one flip-flop column. and controlling the selection means so that if the value of the byte count section is an odd number, the data of the flip-flop on the device B side is output to the other flip-flop row; A data transfer system characterized in that the data transmission signal is transmitted to the device A on the condition that both flip-flops on the device A side of the two flip-flop arrays are full.