JPS61140533U - - Google Patents

Info

Publication number
JPS61140533U
JPS61140533U JP1985023997U JP2399785U JPS61140533U JP S61140533 U JPS61140533 U JP S61140533U JP 1985023997 U JP1985023997 U JP 1985023997U JP 2399785 U JP2399785 U JP 2399785U JP S61140533 U JPS61140533 U JP S61140533U
Authority
JP
Japan
Prior art keywords
substrate
conductor layer
layer formed
conductor
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985023997U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985023997U priority Critical patent/JPS61140533U/ja
Publication of JPS61140533U publication Critical patent/JPS61140533U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す断面図、第２
図は従来例を示す断面図である。 １，１′……内部配線、２……Ａｕバンプ、３
，３′……半導体チツプ、４，４′……半導体チ
ツプの電極、５，５′……セラミツク基板、６…
…低融点ガラス等の接合材、７……外部配線、８
……セラミツク製上ブタ、９′……ボンデイング
ワイヤー。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁性基板の表面から該基板の側面を介して該
    基板の裏面に至るまで導体層が形成され、該基板
    の表面に形成された該導体層の部分に半導体素子
    の電極が直接接続され、該基板の側面および／又
    は裏面に形成された該導体層の部分を外部導出用
    導体としてなることを特徴とする半導体装置。
JP1985023997U 1985-02-21 1985-02-21 Pending JPS61140533U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985023997U JPS61140533U (ja) 1985-02-21 1985-02-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985023997U JPS61140533U (ja) 1985-02-21 1985-02-21

Publications (1)

Publication Number Publication Date
JPS61140533U true JPS61140533U (ja) 1986-08-30

Family

ID=30517742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985023997U Pending JPS61140533U (ja) 1985-02-21 1985-02-21

Country Status (1)

Country Link
JP (1) JPS61140533U (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010564A (ja) * 1973-05-25 1975-02-03
JPS5028769A (ja) * 1973-07-13 1975-03-24

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010564A (ja) * 1973-05-25 1975-02-03
JPS5028769A (ja) * 1973-07-13 1975-03-24

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