JPS6113931U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6113931U
JPS6113931U JP9932284U JP9932284U JPS6113931U JP S6113931 U JPS6113931 U JP S6113931U JP 9932284 U JP9932284 U JP 9932284U JP 9932284 U JP9932284 U JP 9932284U JP S6113931 U JPS6113931 U JP S6113931U
Authority
JP
Japan
Prior art keywords
land
wiring board
semiconductor equipment
land part
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9932284U
Other languages
English (en)
Other versions
JPH023622Y2 (ja
Inventor
幸孝 徳本
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP9932284U priority Critical patent/JPS6113931U/ja
Publication of JPS6113931U publication Critical patent/JPS6113931U/ja
Application granted granted Critical
Publication of JPH023622Y2 publication Critical patent/JPH023622Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の一実施例である半導体装置に用いられ
るリードフレームの平面図、第２図及び第３図は第１図
のＡ−Ａ線及びＢ−Ｂ線に沿う要部拡大断面図、第４図
及び第５図は従来の半導体装置に用いられるリードフレ
ームの平面図及びＣ一Ｃ線に沿う要部拡大断面図、第６
図は他の従来の半導体装置に用いられる”ＩＪ−ドフレ
ームの断面図である。 ７・・・リードフレーム、８・・・ランド部、９−・・
リード、９′・・・リード先端部、１１・・・配線基板
、１５．１５’・・・絶縁性突起、１６，１７，１８・
・・電子部品、１９・・・ワイヤ。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードフレームのランド部下とこのランド部の近傍から
    周辺に延びる複数のリードのランド部側先端部下とに跨
    がって配線基板を固着し、ランド部と配線基板上に半導
    体ペレットを含む電子部品をマウントしてワイヤボンデ
    イングで接続したものであって、前記破線基板上の前記
    ワイヤの下部に相当する箇所に絶縁性突起を形成したこ
    とを特徴とする半導体装置。
JP9932284U 1984-06-29 1984-06-29 半導体装置 Granted JPS6113931U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9932284U JPS6113931U (ja) 1984-06-29 1984-06-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9932284U JPS6113931U (ja) 1984-06-29 1984-06-29 半導体装置

Publications (2)

Publication Number Publication Date
JPS6113931U true JPS6113931U (ja) 1986-01-27
JPH023622Y2 JPH023622Y2 (ja) 1990-01-29

Family

ID=30658829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9932284U Granted JPS6113931U (ja) 1984-06-29 1984-06-29 半導体装置

Country Status (1)

Country Link
JP (1) JPS6113931U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335366A (ja) * 1992-05-29 1993-12-17 Nec Corp 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335366A (ja) * 1992-05-29 1993-12-17 Nec Corp 半導体装置

Also Published As

Publication number Publication date
JPH023622Y2 (ja) 1990-01-29

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