JPS61131473A - エツチングによるリ−ドフレ−ムパタ−ンの形成方法 - Google Patents

エツチングによるリ−ドフレ−ムパタ−ンの形成方法

Info

Publication number
JPS61131473A
JPS61131473A JP25266784A JP25266784A JPS61131473A JP S61131473 A JPS61131473 A JP S61131473A JP 25266784 A JP25266784 A JP 25266784A JP 25266784 A JP25266784 A JP 25266784A JP S61131473 A JPS61131473 A JP S61131473A
Authority
JP
Japan
Prior art keywords
etching
boundary
lead frame
etchant
frame pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25266784A
Other languages
English (en)
Japanese (ja)
Other versions
JPH058580B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Mamoru Onda
護 御田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP25266784A priority Critical patent/JPS61131473A/ja
Publication of JPS61131473A publication Critical patent/JPS61131473A/ja
Publication of JPH058580B2 publication Critical patent/JPH058580B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • ing And Chemical Polishing (AREA)
JP25266784A 1984-11-29 1984-11-29 エツチングによるリ−ドフレ−ムパタ−ンの形成方法 Granted JPS61131473A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25266784A JPS61131473A (ja) 1984-11-29 1984-11-29 エツチングによるリ−ドフレ−ムパタ−ンの形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25266784A JPS61131473A (ja) 1984-11-29 1984-11-29 エツチングによるリ−ドフレ−ムパタ−ンの形成方法

Publications (2)

Publication Number Publication Date
JPS61131473A true JPS61131473A (ja) 1986-06-19
JPH058580B2 JPH058580B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-02-02

Family

ID=17240552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25266784A Granted JPS61131473A (ja) 1984-11-29 1984-11-29 エツチングによるリ−ドフレ−ムパタ−ンの形成方法

Country Status (1)

Country Link
JP (1) JPS61131473A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6217187A (ja) * 1985-07-17 1987-01-26 Hitachi Cable Ltd リ−ドフレ−ムの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6217187A (ja) * 1985-07-17 1987-01-26 Hitachi Cable Ltd リ−ドフレ−ムの製造方法

Also Published As

Publication number Publication date
JPH058580B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-02-02

Similar Documents

Publication Publication Date Title
JPH07180089A (ja) 電気鍍金方法及び構成
US5066366A (en) Method for making foil
CN110113872A (zh) 一种pcb退膜工艺、制造方法及系统
CN113766747A (zh) 一种微细线路的pcb微蚀刻工艺以及电路板
US4155775A (en) Cleaning of high aspect ratio through holes in multilayer printed circuit boards
CN114724958B (zh) 半导体引线框架的制造方法
JPS61131473A (ja) エツチングによるリ−ドフレ−ムパタ−ンの形成方法
CA1231595A (en) Apparatus and process for treating printed circuit boards
JPS58127328A (ja) 半導体基板の絶縁保護膜の蝕刻方法
JPH01172241A (ja) 石英ガラスのエッチング方法
JPS6257106B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS5792829A (en) Forming method for electrode
JPS5610368A (en) Method and device for immersion coating
JPH02277281A (ja) プリント板のエッチング方法及びその装置
JPH01188444A (ja) ウェットエッチング方法
JP2665343B2 (ja) 印刷回路板の洗浄方法
JP4626062B2 (ja) 基板処理装置及び基板処理方法
JPS5633836A (en) Patterning method of gaas thermal oxide film
JP2006249530A (ja) 金属膜パターンの形成方法
JPS5750454A (en) Etching for soldered electrode
JPH0355556B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS6213817Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0529210A (ja) 感光性レジスト層の剥離方法
JPH0783169B2 (ja) プリント基板の製造方法
JPH0210793A (ja) プリント配線板におけるキャビティの形成方法

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees