JPS61127661U - - Google Patents
Info
- Publication number
- JPS61127661U JPS61127661U JP1059885U JP1059885U JPS61127661U JP S61127661 U JPS61127661 U JP S61127661U JP 1059885 U JP1059885 U JP 1059885U JP 1059885 U JP1059885 U JP 1059885U JP S61127661 U JPS61127661 U JP S61127661U
- Authority
- JP
- Japan
- Prior art keywords
- laser diode
- semiconductor laser
- diode chip
- solder
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000007599 discharging Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第1図はこの考案の半導体レーザダイオードの
実装構造の一実施例の平面図、第2図は第1図の
右側面図、第3図は同上半導体レーザダイオード
の実装構造の正面図、第4図は同上半導体レーザ
ダイオードの実装構造の斜視図、第5図は同上半
導体レーザダイオードの実装構造をヒートシンク
上に実装した例を示す平面図、第6図は第5図の
右側面図、第7図は同上半導体レーザダイオード
の実装構造をヒートシンク上に実装した例の正面
図、第8図は従来の半導体レーザダイオードの実
装構造の斜視図である。 1……半導体レーザダイオードチツプ、2……
活性層、3……全線、4……ステム、5……ボン
デイング用溝、6……半田排出用溝、7……半田
、8……リード、9……ヒートシンク。
実装構造の一実施例の平面図、第2図は第1図の
右側面図、第3図は同上半導体レーザダイオード
の実装構造の正面図、第4図は同上半導体レーザ
ダイオードの実装構造の斜視図、第5図は同上半
導体レーザダイオードの実装構造をヒートシンク
上に実装した例を示す平面図、第6図は第5図の
右側面図、第7図は同上半導体レーザダイオード
の実装構造をヒートシンク上に実装した例の正面
図、第8図は従来の半導体レーザダイオードの実
装構造の斜視図である。 1……半導体レーザダイオードチツプ、2……
活性層、3……全線、4……ステム、5……ボン
デイング用溝、6……半田排出用溝、7……半田
、8……リード、9……ヒートシンク。
Claims (1)
- 半導体パツケージの半導体レーザダイオードチ
ツプ搭載領域の所定位置にこの半導体レーザダイ
オードチツプより大きいボンデイング用溝および
半田排出用溝を設け上記ボンデイング用溝に溶融
した半田で上記半導体レーザダイオードチツプを
ボンデイングするとともにこの半導体レーザダイ
オードチツプの活性層と上記半田排出用溝とを位
置合わせすることを特徴とする半導体レーザダイ
オードの実装構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1059885U JPS61127661U (ja) | 1985-01-30 | 1985-01-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1059885U JPS61127661U (ja) | 1985-01-30 | 1985-01-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61127661U true JPS61127661U (ja) | 1986-08-11 |
Family
ID=30491927
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1059885U Pending JPS61127661U (ja) | 1985-01-30 | 1985-01-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61127661U (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63136685A (ja) * | 1986-11-28 | 1988-06-08 | Sony Corp | 半導体レ−ザ装置 |
JP2017069267A (ja) * | 2015-09-28 | 2017-04-06 | 京セラ株式会社 | 光素子搭載用パッケージおよび電子装置 |
JP6928199B1 (ja) * | 2020-10-01 | 2021-09-01 | 三菱電機株式会社 | 半導体レーザ装置 |
-
1985
- 1985-01-30 JP JP1059885U patent/JPS61127661U/ja active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63136685A (ja) * | 1986-11-28 | 1988-06-08 | Sony Corp | 半導体レ−ザ装置 |
JP2017069267A (ja) * | 2015-09-28 | 2017-04-06 | 京セラ株式会社 | 光素子搭載用パッケージおよび電子装置 |
JP6928199B1 (ja) * | 2020-10-01 | 2021-09-01 | 三菱電機株式会社 | 半導体レーザ装置 |
WO2022070388A1 (ja) * | 2020-10-01 | 2022-04-07 | 三菱電機株式会社 | 半導体レーザ装置 |