JPS61118842A - Generating system of pseudo soft error - Google Patents

Abstract

PURPOSE:To attain a soft error check by breaking the part of a read data given from a RAM in the stage of the storage of it to a data register. CONSTITUTION:An inverting circuit 14 is set between a RAM10 and a read register (RDR)12. A counter 20 works at every time the RAM10 receives a read access for the extraction of the output of the highest stage. A production circuit 22 produces the pulse '1' of the prescribed width. This pulse is delivered to an inversion indicating circuit 16. When an inversion mode is indicated by a signal source 18, the inversion is given to a prescribed access frequency to produce a state similar to an error generation mode.

Description

[Detailed description of the invention] [Industrial field of application] The present invention is a pseudo soft error generation method suitable for testing the operation of error detection and correction circuits (ECC) [Prior art] Used in the main memory of computers, etc. Random access memory (RAM) is known to generate soft errors due to alpha ray irradiation. RAM read data is first entered into the read data register (RDR) and then sent to the request source via a bus etc.
An ECC circuit is provided for the DRfl'S, and the read data is checked by the ECC circuit, and if there is a small number of pinpoints determined by the configuration of the circuit, generally a 1-bit error in the whole or in each block, it is corrected. is output. A soft error that occurs in the data stored in RAM remains an error unless it is rewritten with correct data. If a new soft error occurs in the data in this state, it will become a 2-bit error and will be corrected by the ECC circuit. is impossible, so the operation will stop,
The correction result in the ECC circuit is written into the RAM to correct the stored data.

It is necessary to check whether such an ECC circuit is normal. This can be done during system tests or periodic inspections, but since the soft error occurrence rate of RAM storage data is a rare phenomenon, such as once a month, pseudo (artificial) It is necessary to generate a soft error.

[Problem that the invention seeks to solve]

Regarding RAM soft error countermeasures, there are various error correction and retry methods in the ECC field, and each has been put into practical use, but this function should be tested in real time in an environment as similar to the actual situation as possible. This is not easy; there is a method of intentionally destroying the RAM contents with the help of a service processor (SVP) and checking whether the ECC circuit etc. is working, but this method
, it is difficult to create a real-time operating environment.

The present invention aims to artificially generate soft errors in a manner similar to the actual occurrence in real time, and to test ECC circuits and the like.

[Means for solving problems]

The pseudo soft error generation method of the present invention is provided with a circuit capable of inverting a predetermined bea/ ) in the read data of the memory between a random access memory and a register storing read data thereof, and the inverting circuit: When in the soft error occurrence mode, the inversion operation is performed intermittently once for every plural read of the memory.

〔Example〕

To explain this with reference to the drawings, in FIG. 1, 10 is a RAM, and 12 is a register that stores the read data.

In the present invention, an inverting circuit 14 is provided between the RAMI OSI output data register 12. If the RAM read data is 32 bits, the inversion circuit 14 is provided for 1 bit, or for 1 bit of each block in the case of a 4 block configuration of 8 bits each. Since one bit also means one signal line, the inverting circuit 14 is inserted into that one signal line. An inverter may be used to invert the signal bits, but in this case the 0 inversion circuit 14 uses an exclusive OR (EOR) gate because the signal bits are inverted or not inverted.
The number of bits to be provided is determined depending on the configuration of the ECC circuit within a range that allows correction even if the bits are inverted and does not affect operation. R.A.
There is no particular problem as to which bit of the M read data should be inserted, and therefore it may be inserted fixedly into an appropriate bit.

Since bit inversion is performed during testing and inspection, and should not be done all the time, the inversion circuit 14 is provided with a y-column circuit, and a 0 inversion indicating circuit 16 is used. ” is output to instruct inversion, and “0” is output to instruct through. 18 is a reversal instruction circuit 1
A signal source (for soft error generation mode instruction) for 6, for example, outputs "1" when a switch provided on the panel is closed, and outputs "0" when the switch is opened. 20 is 3
Each time the RAM 10 is read accessed, a RAM read access signal RA is input and counted by a bit or 4-bit counter. The output of the top stage of the counter 20 is taken out, and the shaping circuit 22 generates a predetermined pulse width of “11”.
The 0 inversion instruction circuit 16, which is pulsed and input to the inversion instruction circuit 16, is an AND gate in this example, and the signal source 18
outputs "1", that is, inversion mode is commanded, and when the top stage output ° of the counter rises to "1", the shaping circuit 22
Outputs “1” during the period determined by . If the counter 20 has 3 pins, this "1° output therefore the bit inversion is RAM
If the counter 20 has 4 bits, the bit inversion is 1 for every 8 read accesses of RAM 10.
This is one time for every six read accesses.

This normally normal occurrence of bit errors at times is similar to the occurrence of normal RAM soft errors.

Of course, the frequency varies greatly, but this is what is commonly used in life tests and the like. The test start instruction, that is, the switch operation described above, is performed by CE (Customer's
The program to be run at this time is preferably a test program, which is configured to stop if there is any abnormality in the system. Therefore, instruct to start the test,
If the test program ends normally, the ECC circuit is considered to be normal. Furthermore, when the ECC circuit performs a correction operation, it raises the machine check report MCK as shown in FIG. 2, so the operation of the ECC circuit can be confirmed by printing out the log data.

FIG. 2 shows a RAM I O, a read data register 12, an ECC circuit, etc., and 24 is the ECC circuit, which consists of a check circuit and an error correction circuit. A selector 26 is switched to the ECC circuit side when there is an error in the data in the read data register 12, and outputs the corrected data output by the error correction circuit. Further, this corrected data is rewritten to the address of the data in RAM10 through the write data register 28, and if an error occurs by the 0 inversion circuit 14 that corrects the stored data, the RAM
Since there are no errors in the stored data, rewriting is not necessary. Of course, there is no problem even if the data is rewritten, and the control is normal and simpler in this case. An ECC bit is added to the data stored in the RAM 10, and errors are corrected using this bit.

The number of bits in the counter 20 may be increased or decreased as appropriate.

If the number of bits is small and the frequency of bit inversion is high, a bit correction operation will be required each time, slowing down the program execution speed, so it is not desirable to have too few bits.
It is also effective to use a timer counter normally present in the system to invert bits at a certain period, such as every 1 μs or 1 mS, without providing a special counter.

Note that when an error occurs using this method, it is best when the system is in a normal state, and if this is done when accessing RAM during error processing, there is a risk of a double failure and the error processing cannot be continued, so avoid this. This method is suitable for E
It can be used not only for checking CC circuits, but also for checking the operation of parity check circuits, retry control systems, etc.

However, in the former case, if the bits are inverted, an error will occur and a retry will be performed, so the operation will be checked to see if these things worked as planned.

〔Effect of the invention〕

As explained above, in the present invention, the data stored in the RAM itself is not destroyed, but the parity or data bits are partially destroyed at the stage of accessing the RAM and storing the read data in the read data register. In the error generation mode, the error does not occur every time a RAM read access is performed, but occurs intermittently at an appropriate frequency, so it does not particularly interfere with normal operation, and soft errors can be detected in real time in a similar environment. It is extremely effective because it allows you to check the occurrence of the occurrence and whether the functions of each part are normal or abnormal.

[Brief explanation of drawings]

1 and 2 are block diagrams showing embodiments of the present invention. In the drawing, 10 is a random access memory, 12 is a read data register, 14 is an inversion circuit, 18 is a soft error generation mode instruction signal source, and 20 is an intermittent operation counter.

Claims (2)

[Claims] (1) A circuit capable of inverting a predetermined bit in the read data of the memory is provided between the random access memory and the register that stores the read data, and the inverting circuit is
A pseudo soft error generation method characterized in that when in a soft error generation mode, an inversion operation is performed intermittently once for every plural read of the memory. (2) The inverting circuit is within the correctable bit number range of the circuit that detects and corrects errors in the output data of the read data register.
2. The pseudo soft error generation method according to claim 1, wherein the pseudo soft error generation method is inserted into a random access memory read data line.