JPH01133163A - 1-bit inversion error processing system - Google Patents

Abstract

PURPOSE:To prevent the frequent generation of one-bit error software reports by counting up a number when an address at the time of generating an error coincides with the preceding error generating address, and only when the count value reaches a prescribed value, reporting the state. CONSTITUTION:When an one-bit error is generated by reading operation from a master device 10, a memory device 12 logs an error generating address, corrects an one-bit inversion error and outputs the corrected result to the device 10. Then, the device 12 compares the an error generating address An with the preceding error generating address An-1 after logging, and when both the generating addresses coincide with each other, counts up the contents of an error generating counter C by '+1'. When the value of the counter C reaches a previously determined prescribed value N, the device 12 reports error generation to the device 10. When the generated addresses are different from each other, the contents of the counter C are cleared and the error generation is reported to the device 10. Consequently, the frequent generation of reports can be reduced and correction timing can be applied by the writing access from the master device, so that the report can also be omitted.

Description

[Detailed Description of the Invention] Summary] Regarding a 1-bit inversion error processing method that performs a software report to a higher-level device when a 1-bit inversion error occurs when reading data from a memory device, the present invention relates to a 1-bit inversion error processing method that performs a software report to a host device when a 1-bit inversion error occurs when reading data from a memory device. The purpose is to prevent software reporting of inversion errors.When a 1-bit inversion error occurs, the error occurrence address is compared with the previous error occurrence address, and when the occurrence addresses match, the error occurrence counter is counted up. , the error occurrence is reported to the host device only when the value of the error occurrence counter reaches a predetermined value.

[Industrial Application Fields] The present invention provides a software report to a host device when a 1-bit inversion error occurs during data read of a memory device.
Concerning a method for handling bit reversal errors.

In recent years, memory devices installed in general-purpose information processing devices have become highly integrated, and as a result of this high integration, when alpha rays coming from outer space hit the memory device, the data bits at the memory location that received the alpha rays are destroyed. For example, bit "1" is inverted to bit "O".

Therefore, when reading data at an address that has undergone bit inversion due to alpha rays, a 1-bit inversion error will occur as a so-called soft error.

[Prior Art] Conventionally, in a general-purpose information processing device, when a 1-bit inversion error occurs when reading a memory device, a data logging system is used to store the error occurrence address in an appropriate logging table, as shown in the operation flow diagram of FIG. After processing, in order to prevent recurrence of the 1-bit inversion error, a 1-bit error mask is applied for a certain period of time by a timer to close the error bit, and the occurrence of the error is reported by software. In addition, 1 bit inversion error is FC
Since it is modified by the C circuit and sent to the upper level device,
The host device is not affected by the 1-bit inversion error.

[Problem to be solved by the invention] Therefore, even if a 1-bit inversion error occurs during reading due to bit inversion caused by alpha rays, a software report will be made even though it is not a hard error, and an error warning will be displayed to the operator. is served.

In fact, if a bit inversion due to alpha rays occurs in a data part that is frequently used, the error will be reported frequently to the operator, and the operator will judge it to be a hard error and remove the memory device even though it is a soft error. This may result in measures such as replacing the hardware.

Of course, in order to prevent software reporting of a 1-bit inversion error caused by bit inversion caused by alpha rays, the occurrence of errors can be eliminated by performing read/write processing from a host device to the bit inversion data caused by alpha rays.

However, if the memory device is being accessed by another processor following a read operation in which a 1-bit inversion error has occurred, the error cannot be corrected by read/write processing unless the access is completed. Therefore, it is not easy to correct errors through read/write processing.

In addition, in order to enable error correction by read/write processing immediately after an error occurs, it is necessary to newly install a deterrent circuit that prohibits access by other processors, which complicates the circuit configuration and increases costs. There are disadvantages to inviting them.

The present invention has been made in view of these conventional problems, and provides a 1-bit inversion error processing method that prevents frequent soft reporting of 1-bit inversion errors caused by bit inversion caused by alpha rays. The purpose is to provide.

[Means for solving problems] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 10 is a host device, 12 is a memory device, and an information processing device is constituted by an input/output interface I10 that connects these and external devices.

When a 1-bit inversion error occurs in a read operation from the host device 10, the memory device 12 logs the error occurrence address, corrects the 1-bit inversion error, and outputs it to the host device 10.

Furthermore, after logging, the memory device 10 compares the error occurrence address 〇 with the previous error occurrence address An-1, and when the occurrence addresses match, the error occurrence counter C is
is counted up by +1, and when the value of this counter C reaches a predetermined value N, for example, N=10, the host device 1
Reports the error occurrence to 0.

On the other hand, when the generated addresses do not match, the counter C is cleared (to C=1), and the error occurrence is notified to the host device 10.
will be reported to.

[Function] Even if a 1-bit inversion error occurs due to bit inversion caused by alpha rays, if the error occurs at the same address, software reporting to the host device will not be performed until the number of occurrences of 1-bit inversion error reaches a predetermined value. , it is possible to prevent an operator from frequently reporting a 1-bit inversion error and mistaking it as a hardware error and taking measures such as replacing the hardware.

In addition, since it is necessary for a 1-bit inversion error to occur a predetermined number of times before a software report of a 1-bit inversion error is made, it is possible to provide timing to correct the error occurrence address by write access on the host device during this time. As a result, it is possible to eliminate software reporting of 1-bit inversion errors caused by bit inversion caused by alpha rays.

[Example] FIG. 2 is an explanatory diagram showing an embodiment of the present invention.

In FIG. 2, reference numeral 10 denotes a host device, and 12 a memory device. In this embodiment, only the signal system for read operations by the host device 10 is shown.

The memory device 12 is provided with a highly integrated data memory 14, which reads out data corresponding to a read address specified by the host device 10 and sends the read data to the host device 10 via the ECC circuit 16. I'm doing it. Also, when reading the data memory 14, the memory device 12 receives 1
A logging table 18 is provided for logging the error occurrence address when a bit inversion error occurs, and the EC
Upon receiving the 1-bit inverted error detection output from the C circuit 16, the error occurrence address is stored in the logging table 18, and the data stored in this logging table 18 is read by the host device 10 during maintenance and inspection, etc. to detect the occurrence of the error. It allows you to see the situation.

In addition to such a configuration of the memory device 12, one aspect of the present invention
An address comparator 20, a counter 22, and a counter comparator 24 are provided to implement a bit reversal error processing operation.

That is, when a 1-bit inversion error occurs when reading the data memory 14, the address comparison unit 20 compares the current error occurrence address An with the previous error occurrence address An-1 stored in the logging table 18. death,
For example, when an address matches, an H level output is generated, and when an address does not match, an L level output is generated.

The counter 22 counts the number of times C of 1-bit inversion errors occur at the same address.
When a comparison output of an address match that becomes H level is received, the counter comparison section 24 increments the count value C by +1 through comparison processing. Further, when the address comparator 20 generates a comparison output of address mismatch that goes to L level, it is cleared with the inverted output of the inverter 26, and when the counter 22 is cleared, the initial value C=
Return to the set state of 1.

The counter comparison unit 24 compares the count value C of the counter 22 with a predetermined value N, for example, N=10, and when the count value C of the counter 22 is smaller than the predetermined value N, the count value C of the counter 22 is set as C=C+1. On the other hand, when the counter count value C matches the predetermined value N, the host device 10
A software report indicating the occurrence of a 1-bit inversion error is performed.

Note that the L level output from the address comparator 20 due to address mismatch is inverted by the inverter 26, clears the counter 22, and at the same time outputs a software report of the occurrence of an error to the host device 10.

Next, the processing operation for a 1-bit inversion error in the embodiment of FIG. 2 will be explained with reference to the operation flowchart of FIG. 3.

First, in normal data reading in which bit inversion due to alpha rays does not occur, as shown in FIG. It is sent as is to the higher-level device.

On the other hand, if the data memory 14 is hit by alpha rays and a bit inversion occurs in the second bit of specific 8-bit data as shown in FIG. The data in which the first "1" is inverted to bit rOJ is read out, the ECC circuit 16 corrects the 1-bit inversion error, and sends it to the host device 10.
The output of the circuit 16 is a detection signal of a 1-bit inversion error (q).

In this way, when a 1-bit inversion error detection output is obtained by reading the data memory 14, the operation flow shown in FIG. 3 is executed.

First, data logging processing is performed in which the address where the 1-bit inversion error occurred in step S1 is stored in the logging table 18. Subsequently, in step S2,
In order to prevent recurrence of a 1-bit inversion error caused by reading the same address, a mask close is performed in which the error bit is masked for a certain period of time by a timer.

Next, in step S3, the previous error occurrence address An-1 is read from the logging table 18, and in step S
In step 4, it is determined whether the address is the same as the current error occurrence address An.

At this time, assuming that the previous error occurrence address An-1 = XB and the current error occurrence address An = XA (however, the error occurrence address XB is a 1-bit inversion error due to a soft error other than alpha rays), Since the error occurrence addresses do not match, the process proceeds to step S5, where the count value C of the counter 22 is cleared to C=1, and at step S6, a software report of the error occurrence is made to the host device @10. That is, the probability that a one-bit inversion error caused by α rays will occur in a large number of memory elements is extremely small, and if an inversion error occurs at another address, there is a high probability that it is a read error.

On the other hand, in step S4, the previous error occurrence address An-
1 and the current error occurrence address An are both rXAj, that is, if the rereading of the data address whose bits have been inverted by the α ray is performed, step S
7, the count value C of the counter 22 is checked. That is, the count value C of the counter 22 is a predetermined value N, for example, N=1.
Checks if it is less than or equal to 0. At this time, if the counter count value C is smaller than the predetermined value N, the process proceeds to step S8, where the count value of the counter 22 is counted up to C'&C=C+1, and no software reporting is performed, and the process is continued to detect the next 1-bit inversion error. I can do it.

Note that this counter check may be performed after the count-up.

On the other hand, when the counter count value C matches the predetermined value N in step S7, the process proceeds to step S5, where the counter 22 is cleared to C=1, and the occurrence of a 1-bit inversion error is software reported in step S6.

According to the 1-bit inversion error processing method of the present invention, even if a 1-bit inversion error occurs due to bit inversion caused by alpha rays, the same 1-bit inversion error will occur after soft reporting is performed when the first error occurs. Software reporting to the host device is not performed until the occurrence of the error has been repeated a predetermined value N, for example N=10 times, and it is possible to prevent frequent software reporting of 1-bit inversion errors caused by bit inversion caused by alpha rays.

In addition, since software reporting is not performed until a 1-bit inversion error occurs a predetermined number of times, sufficient time is secured for the host device to write access the address where the error occurred, and as a result, the host device Read/write processing is performed for the error address portion on the condition that the address does not access the data memory 14. Therefore,
A 1-bit inversion error is corrected by a write access of a host device before a soft report is performed, and as a result, unnecessary soft reporting of a 1-bit inversion error can be prevented from occurring.

In the embodiment shown in FIG. 2, the address comparison unit 20 reads out the previous error occurrence address An-1 from the logging table and compares it with the current error occurrence address An. A dedicated register may be provided to store the address where the error occurred, and the address comparison between the previous address and the current address where the error occurred may be performed.

Furthermore, as mentioned above, the location where a 1-bit inversion error occurs due to α rays is approximately fixed. Therefore, for example, when read access to the data memory 14 is made to multiple specific areas, an address comparison section is provided for each area, and it is configured to manage whether or not the addresses are the same for each area. It's okay.

[Effects of the Invention] As explained above, according to the present invention, frequent occurrence of error warning display by software reporting can be prevented without adding any hardware circuit function to one bit inversion error caused by bit inversion caused by alpha rays. can be prevented.

In addition, the memory device performs the process of comparing the previous and current error occurrence addresses, counting up the number of occurrences when they match, and issuing a software report when a predetermined value is reached. No changes are required and there is no impact on the processing speed of read operations.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention; Fig. 2 is a detailed explanatory diagram of the invention; Fig. 3 is an operational flow diagram of the embodiment of Fig. 2; Fig. 4 is an explanatory diagram of normal data read; FIG. 5 is an explanatory diagram of data read when a 1-bit inversion error occurs; FIG. 6 is a flowchart of a conventional 1-bit inversion error operation. 10 in the figure: Host device 12: Memory device 14: Data memory 16: ECC circuit 18 Two logging tables 20 Near address comparison section 22: Counter 24: Counter comparison section 1 Figure 4 - Operation flowchart for starting operation Figure 8 Data read for speed control LEI80 Figure 4 1 Error occurred - TI! Data read divination of t, 5th centroid ε, 1 bit counterclockwise error calculation, 1,000 flowchart, Figure 6

Claims (2)

[Claims] (1) Has a host device (10) and a memory device (12),
In an information processing device that logs the error occurrence address when a 1-bit inversion error occurs when reading data from the memory device (12), corrects the 1-bit inversion error, and outputs it to a host device, When an error occurs, the error occurrence address (An) is compared with the previous error occurrence address (An-1), and when the error occurrence addresses match, the error occurrence counter (C) is counted up, and the error occurrence counter (C) is counted up.
) reaches a predetermined value (N), the host device (10
) A 1-bit inversion error processing method characterized by reporting the occurrence of an error. (2) When the error occurrence addresses are compared and they do not match, an error occurrence counter (C) is cleared and the error occurrence is reported to the host device (10). 1-bit reversal error handling method.