JPS59207500A - Data processor - Google Patents

Abstract

PURPOSE:To improve the working factor of a system by storing the contents of an address register and the contents of the input data at a time point when an 1-bit error is generated and delivering a report in case of overflow of those stored contents. CONSTITUTION:If the read data contains a 1-bit error, an ECC circuit 3 corrects the data. At the same time, an FF6 is set by an error detection signal 107 and the output signal 111 of the FF6 is fed to a sensor circuit. In this case, an address register 8 undegorgoes addition and at the same time the output signal 112 of an address register 7 and the output data 104 of a memory circuit 2 are stored in a memory circuit 10. When the writing is completely through with the circuit 10, the overflow signal 114 of the register 8 becomes active and is fed to an FF9. The output signal 115 of the FF9 can be sensed by the firmware. Then the address and the data obtained when an error is generated in the circuit 10 are collected in the form of the output signal 116 and then reported to a maintainer as the logging information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a data processing device, and particularly to a system for transmitting a bladder ejection data error detection signal from a memory circuit thereof.

[Prior art]

In a data processing apparatus having a memory circuit section, the memory circuit section is usually equipped with data error detection/data error correction functions.

For example, in a data processing device that has a data error detection/data error correction circuit capable of detecting data errors of 2 bits or more and correcting 9 data errors of 1 bit, if a data error of 2 bits or more is detected, the system will go down. However, in the case of a 1-bit data error, the data is correctly corrected in the data correction circuit and does not interfere with system operation.

Previously, the presence or absence of a 1-bit error was determined by a "memory scan" (MEMORY8CAN) by maintenance personnel during regular maintenance.
), the presence or absence of an error was reported for the first time. However, if the regular maintenance cycle is long, or if the maintenance person neglects the above-mentioned operations, the system will remain idle with a 1-bit error occurring.

If a failure occurs in another storage element of the same word at this time, a data error of 2 or more bits will be detected, resulting in a serious failure, resulting in a reduction in system operating efficiency.

[Purpose of the invention]

In order to improve such conventional drawbacks, the present invention makes it possible to report such a 1-bit error to a host device when it occurs, to report it to the operator or maintenance person as logging information or sense byte, and to record the collected address register. The present invention aims to provide a data processing device that analyzes the contents of circuits and data, repairs and replaces memory elements as needed, and improves the operating rate of the system.

[Structure of the invention]

According to the present invention, a first memory circuit unit stores a data input signal, and a first memory circuit unit supplies all addresses to the first memory circuit unit.
an error detection and correction code generation circuit for other data having a data error detection function of 2 or more bits and a 1-bit data error detection and correction function; The above-mentioned data error detection and correction circuit generates a data error detection signal and a correctable 1-bit data error detection signal, and a flip-flop is set when the correctable data error detection signal of 1 bit and 1 bit is generated. a second address register circuit to be added, and a second address register circuit to store the contents of the first address register circuit and data read from the first storage circuit section when the erroneous detection signal is generated. There is obtained a data processing device characterized in that it includes a memory circuit section 2, a flip-flop circuit 7 indicating that the second address register circuit has overflowed. 3 [Description of Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Referring to FIG. 1, this embodiment is a write data error detection correction code generation circuit (hereinafter referred to as write data WCC generation circuit).
, a first storage circuit section 2, a readout error calibration circuit (hereinafter referred to as readout data ECC 1 path) 3, a logic output circuit 4, an error register circuit 5, and 7'. The address register circuit 6.9 includes a first address register circuit 7, a second address register circuit 8, and a second memory circuit section S10.

=14: The included data 101 is input to the ncc generation circuit for included data, 'X1, and the first register circuit section 2, and
2 is input to the tenth distribution circuit section 2, and the other output No. 16 103 of the write data FCC generation circuit 1 is input to the 10th distribution circuit section 2.
This is the check output of the generating circuit 1, and is output when an error is accumulated. First memory, output of circuit section 2\371
04 is input to the lfi' read data Ecc circuit 3 and the second storage circuit section IO, and is input to the read data ECC circuit 3.
The first output signal 105 of the circuit 3 is sent to the next stage circuit, and the second output signal 106 of the read data ECC circuit 3 is input to the logic error circuit 4 when the read data has an uncorrectable data error. Furthermore, the read data EC
The third output signal 107 of the C circuit 3 is output to the OR circuit 40 only when the input signal 108 is valid when a correctable data error occurs.
becomes an input signal, and at the same time the second address register circuit 8
And the human power of Norinogu Furosop Circuit 6 is reached.

The output signal 109 of the OR circuit 4 is sent to the error register circuit 5.
The output signal 110 of the error register circuit 5 is 1 (it becomes valid when a major fault occurs and becomes the input signal of the next-stage control circuit).
The output signal 107 of the C circuit 3 becomes unconditionally free when a correctable data error occurs.

The output signal 111 of the flip-flop circuit 6 is not an input signal of the flip-flop circuit 6, and the output signal 111 of the flip-flop circuit 6 is not an input signal of the next-stage sense circuit. The occurrence of - is reported as logging information or sense byte.

The output signal 112 of the first address register circuit 7 is
Note 1. It is supplied as the address of the circuit changing unit 2, and is stored in the second memory circuit unit 10 when a 1/railway error is detected. The blade signal 113 of the second address register circuit 8 is the second address register circuit 8.
is supplied as the address of the memory circuit section 10 of the second
Other outputs of address register circuit 8 B 11.4-
('J,"!'r If the address register circuit 8 of 2 becomes bar 70-, it is output and becomes the input signal of the flip-flop circuit 9. The output signal 115 of the flip-flop circuit 9 is sent to the next stage circuit. Sent. Memory of approximately 2, +
The output signal 116 of the g'l path unit 10 is sensed by the firmware when the output signal 115 of the flip-flop circuit 9 becomes a rumble, and is taken as logging information.
It will be done.

Next, the operation of this embodiment will be explained. The write data and The ECC code is stored in the first storage circuit section 2 at the same time.
The existence of the data is checked in the ECC circuit 3 for appearance data.

For example, normal operation '4Q 4. Here, the first entry (, i
; i, 116 If a write command is generated for part 2 and 7 and j, the f input booter input signal 101 is the first write time:
Input to the FCC generation circuit for the 2 and 1 old data.
A LiNUC code 102 is generated and input into the first storage circuit section 2 at the same time as the weakening data input 18'' 101. .

If erroneous shift) 1 is detected when this ECC code is generated,
An output signal 103 is generated and reported to the outside.

If a V output command is still issued to the first memory circuit unit 2, the output signal 104 of the first memory circuit unit 2 is output, and the ECC code 44-converted to 7 at the same time as the male data is output. They are simultaneously read out, and the read data ECC circuit 3 checks whether there is an error in the take. At this time, the explanatory data or 〒) similar to the included data is read n! If L, output signal 105 is generated and sent to the next stage circuit, and blade signals 106 and 107 do not become active.

However, if there is a 1-bit error in the read data, the read data is corrected by the read data JJCC circuit 3, and the output signal 105, which has been properly MJ-marked, is sent out to the input signal. At this time, data error detection of 1 bit and
07 becomes an input signal to the flip-flop 6, and the flip-flop 6 is set to -.

'1jjl Noritubfrog 6 output @ , 11
1 is input to the sense circuit, which is sensed by the firmware.

At this time, the address register circuit 8 of the second address register circuit 8 is transferred to the address register circuit 7 of the sword, and at the same time the output signal 112 of the address register circuit 7 of the address register 7 of the address register 7 and the output data 104 of the address register circuit 7 of stored in the second H% color circuit i,+b 10; This operation is a 1-bit data error detection signal 1 (1
7 is the response register circuit Mj1iS 8'-bar 70-count-Q114 is active and is input to the Noritsu flop circuit 9. Output 18 of the Noritsubu flop circuit 9
No. 115 is a sensing function in the firmware, and by sensing it, data is collected as an output signal 116 when an error occurs from the second temperature record, and C1 logging is performed. I want to operate the book as ¥19 (
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jl! It is easy to measure the improvement of 4'i, -.

``Memory scan'' when measuring reeds gj+47.1
When the '1 error occurs, the 81 person chi Δ number 108 becomes active and the output signal 109 of the OR circuit 4 is stored in the error register circuit 5. '-Also, if an error of 2 or more bits is detected in the master take, read 1 to data ECC
The output signal 106 of the circuit 3 becomes active indicating that a data error of 2 pins or more has been detected, and the output signal 109 of the logic A' circuit 4 becomes active.
This causes the error register circuit 5'4 to be set, and the output/opening force 110 indicates that a serious failure has occurred, and the input signal 1 of the control 1 circuit in the next stage is This becomes a report signal as a sense byte.

[Efficacy of invention]

As explained above, the present invention stores the contents of the address register circuit and the data contents of the first storage circuit section in the second storage circuit section at the time when a one-bit failure occurs. By reporting the occurrence of an overflow in the circuit section to an operator or maintenance person as logging information, the storage element can be repaired or replaced as needed, thereby improving the operating rate of the system.

[Brief explanation of the drawing]

FIG. 1 is a basic block diagram of one embodiment of the present invention.

Claims (1)

[Claims] a first storage circuit section storing a data input signal;
a first address register circuit that supplies an address to the storage circuit section of the memory circuit; an error detection and correction code generation circuit for write data having a data error detection function of 2 or more bits and a data error detection and correction function of 1 bit; a data error detection and correction circuit that generates an uncorrectable 2-bit or more data error detection signal and a correctable 1-bit data error detection signal; and a data error detection and correction circuit that is set when the correctable 1-bit data error detection signal is generated. a flip-flop circuit to be added and a second address register circuit to be added; the contents of the first address register circuit and the data read from the first storage circuit section when the erroneous detection signal is generated; The second memory circuit section and the second address register circuit overflow.