JPH0758478B2 - 1-bit inversion error processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A processing method of a 1-bit inversion error in which a soft report is sent to a higher-level device when a 1-bit inversion error occurs in a data read of a memory device. The purpose is to prevent the frequent occurrence of inversion error software reports. When a 1-bit inversion error occurs, the error occurrence address is compared with the previous error occurrence address, and when the occurrence address matches, the error occurrence counter is incremented, Only when the value of the error occurrence counter reaches a predetermined value, the error occurrence is reported to the host device.

[Industrial field of application] The present invention makes a soft report to a higher-level device when a 1-bit inversion error occurs in data reading of a memory device.
The present invention relates to a bit inversion error processing method.

In recent years, a memory device provided in a general-purpose information processing device has been highly integrated. When the α-ray flying from outer space hits the memory device due to the high integration, the data bit of the memory position which received the α-ray. Is inverted from bit "1" to bit "0", for example.

Therefore, when the data of the address which has undergone the bit inversion by the α ray is read, the 1-bit inversion error occurs as a so-called soft error.

[Prior Art] Conventionally, in a general-purpose information processing device, when a 1-bit inversion error occurs in a read of a memory device, as shown in an operation flow chart of FIG. 6, a data logging device that stores an error occurrence address in an appropriate logging table. After processing, in order to prevent the recurrence of the 1-bit inversion error, the 1-bit error mask is applied by the timer for a certain period of time to close the error bit, and the error occurrence is softly reported. 1 bit inversion error is EC
Since it is modified by the C circuit and sent to the upper device,
The upper device is not affected by the 1-bit inversion error.

[Problems to be Solved by the Invention] Therefore, even if a 1-bit inversion error occurs at the time of reading due to bit inversion by α ray, a soft report is made even though it is not a hard error, and an error warning is displayed to the operator. Is issued.

In particular, if bit inversion due to α-rays occurs in a data portion that is frequently used, an error report will be frequently made to the operator, and the operator will judge that the error is a hard error and the memory device This will result in taking measures such as hardware replacement.

Of course, in order to prevent the soft report of the 1-bit inversion error caused by the bit inversion by the α line, the error occurrence can be eliminated by performing the error correction by the read / write processing from the host device to the bit inversion data by the α line. it can.

However, if the memory device is accessed by another processor following the read operation in which the 1-bit inversion error occurs, the error cannot be corrected by the read / write processing until the access is completed. Therefore, error correction by read / write processing cannot be done easily.

Further, in order to correct the error by the read / write processing immediately after the error occurs, it is necessary to newly provide a suppressor circuit that prohibits the access of other processors, which complicates the circuit configuration and increases the cost. There is a demerit to invite.

The present invention has been made in view of such conventional problems, and provides a 1-bit inversion error processing method for preventing frequent occurrence of soft reporting of 1-bit inversion error due to bit inversion by α-rays. The purpose is to provide.

[Means for Solving Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

In FIG. 1, 10 is a host device, 12 is a memory device, and an input / output interface for connecting these to an external device.
An information processing device is configured by I / O.

When a 1-bit inversion error occurs in the read operation from the host device 10, the memory device 12 logs the error occurrence address, corrects the 1-bit inversion error, and outputs the corrected error to the host device 10. Further, when the upper-level device 10 receives the error occurrence report of the 1-bit inversion error, the higher-level device 10 performs the read / write processing using the bright time after that to the memory device 12
Correct 1-bit inversion error.

Further, the memory device 12 compares the error occurrence address An with the previous error occurrence address An-1 after logging, and when the occurrence addresses match, the error occurrence counter C is incremented by +1.
It counts up, and when the value of the counter C reaches a predetermined value N, for example, N = 10, the error occurrence is reported to the host device 10.

On the other hand, when the generated addresses do not match, that is, when the 1-bit inversion error is first detected, the counter C is cleared (cleared to C = 1) and the error occurrence is reported to the host device 10. In response to this error report, the higher-level device 10
The 1-bit inversion error of the memory device 12 is corrected by the read / write processing in the idle time when the memory device 12 is released.

[Operation] Even if a 1-bit inversion error occurs due to bit inversion by α ray, if an error occurs at the same address, soft report is not performed to the host device until the number of 1-bit inversion error occurrences reaches a predetermined value. It can be prevented that an error report of a 1-bit inversion error frequently occurs and the operator mistakenly recognizes it as a hard error and takes action such as hardware replacement.

Further, since it is necessary to generate a predetermined number of 1-bit inversion errors before the soft report of the 1-bit inversion error is made, it is possible to give a timing to correct the error occurrence address by the write access of the host device during this period. As a result, it is possible to eliminate the soft report of the 1-bit inversion error caused by the bit inversion by the α ray.

[Embodiment] FIG. 2 is an explanatory view showing an embodiment of the present invention.

In FIG. 2, 10 is a host device and 12 is a memory device. In this embodiment, only the signal system for the read operation by the host device 10 is shown.

The memory device 12 is provided with a highly integrated data memory 14, which reads corresponding data by designating a read address from the host device 10 and sends the read data to the host device 10 via the ECC circuit 16. I am doing it. Further, the memory device 12 is provided with a logging table 18 which logs an error occurrence address when a 1-bit inversion error occurs when reading the data memory 14, and receives a 1-bit inversion error detection output obtained from the ECC circuit 16. The error occurrence address is stored in the logging table 18, and the data stored in the logging table 18 is read by the host device 10 at the time of maintenance or the like so that the error occurrence situation can be viewed.

In addition to the configuration of the memory device 12 as described above, an address comparison unit 20, a counter 22, and a counter comparison unit 24 are provided in order to realize the 1-bit inversion error processing operation of the present invention.

That is, the address comparison unit 20 reads 1 from the data memory 14.
When a bit inversion error occurs, the current error occurrence address An and the previous error occurrence address An-1 stored in the logging table 18 are compared. For example, if the address matches, the H level output is output, and if the address does not match, It produces an L level output.

The counter 22 counts the number C of occurrences of 1-bit inversion error at the same address. When receiving the comparison output of the address coincidence which becomes the H level from the address comparison unit 21, the counter comparison unit 24 performs comparison processing until then. Number C
Is incremented by +1. Also, the address comparison unit
When the address mismatch comparison output of L level 20 is generated, it is cleared by the inverted output of the inverter 26, and when the counter 22 is cleared, the initial value C = 1 is restored.

The counter comparison unit 24 compares the count value C of the counter 22 with a predetermined value N set in advance, for example N = 10, and counts the counter count value C.
Is smaller than the predetermined value N, the count value C of the counter 22 is incremented to C = C + 1. On the other hand, when it is equal to the predetermined value N of the counter count value C, it indicates that a 1-bit inversion error has occurred to the upper level device 10. Make a soft report.

The L level output due to the address mismatch in the address comparison unit 20 is inverted by the inverter 26 to clear the counter 22 and at the same time, to output the software report of the error occurrence to the host device 10.

Next, the operation of processing the 1-bit inversion error in the embodiment of FIG. 2 will be described with reference to the operation flow chart of FIG.

First, in a normal data read in which bit inversion by α rays has not occurred, as shown in FIG.
The 8-bit data corresponding to the designation of the read address from the host device 10 for 14 is read and sent as it is to the host device.

On the other hand, if the α line hits the data memory 14 and bit inversion occurs in the second bit of the specific 8-bit data as shown in FIG. The data in which the eye "1" is inverted to bit "0" is read, the ECC circuit 16 corrects the 1-bit inversion error and sends it to the host device 10, and at the same time, the 1-bit inversion error detection signal is output as the output of the ECC circuit 16. can get.

When the detection output of the 1-bit inversion error is obtained by reading the data memory 14 in this manner, the operation flow of FIG. 3 is executed.

First, in step S1, a data logging process of storing the address in which the 1-bit inversion error has occurred in the logging table 18 is performed. Then, in step S2, in order to prevent the recurrence of the 1-bit inversion error due to the reading of the same address, the error-occurring bit is masked by a timer for a certain period of time.

Subsequently, in step S3, the previous error occurrence address An-1 is read from the logging table 18, and in step S4 it is determined whether or not the address is the same as the current error occurrence address An.

At this time, the previous error occurrence address An-1 = XB,
Assuming that the error occurrence address An = XA this time (however, the error occurrence address XB is a 1-bit inversion error due to a software error other than the α ray), the error occurrence addresses do not match, so the process proceeds to step S5 and the counter twenty two
The count value C of C is cleared to C = 1, and in step S6, the host device
Soft report of error occurrence to 10. That is, the probability of a 1-bit inversion error due to α rays occurring in a large number of memory elements is extremely small, and when an inversion error occurs at another address, it is likely to be a read error.

On the other hand, if both the previous error occurrence address An-1 and the current error occurrence address An are "XA" in step S4, that is, if the data address bit-inverted by the α line is reread, In step S7, the count value C of the counter 22 is checked. That is, the counter
It is checked whether the count value C of 22 is less than or equal to a predetermined value N, for example N = 10. At this time, if the counter count value C is smaller than the predetermined value N, the process proceeds to step S8, the count value C of the counter 22 is counted up to C = C + 1, and the next 1-bit inversion error is detected without software reporting. .

The counter check may be performed after the count up.

On the other hand, when the counter count value C matches the predetermined value N in step S7, the process proceeds to step S5 and the counter 22 is set to C = 1.
Then, in step S6, the occurrence of a 1-bit inversion error is soft-reported.

According to such a 1-bit inversion error processing method of the present invention, even if a 1-bit inversion error occurs due to bit inversion by α-ray, the same 1-bit inversion occurs after the soft report is made at the first error occurrence. Soft reporting to the host device is not performed until the occurrence of an error is repeated a predetermined value N, for example N = 10 times, and it is possible to prevent frequent soft reporting of 1-bit inversion errors due to bit inversion by α rays.

Further, since the soft report is not performed until the 1-bit inversion error occurs N times the predetermined value, sufficient time is secured for the write access to the error occurrence address from the host device and correction during this period. Corrects the error occurrence address portion by the read / write processing on the condition that the other memory does not access the data memory 14. Therefore, the 1-bit inversion error is corrected by the write access of the host device before the soft report is made,
As a result, it is possible to prevent generation of unnecessary soft report of 1-bit inversion error.

In the embodiment shown in FIG. 2, the previous error occurrence address An-1 is read from the logging table and compared with the current error occurrence address An by the address comparison unit 20, but It is also possible to provide a dedicated register for storing the error occurrence address of and to perform the address comparison between the previous and present error occurrence addresses.

Further, as described above, the location where the 1-bit inversion error due to α rays occurs is substantially fixed. Therefore, for example, when the read access to the data memory 14 is a specific area having a plurality of locations, an address comparison unit is provided for each area, and it is configured to manage whether or not the addresses are the same for each area. May be.

[Effects of the Invention] As described above, according to the present invention, with respect to a 1-bit inversion error caused by bit inversion due to α-rays, an error warning is frequently displayed by software reporting without adding a hardware circuit function. Can be prevented.

In addition, the memory device performs the process of counting up the number of occurrences when the previous and present error occurrence addresses are compared and counting up when they match, and when a predetermined value is reached. It does not need to be changed and does not affect the processing speed of read operations.

That is, according to the present invention, for example, 10 times of 1-bit inversion error of the same address is received from the upper device receiving the error report by the first detection of the 1-bit inversion error until the next error report of the same address is received. It is necessary to detect, and by effectively utilizing the vacant time during this period, the host device can perform correction by read / write processing of the address in which the 1-bit inversion error occurs with sufficient margin.

[Brief description of drawings]

1 is an explanatory view of the principle of the present invention; FIG. 2 is an explanatory view of an embodiment of the present invention; FIG. 3 is an operation flow chart of the embodiment of FIG. 2; FIG. 4 is an ordinary data read explanatory view; FIG. 5 is an explanatory diagram of data read when a 1-bit inversion error occurs; FIG. 6 is a conventional 1-bit inversion error operation flow chart. In the figure 10: Host device 12: Memory device 14: Data memory 16: ECC circuit 18: Logging table 20: Address comparison unit 22: Counter 24: Counter comparison unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Ikeda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References JP 59-117643 (JP, A) JP 62-120557 (JP, A) JP-A-61-114344 (JP, A)

Claims (1)

[Claims] 1. A host device (10) and a memory device (12), wherein when a 1-bit inversion error occurs in data reading of the memory device (12), an error occurrence address is logged and included in the read data. In the information processing apparatus which corrects the 1-bit inversion error and outputs it to the host device (10), the memory device (12) stores the error occurrence address (An) and the previous address when the 1-bit inversion error occurs. The error occurrence address (An-1) is compared, and when the occurrence addresses do not match, the error occurrence counter (C) is cleared and an error is reported to the host device (10). When the occurrence addresses match, the error occurrence counter ( C) is counted up, and when the value of the error occurrence counter (C) reaches a predetermined value (N), the error occurrence is reported to the host device, and the device (10) further comprises:
A 1-bit inversion error of the memory device (12) is corrected by a subsequent read / write process using a free time when an error occurrence report of the 1-bit inversion error is received. Processing method.