JPS6232822B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a storage device, and particularly to a storage device that can improve the detection rate of an error detection and correction function.

Prior Art In a storage device, during a write operation, information obtained by adding an error correction code (ECC) to an information code is stored in a storage medium, and during a read operation, the stored contents are read out, and if there is a 1-bit error,
The error can be corrected, and if there is a 2-bit error, it can be detected. Such a code for 1-bit error correction and 2-bit error detection is called a Hamming code.

Conventional storage devices with error detection and correction functions are
As shown in FIG. 1, the access device is composed of a write register 2, a Hamming generator 3, a storage section 4, a read register 5, a Hamming checker 6, a decoder 7 for pointing out error bits, and an error correction circuit 8. A write operation or a read operation is instructed from the processing device 1 as a memory.

That is, during a write operation, when write information is sent from the processing device 1 to the storage unit 4 via the write register 2, the Hamming generator 3 generates a Hamming code from the write information, and combines the write information and its Hamming code. is stored in the storage unit 4 at the specified address. On the other hand, during a read operation, the read information and its Hamming code are read from the storage section 4 at the specified address into the read register 5, a syndrome (error code) is generated by the Hamming checker 6, and the decoder 7 decodes it. After pointing out the error bit, if it is a 1-bit error, the error correction circuit 8 corrects the error. Here, the humming generator 3 and the humming checker 6 are parity generation circuits configured according to an error correction parity generation matrix, and the decoder 7 decodes error positions according to the error correction parity generation matrix. Furthermore, the error correction circuit 8 is constituted by a circuit that outputs the exclusive OR of each information code and the corresponding syndrome decoding circuit output.

FIG. 2 is a diagram showing an example of a Hamming code for explaining the error detection and correction operation of FIG. 1.

Figure 2 shows the case where an 8-bit Hamming code C is added to an 8-byte information code.
The Hamming generator 3 generates a Hamming code C based on these 8-byte information codes,
The Hamming checker 6 extracts the bit positions marked with ○ from the 72 bits of the information code and the Hamming code C to obtain error codes _S0 to _S7 , and sends them to the decoder 7.
By decoding this, 1 bit error, 2
Detects the location of bit errors. In Figure 2,
Positions other than those marked with ○ are portions not related to error detection and correction.

By the way, in the storage device 9 equipped with error detection and correction functions as shown in FIGS. 1 and 2, a failure or the like occurs in the storage section 4, and the information read from the storage section 4 and the Hamming code are lost. If there is an error and all the values are "0", the general even number check mode cannot detect the error, so there is a risk of erroneous processing. Conversely, the odd check mode has the disadvantage that if the information and the Hamming code accidentally become all "1"s, the error cannot be detected as before. Note that the case where the information and Hamming code are all "0" is a failure mode that may occur due to a failure such as the read strobe signal not being output, and the case where all the information and the Hamming code are "1" This is a failure mode due to a failure such as failure of the reset signal of the read register 2.

Furthermore, in the prior art, even at the expense of reliability, the humming generator 3 and the humming generator
In order to simplify the checker 6, it is common for each byte to have the same configuration. However, in recent years, there has been a remarkable improvement in device reliability, and it has also become essential to improve the error detection rate. Therefore, as a countermeasure to this problem, a method has been proposed to eliminate the above drawback by changing the check code C, breaking up the same configuration in bytes, and rearranging the check codes. to
As the number of LSI types increases, LSI development costs and LSI
This will lead to an increase in the unit price. We also improved the conventional technology,
If the error detection rate is improved by changing the check code, it not only requires a large change in the hardware, but also requires a change in the maintenance/diagnosis program, which has the drawback of increasing the number of design steps.

Purpose of the Invention The purpose of the present invention is to improve the detection rate of read errors by only making simple circuit changes and without changing the check code, in order to eliminate the conventional drawbacks as described above, and to improve the read error detection rate without changing the check code. The object of the present invention is to provide a storage device that can satisfy a correction function.

General Description of the Invention In order to achieve the above object, the storage device of the present invention includes an error detection and correction code generation section, a storage section, an error check section for information read from the storage section, and an error correction section. A first inverting circuit for inverting a part of the check bits generated by the error detection and correction code generating section; has a second inversion circuit for restoring the
After some of the test bits are inverted by the first inverting circuit, they are written together with information into the storage section, and after the test bits read from the storage section are inverted by the second inverting circuit, errors are inverted along with the information. It is characterized by being input to the inspection section.

Embodiments of the invention and their effects Examples of the invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a storage device showing an embodiment of the present invention, and FIG. 4 is a diagram for explaining the operation of FIG. 3.

In FIG. 3, the same symbols as in FIG. 1 indicate the same things. 10 and 11 are inverting circuits that invert a part of _the Hamming bits. In the _{case of FIG} . storage unit 4
Hamming bit C ₀ ~
Out of C ₇ , only 3 bits of C ₅ to C ₇ are inverted by the inverting circuit 11.
Invert it again and return it to its original state. Therefore, the input of the humming checker 6 becomes the same as the output of the humming generator 3, and if the inverting circuits 10 and 11, that is, the memory section 4 is in normal operation, the error detection and correction method is exactly the same as the original error detection and correction method. A normal check can be performed depending on the method.

However, as mentioned above, if there is an abnormality in the timing signal or control signal of the storage section 4 and all the outputs of the storage section 4 become "0", the check
Since the bits _C5 to _C7 are inverted to "1" by the inverting circuit 11, the output of the humming checker 6 becomes an error display with error codes _S5 to _S7 . That is, as shown in FIG. 4, since the bit position of the black circle is "1", the error codes _S0 to _S7 are (00000111). This error code does not meet the definition of a 1-bit error code in FIG. 2, and is detected as an undefined bit error.

In addition, as shown on the right side of FIG. 4, the inverting circuit 10
If the output of the storage unit 4 becomes all " ₁ " due to an error that occurs between and S ₇ becomes (11111000).
Since this error code also does not conform to any one-bit error code, it is possible to correctly detect an error.

In this way, even if an error occurs due to a failure occurring in the storage unit 4, correct error processing can be performed by adding simple inversion circuits 10 and 11, and the detection rate can be improved. In addition, since there is no need to change the maintenance diagnosis program, it is possible to reduce design man-hours and reduce post-process management man-hours.

In the embodiment, the inverting circuits 10 and 11 are installed separately, but the invention is not limited to this, and the humming generator 3 and the humming generator
By partially improving the checker 6, it is possible to perform internal reversal. That is, if there are 9-bit or 10-bit circuits in the Hamming generator 3 and Hamming checker 6, 8 bits are used for normal information and check codes, and the remaining 1 or 2 bits are used for inversion. Just modify the circuit. It is also possible to perform inversion and re-inversion using only one inversion circuit.

Furthermore, in the embodiment, the bits to be inverted are 3 bits _C5 to C7 among the Hamming codes _{C0 to C7} , but if it is an undefined bit that allows error detection, the Hamming codes _{C0 to C7} can be inverted. Any of _C7 or any number of bits can be inverted. The undefined bit is, for example, a code other than the 1-bit error code shown in FIG.

Further, in the embodiment, a case of 1-bit error correction/2-bit error detection is shown, but other methods such as 1-bit and 2-bit error correction can also be applied.

Effects of the Invention As explained above, according to the present invention, by providing a simple inverting circuit, the detection rate of the error detection and correction function can be improved, so there is no need to employ irregular Hamming codes. Therefore, since the Hamming code becomes regular, there are fewer types of LSIs and the prices are lower. Furthermore, since the Hamming code is not changed in order to improve the detection rate, there is no need to change the maintenance diagnosis program, making it possible to reduce design man-hours and post-process management man-hours.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional storage device, FIG. 2 is a diagram showing an example of a Hamming code for explaining the operation of FIG. 1, and FIG. 3 is a configuration diagram of a storage device showing an embodiment of the present invention. FIG. 4 is a diagram for explaining the operation of FIG. 3. 1: processing device, 3: humming generator,
4: storage section, 6: humming checker, 7: decoder, 8: error correction circuit, 10, 11: inversion circuit.

Claims (1)

[Claims] 1. A storage device that performs error detection and correction, comprising an error detection and correction code generation section, a storage section, an error check section for information read from the storage section, and an error correction section. The apparatus includes means for inverting a part of the check bits generated by the error detection and correction code generating section, and an inverting means for restoring the check bits inverted by the inverting means; is inverted by the above-mentioned inverting means, and then written into the above-mentioned storage section along with the information, and after a part of the test bits read from the storage section is re-inverted by the same or separate inversion means, the above-mentioned bits are written together with the read information. A storage device for inputting data to an error checking section. 2. The storage device according to claim 1, wherein each of the inversion means is an inversion means in which the inside of an error detection and correction code generation section and an error check section are partially modified.