JPS63141153A - Semiconductor external memory device - Google Patents

Semiconductor external memory device

Info

Publication number
JPS63141153A
JPS63141153A JP61286683A JP28668386A JPS63141153A JP S63141153 A JPS63141153 A JP S63141153A JP 61286683 A JP61286683 A JP 61286683A JP 28668386 A JP28668386 A JP 28668386A JP S63141153 A JPS63141153 A JP S63141153A
Authority
JP
Japan
Prior art keywords
data
fault
error
memory part
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61286683A
Other languages
Japanese (ja)
Inventor
Ichirou Shirasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61286683A priority Critical patent/JPS63141153A/en
Publication of JPS63141153A publication Critical patent/JPS63141153A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform the correction of a fixed error of one bit and to enhance error correcting capability, by storing a fault designating data which represents the fixed error position of a data memory in a registration memory part.
CONSTITUTION: An information processor 2 detects the fixed error of the data memory part 12, and generates the fault designating data 15a based on a detected result, and writes it on the data registration memory pat 15. Afterwards, a data 2a is inputted to a redundant code generating part 11, and a redundant code 11b is generated at every data bit of one block, and it is written on a prescribed address on the data memory part 12 with the data bit 11a. Next, when the data is read out, a prescribed address signal 2c is inputted to the data memory part 12, and simultaneously, it is inputted to the registration memory part 15, then, the fault designating data 15a is read out, and after the data error due to the fixed fault of the data bit 11a is corrected at a data corrector 13, error correction and detection are performed by a redundant code 13b.
COPYRIGHT: (C)1988,JPO&Japio
JP61286683A 1986-12-03 1986-12-03 Semiconductor external memory device Pending JPS63141153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61286683A JPS63141153A (en) 1986-12-03 1986-12-03 Semiconductor external memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61286683A JPS63141153A (en) 1986-12-03 1986-12-03 Semiconductor external memory device

Publications (1)

Publication Number Publication Date
JPS63141153A true JPS63141153A (en) 1988-06-13

Family

ID=17707616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61286683A Pending JPS63141153A (en) 1986-12-03 1986-12-03 Semiconductor external memory device

Country Status (1)

Country Link
JP (1) JPS63141153A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010092459A (en) * 2008-07-17 2010-04-22 Marvell World Trade Ltd Data recovery in solid state memory device
JP2014120195A (en) * 2012-12-12 2014-06-30 Hgst Netherlands B V Method for encoding and decoding with use of combination number system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010092459A (en) * 2008-07-17 2010-04-22 Marvell World Trade Ltd Data recovery in solid state memory device
JP2014120195A (en) * 2012-12-12 2014-06-30 Hgst Netherlands B V Method for encoding and decoding with use of combination number system

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