JPS5860497A - Error detection control system - Google Patents

Abstract

PURPOSE:To reduce circuit delay and to speed access to a storage device through simple constitution, by using a parity circuit and an error correction detecting circuit partially in common, and putting them in parallel operation. CONSTITUTION:Outputs of parity check generator circuits PCG1-PCG6 of an error detecting and correcting circuit ECC which responds to pieces of readout in formation D00-D15, etc., and a readout check bit RCB are compared mutually by exclusive OR circuits EOR1-EOR6 to generate a syndrome SDM. Signals ECU, ECL, and DL based upon error detection and correction which correspond to the syndrome SDM control exclusive OR circuits EOR9 and EOR10, thereby controlling the inversion, etc., of parity bits from the parity generating circuit PCG6 and parity check generator PCG7 for common use with the circuit ECC of the parity generating circuit PCG. Writing is the same and the simple constitution of the circuit ECC and circuits PCG used partially in common perform the generation of parity bits, and detection and correction, etc., in parallel to reduce circuit delay, thereby speeding access to a storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection side (1) control system for performing parity check of write data and creation of check bits, error detection and correction of read data, and creation of parity bits.

As an error checking method in a storage device, a parity check is used on the data bus, and an error 9 detection 11j correction method using check bits is adopted in the storage device.

In such a conventional error detection control system, there is a parity circuit that performs parity check and parity bit creation, and an error detection and correction circuit that performs check bit creation and error detection and correction such as 1-bit error 9 correction and 2-bit error detection. It was common to connect the circuits in cascade. Therefore, when the circuit size becomes relatively large, it is necessary to change the parity bit when performing KX error correction, which has the disadvantage that access to the storage device becomes slow due to circuit delay time.

An object of the present invention is to provide an economical configuration by sharing a part of the parity circuit and the error detection and correction circuit, and to reduce the delay time of the circuit.

Examples will be described in detail below.

Figure 1 shows the praise data and 1f! of the storage device MKM. “(−
2 is a block diagram of a configuration for checking output data, in which write data applied via a data bus DBi undergoes a parity check in a parity check circuit PC, is added to a storage device MEM, and is also sent to an error detection circuit. E
A check bit is created based on the write data, and the check bit is added to the storage device M along with the write data.
Written to EM.

Furthermore, when reading from the memory device MEM, read data and check bits are applied to an error detection circuit EC, a syndrome is created and applied to a correction circuit COH, and if there is an error in the read data, it is corrected.

Then, a parity bit is created in the parity creation circuit PG, and the data to which the parity pit has been added is sent onto the data bus DB.

FIG. 2 is a block diagram of main parts of an embodiment of the present invention, and 1
The error detection and correction circuit FCC is inside the dotted line, and the parity circuit PCG is inside the two-dot chain line. Also, PCGI to PCG7 are integrated circuit parity check generation circuits, EOR
1~EORIO is an exclusive OR circuit, N0RI.

N0R2 is a NOR circuit. Also, the data is 16 bits ((
3) When DOO to D15), the error detection and correction circuit l8CC requires six parity check generation circuits PCG1 to l)CG6 each receiving 8 bits, and the parity circuit PCG requires two parity check generation circuits PCG1 to D15). Check generation circuit PCG6, POC7' (r required, validity check generation circuit PC06k
An example of shared use is shown.

Also, WCBU parity check generation circuit PCG
Six check bits created by PCG1 to PCG6 are added to the storage device. RCB is a 6-bit check bit read together with the read data from the storage device. SDM is a syndrome of the outputs of exclusive OR circuits EOR1 to EOR6.

When writing all data, 16-bit write data DOO~
Upper pie of D15) DOO~DO'lj Parity check generation circuit PCG7, lower pie 1-D08
~D15 is parity check generation circuit PCG6
At the same time, 8 bits of a predetermined order are added to the parity generator circuits PCGI to PCG5. Par (4) Retention check generate circuit PCG7. POC3
Parity check results and upper bytes DOO~D
parity bit added to O7) DPUI and parity bit DPLI added to lower bytes D08 to D15
are compared by exclusive OR circuits FOR7 and EOR8, and when they match, it is a parity error, so the parity error signals PEU and PEL become "0", and an interrupt is issued to, for example, a processor (not shown). Also, when there is a mismatch, the parity error signals PEU and PEL are °゛1#
becomes. Also parity check generation circuit PCGI
The output of ~PCG6 becomes check bit WCB and is added to the storage device along with the write data.

The read data DOO to D15 read from the storage device are sent to the parity check generation circuit PCG as in the case of writing.
I~Check pick added to PCG7 and read out)R
CB is added to exclusive OR circuits EORI-EOR6.

Parity check generation circuit PCGI~PCG6
Syndrome SDM is formed by comparing the output of and check bit RCB, and as a result of analysis of syndrome SDM in a correction circuit (not shown), if a 1-bit error in the upper byte is detected, the current signal ECU becomes "1n". ,
Also, when a 1-bit error in the lower byte is detected, the signal EC
L becomes "'l". Also, if there is a 2-bit error, the A word D
E becomes 1”.

Also parity check generation circuit PCG7.

POC3 output is exclusive, t7 times circuit OR9, EORI
O, the read data has no error, and the signal ECU,
ECL.

If DE is all It OIt, /7 circuit N0RI
, the output of N0R2 becomes °゛1'', and the output of parity check generator circuit PCG7.
O, DPLO is output. For example, if there is a 1-bit error in the upper byte, that error bit is the syndrome SDM.
When corrected in a correction circuit (not shown) using 'i,
The signal ECU from the correction circuit is '°B, signal ECL
.

Since DE becomes "parity 0", it is the parity bit added to the upper byte when there is no error in the read data) DPU
O will be inverted and becomes the correct parity bit.

In addition, in the case of a 2-pit error, the signal DE becomes u I II, and the outputs of the NOR circuits N0RI and N0R2 become 0''', so the outputs of the parity check generator circuits PCG7 and PCG6 remain as parity pits) DP-UO , DPLO.In this case, the detection of 2-bit error 9 causes an interrupt to the processor, for example.

The integrated circuit parity check generation circuits PCGI-PCG7 in the above-mentioned embodiments are configured such that if, for example, there is an odd number of II I IT in the input 8 bits,
It has a logic configuration that outputs ``1'', and outputs °'o'''1 when there is an even number of parity bits. In this case, the parity bit is 1'' when there is an odd number of par 1'' in the upper and lower bytes. It is something to do. Also parity check generation circuit PC
GI to PCG7 If all exclusive OR circuits are used, the total number of shared parts can be further increased.

As explained above, the present invention includes a parity circuit PCG that performs a parity check on write data and creates a parity bit to be added to read data, and a parity circuit PCG that performs a parity check on write data and creates a parity bit to be added to read data, and a The parity circuit PCG has an error detection and correction circuit ECC12, each of which is composed of a plurality of parity check generation circuits, so that a part of the circuit is shared and the parity bits DPUO and DPLO are generated from the read data by the parity circuit PCG. , When error correction is performed by the error detection circuit FCC, the parity bit is also corrected, and the parity bit creation and error detection and correction are performed in parallel, and one bit error is corrected]7/ This can be corrected correctly by inverting the parity bits and adding the corrected correct read data. In addition, since the parity check of the write data and the creation of the WCB (check pin) are performed in parallel, it is possible to save money by sharing parts and to reduce the delay time of the circuit. Therefore, item 1 has the advantage of reducing the time required to access the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a configuration for checking errors in write data and read data of a storage device, and FIG. PCG is a Harrity circuit, ECC is an error detection and correction circuit, P
CGI to PCG7 are parity check generation circuits, WCB is the created check bit), RCB is the read check bit, SDM is the syndrome, and EEOR
1~EORIO is exclusive OR circuit, DPUI, DP
LI is the parity bit added to the write data, DPU
O. DPLO is a parity bit added to read data. Patent Applicant: Fujitsu Limited Representative Patent Attorney Hisashi Tamamushi Gobe (3 others) (8)

Claims (1)

[Claims] It has a parity circuit that performs a parity check on write data and creates a parity bit to be added to read data, and an error detection and correction circuit that creates check bits for write data and detects and corrects errors in read data. A part of a plurality of parity check generation circuits, each of which is configured by the parity circuit and the error detection and correction circuit, is shared by the parity circuit and the error detection and correction circuit, and a parity bit is generated by the parity circuit from the read data. An error detection control system characterized in that when the error detection and correction circuit corrects an error, a parity bit by the parity circuit is also corrected.