JPS61116871A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS61116871A JPS61116871A JP23965384A JP23965384A JPS61116871A JP S61116871 A JPS61116871 A JP S61116871A JP 23965384 A JP23965384 A JP 23965384A JP 23965384 A JP23965384 A JP 23965384A JP S61116871 A JPS61116871 A JP S61116871A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- source
- wiring
- electrode
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 14
- 239000010408 film Substances 0.000 claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 description 7
- 229910052715 tantalum Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 101100203658 Mus musculus Spag1 gene Proteins 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000003580 lung surfactant Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、製造の歩留りの向上を図った構造を有する薄
膜トランジスタ（以下ＴＰＴと略す）に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a thin film transistor (hereinafter abbreviated as TPT) having a structure designed to improve manufacturing yield.
（従来技術）
近年、ぽ晶のアクティブマトリクス表示において、絶縁
性基板上にＴＦＴをマトリクス状に形成したアクティブ
・マトリクス基板の研究が活発に行なわれている。半導
体材料として、ポリＳ１、ａ−３ｉ 、 Ｔｅ 、 Ｃ
ｃｌＳｅ等がある。ａ−３ｉを用いｔこＴＦＴ＋７）構
造の一例を第４図の部分断面図及び第５図の部分平面図
に示す。第４図は、ｔｐＩＳ図のＡ−Ａ線での断面を示
す。プラス基板１の上に、ゲート電１２．２．・・・を
連結するゲート配ｍ３を膜厚２ ｏ ｏ Ｏ−３旧）Ｏ
入のＴａ、 Ｍｏ、 Ｔ ｉ、 Ａ １等の金属により
形成する。デート配ｔＱ３には枝分れ部３ａが設けられ
、ＴＦＴは枝分れ部３！を中心に形成される。ゲート絶
縁膜４は、プラズマＣ＼ｉＤによって形成した膜厚１
ｆｉ Ｕ ｌ）〜２０００人の窒化シリコン（以下Ｓｉ
Ｎｘと略す）股である。（第５図においては、図示しな
い。）ａｓｉ屑ｓは、プラズマＣＶＤＩこより膜厚１
（ｌ ＯＯ〜３ ｏ ｏ ｏ人に形成する。ソース電極
６，６１・・・を連結するソース配線７をデート配線３
に直交して形成する。(Prior Art) In recent years, active matrix substrates in which TFTs are formed in a matrix on an insulating substrate have been actively researched in active matrix displays using polycrystalline crystals. As semiconductor materials, poly S1, a-3i, Te, C
There are clSe etc. An example of a TFT+7) structure using a-3i is shown in the partial cross-sectional view of FIG. 4 and the partial plan view of FIG. 5. FIG. 4 shows a cross section taken along line A-A of the tpIS diagram. On the positive substrate 1, gate electrodes 12.2. The gate arrangement m3 connecting... has a film thickness of 2 o o O-3 old) O
It is formed from metals such as Ta, Mo, Ti, and A1. A branch portion 3a is provided in the date distribution tQ3, and the TFT is provided in the branch portion 3! formed around. The gate insulating film 4 has a film thickness of 1 formed by plasma C\iD.
fi U l) ~ 2000 people silicon nitride (hereinafter Si
(abbreviated as Nx) is the crotch. (Not shown in FIG. 5.) ASI scraps are removed from plasma CVDI to a film thickness of 1
(l OO~3o
formed perpendicular to.
ソース電極６とドレイン電極８とは、ともに膜厚２ （
１１＋ １１−１１１０旧）人のＴａ、 Ｍｏ、 Ｔｉ
、ＡＣ等の金属により形成する。なお、ソース電極６及
びドレイン電極８とａ−Ｓｉ薄膜の間に、リンをドープ
した膜厚Ｓ ０１１−２０１３ （１人のａ−３ｉ膜９
を介在させると、ソース環１ｆｉ６、ドレイン電１販８
とａ−３ｉ層５のオーミックコンタクトがとれ、好まし
い、こうして、デート配置３とソース配線２
７どの又点毎に’ｒ Ｆ Ｔ
が７レイ状に形成される。Both the source electrode 6 and the drain electrode 8 have a film thickness of 2 (
11+ 11-1110 old) people's Ta, Mo, Ti
, AC, or other metal. Note that between the source electrode 6 and drain electrode 8 and the a-Si thin film, the thickness of the phosphorus-doped film S 011-2013 (one person's a-3i film 9
When intervening, source ring 1fi6, drain electrode 1fi8
It is preferable to make ohmic contact between the a-3i layer 5 and the date arrangement 3 and the source wiring 2.
7 At every point 'r F T
is formed into 7 lays.
さらに、図示しないが、各ＴＰＴに対応する絵素電極が
、ドレイン電極８に接して形成されろ。Furthermore, although not shown, a picture element electrode corresponding to each TPT is formed in contact with the drain electrode 8.
（発明の解決すべき問題点）
ＴＰＴを用いた７クテイプ・マトリクス基板においては
、マトリクスの各配線ごとに共通のゲート配線からシグ
ナル４８号を人力し、共通のソース配線からデータ信号
を入力する。デート配線とソース配線との交点は多数で
あり、例えば２５０×２５０マトリクスにおいては、６
２５００ケ所存在する。この多数の交点のうち１ケ所で
ｔｌデート・ソース間にリークが生じると必然的に該当
するゲート配線とソース配線での十字型のライン欠陥が
発生し、実用に耐えない表示となり、７クテイプ・マト
リクス基板の歩留りはゼロとなる。デート配線とソース
配線の数が増すにつれ、デート・ソース間の絶縁の確実
性が一層要求される。(Problems to be Solved by the Invention) In a seven-tape matrix board using TPT, signal No. 48 is manually inputted from a common gate wiring for each wiring of the matrix, and a data signal is inputted from a common source wiring. There are many intersections between the date wiring and the source wiring, for example, in a 250x250 matrix, there are 6 intersections.
There are 2,500 locations. If a leak occurs between the TL date and the source at one of these many intersections, a cross-shaped line defect will inevitably occur between the corresponding gate wiring and source wiring, resulting in a display that is not suitable for practical use. The yield of matrix substrates will be zero. As the number of date lines and source lines increases, reliable insulation between the date and sources is required.
本発明者らは、デート・ソース間のリーク箇所を種々の
方法によって調べた結果、デート・ソース間のリークが
、デートのエツゾ（縁部）とソースとが交差する部分（
第５図における斜ａ部分）において特に多発することを
見い出した。この原因は、？−１絶縁膜の膜厚がデート
電極の膜Ｊ７より大きいか又は同じ程度であるゆえに、
デート配線のエフ７′の部分の膜厚が薄くなり耐圧が低
下するためと、さらに、デート絶縁膜の膜質が毛担な部
分と段差部分とて”７４なり、段差部分の力が絶縁性の
面で劣るためと考えられる。As a result of investigating leak points between date sources using various methods, the present inventors found that leaks between date sources occur at the intersection of the edge of the date and the source (
It has been found that this occurs particularly frequently in the diagonal section a) in Fig. 5. What is the cause of this? -1 Since the film thickness of the insulating film is larger than or about the same as that of the date electrode film J7,
This is because the film thickness of the F7' part of the date wiring becomes thinner and the withstand voltage decreases, and furthermore, the film quality of the date insulating film is thick and the step part becomes "74", and the force at the step part is increased by the insulation. This is thought to be because they are inferior in terms of quality.
本発明の目的は、ＴＰＴの製造の歩留りを向上させる構
造を有するＴＰＴを提供することである。An object of the present invention is to provide a TPT having a structure that improves the manufacturing yield of the TPT.
（問題点を解決するための手段）
本発明に係る薄膜）ランノスタは、絶縁性基板ｈｌこゲ
ート電極、デート絶縁膜、半導体膜、ソース電極・ドレ
イン電極の順に積層してアレイ状に形成される薄膜トラ
ンジスタにおいて、ソース電極がゲート電極の縁部に重
畳しないようｉこデート電極上に形成されていることを
特徴とする。(Means for Solving the Problems) A thin film according to the present invention) is formed in an array by laminating an insulating substrate, a gate electrode, a date insulating film, a semiconductor film, a source electrode and a drain electrode in this order. The thin film transistor is characterized in that the source electrode is formed on the i-codate electrode so as not to overlap the edge of the gate electrode.
（Ｉｔ用及び発明の効果）
本発明においては、ゲート配線の縁部とソース配線との
交差を最少とするのて゛デート・ソース間のリークの発
生が抑制され、ＴＰＴの歩留りが向上する。(For It and Effects of the Invention) In the present invention, by minimizing the intersection between the edge of the gate wiring and the source wiring, the occurrence of leakage between the gate wiring and the source is suppressed, and the yield of TPT is improved.
（実施例） 以下、添付の図面を用いて本発明の詳細な説明する。(Example) Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
ｆｊＳ１図とｆ５２図は、それぞれ、本発明の実施例の
部分平面図である。第１図ではソース配線１１を一部で
二重配線１１ｍ、１１ｂとし、ＴＰＴを二重配線の一方
１１ｂとデート配！１１２に設けた枝分れ部１２ａとで
形成する。すなわち、二重配線１１ａ、ｌｌｂは、デー
ト配線１２の枝分れｆｆ！１１２ａの一方の縁部１２ｂ
を問にして、縁部１２ｂに重畳することなく、平行に伸
びる。こうして、ＴＰＴにおいて、ソース電極がゲート
電極上にデート電極の縁部に重畳しないように形成され
る。この構造において、ゲート配線１２の縁部１２ｂと
ソース配線１１との交差部分（第１図の斜線部分）は最
少にしている。なお、二重配線としたのは、ＴＰＴを構
成する枝分れ部１２ａだけでは電流？電が不足するため
である。Figure fjS1 and Figure f52 are partial plan views of embodiments of the present invention, respectively. In FIG. 1, part of the source wiring 11 is double wiring 11m and 11b, and the TPT is arranged on one side of the double wiring 11b! It is formed by the branching part 12a provided at 112. That is, the double wires 11a and llb are branches ff! of the date wire 12. One edge 12b of 112a
, and extends parallel to the edge 12b without overlapping it. Thus, in the TPT, the source electrode is formed on the gate electrode so as not to overlap the edge of the date electrode. In this structure, the intersection between the edge 12b of the gate line 12 and the source line 11 (the shaded area in FIG. 1) is minimized. The reason for double wiring is that only the branch portion 12a that makes up the TPT can handle the current. This is due to a lack of electricity.
第２図においてはゲート配線２１を枝分れをらたない構
造とし、ソース配線２２にデート配線２１の長手方向に
伸長する枝分れ部２２ａを設け、ＴＦＴをこの枝分れ部
２２ａに形成する。その技かれ部２２ａの線幅をデート
配線２１の線幅以下にしてデート配線２１のｋｋ邪とソ
ース配線２２との交差部分（第２図の斜線部分）を最少
としている。In FIG. 2, the gate wiring 21 has an unbranched structure, the source wiring 22 is provided with a branching part 22a extending in the longitudinal direction of the date wiring 21, and the TFT is formed in this branching part 22a. do. The line width of the cut portion 22a is set to be less than the line width of the date line 21 to minimize the intersection between the date line 21 and the source line 22 (the shaded area in FIG. 2).
なお、第１図、第２図において１３．２３は夫々半導体
膜、１．１．２４は夫々ドレイン電極である。In FIGS. 1 and 2, 13.23 is a semiconductor film, and 1.1.24 is a drain electrode.
このように、第１図と第２Ｉ２１の構造のＴＦＴにおい
ては、デート配線の縁部とソース配線との交差部分（斜
線部分）は第４図と第５図とに示した従来のＴＰＴに比
べてはるかに少なくなっており、これによってデート・
ソース間のリークを大幅に減少させることができた。In this way, in the TFTs with the structures shown in FIGS. 1 and 2I21, the intersections (shaded areas) between the edge of the date wiring and the source wiring are different from those in the conventional TPTs shown in FIGS. 4 and 5. This makes it much less difficult to date.
We were able to significantly reduce leaks between sources.
ｉ１図と第２図に示した構造を有するＴＰＴは、具体的
には、第３Ｉ２Ｉ（ａ）〜（ｄ＋に示すようにｇ１造さ
れる。なお、ａ ３ ＵＩＪ（ａ） −（ｄ）ノｇ分子
ＩＩｒ面図は、第り
雪
１１ １図の構造のＴＰ
Ｔにおいて１よ、Ｂ−Ｂ線の断面を、第２図の構造のＴ
ＰＴにおいては、Ｃ−Ｃ線での断面を示す。Specifically, the TPT having the structure shown in Figure i1 and Figure 2 is constructed as shown in Figures 3I2I(a) to (d+). The g-molecule IIr surface diagram is the TP of the structure shown in Figure 11.
1 at T, take the cross section of line B-B at T of the structure shown in Figure 2.
In PT, a cross section taken along line C-C is shown.
まず、ガラス基板３１上に、２ ｔ） ０ ＋１人ｌ０
タンタル層をスパッタにより全面に被着し、ホトエツチ
ングにより、第１図または第２図の？−）配線１２．２
１の形にパターン化して、第３５Ａ（ａ）に示すように
、デート電極３２とする。次に、第３図（ｂ）に示すよ
うに、プラズマＣＶＤにより、絶縁膜である１ ５００
人厚ｌ８ｉＮｘ膜３３を、そして引続き、半導体膜であ
るＩ ５ ＋、＋ （１ｌ４のａ Ｓｉ層３４を全面
に被着する。犬に、通常のホトエツチング法によって、
このａ７Ｓｉ層３４を第１図と第２図にそれぞれ１３．
２３で示すように島状のａ−３ｉ層３４にパターン化す
る。次に、プラズマＣＶＤによりり／をドープしたａ−
３ｉ層３５を１０００人、引続き真空蒸着によりＴｉ層
３６をＩ ０００人、ＡＰ層３７を２ ｏ ｏ Ｏ＾被
着する。First, on the glass substrate 31, 2 t) 0 + 1 person l0
A tantalum layer is deposited over the entire surface by sputtering and photoetched to form the tantalum layer shown in FIG. 1 or 2. -) Wiring 12.2
1 to form a date electrode 32 as shown in No. 35A(a). Next, as shown in FIG. 3(b), an insulating film of 1500
A 18iNx film 33 with a thickness of 18cm is deposited on the entire surface, followed by a semiconductor film 34 of I 5 +,+ (1l4 thickness).
This a7Si layer 34 is shown in FIGS. 1 and 2 as 13.
The a-3i layer 34 is patterned into an island shape as shown at 23. Next, a-
A 3i layer 35 of 1,000 layers is subsequently deposited by vacuum evaporation, followed by a Ti layer 36 of 1,000 layers and an AP layer 37 of 2 o o O^.
次に、第３図（ｃ）或いは第３図（ｄ）に示すように、
ホトエツチングにより第１図または第２図のソース配線
（１１，２２）とドレイン電極（１４，２４）に対応し
てパターン化して、ソース電極、ドレイン電極とする６
なお、ｆｆ１２図に示すように、デート配線２１とソー
又配線２２との交差する部分に半導体膜２３を介在させ
ると、さらにデート・ソー人間のリークが減少する。Next, as shown in FIG. 3(c) or FIG. 3(d),
The source wiring (11, 22) and drain electrode (14, 24) in FIG. 1 or 2 are patterned by photoetching to form source and drain electrodes. When the semiconductor film 23 is interposed at the intersection between the date wiring 21 and the saw wiring 22, leakage between the date wiring and the saw wiring is further reduced.
第１図と第２図は、それぞれ、本発明の実施例の図式的
な部分平面図である。
第３図（ａ）〜（ｄ）は、本発明の実施例の製造の工程
を図式的に示す拡大部分断面図である。
第４図と第５図は、そバぞれ、従来のａ−３ｉ／ＩＭＴ
Ｉ−Ｔの図式的な部分断面図と部分平面図である。
１・・絶縁性基板、 ２・・・デート電極、３
・・ゲート配線、 ４・・・デート絶縁膜、５・
・・半導体膜、 ６・・・ソース電極、７・
・ソース配線、 訃・・ドレイン電極、２１
・・デート配線、 ２２−・・ソース配線、２２
ａ ・・枝分れ部、 ２３・・・半導体膜、２
・１・・・ドレイン電極、 ３Ｉ・・・絶縁性基板
、３２・・・ゲート電極、 ３３・・デート絶耘
膜、３４・・・半導体膜、 ３５，３６． ３’；、
・電極。1 and 2 are schematic partial plan views of embodiments of the invention, respectively. FIGS. 3(a) to 3(d) are enlarged partial cross-sectional views schematically showing the manufacturing steps of an embodiment of the present invention. Figures 4 and 5 respectively show conventional a-3i/IMT
FIG. 3 is a schematic partial cross-sectional view and a partial plan view of IT. 1... Insulating substrate, 2... Date electrode, 3
・・Gate wiring, 4・Date insulating film, 5・
・・Semiconductor film, 6・Source electrode, 7・
・Source wiring, ・・Drain electrode, 21
...Date wiring, 22-...Source wiring, 22
a...branching part, 23...semiconductor film, 2
・1...Drain electrode, 3I...Insulating substrate, 32...Gate electrode, 33...Date isolation film, 34...Semiconductor film, 35, 36. 3';,
·electrode.
Claims (4)
体膜、ソース電極・ドレイン電極の順に積層してアレイ
状に形成される薄膜トランジスタにおいて、 ソース電極がゲート電極の縁部に重畳しないようにデー
ト電極上に形成されていることを特徴とする薄膜トラン
ジスタ。(1) In a thin film transistor formed in an array by laminating a gate electrode, a gate insulating film, a semiconductor film, a source electrode and a drain electrode in this order on an insulating substrate, the source electrode should not overlap the edge of the gate electrode. A thin film transistor characterized in that it is formed on a date electrode.
スタにおいて、 薄膜トランジスタの近傍で、ソース配線が、ソース電極
を構成する部分とソース電極を構成しない部分との二重
配線になっていることを特徴とする薄膜トランジスタ。(2) In the thin film transistor recited in claim 1, the source wiring is double wiring in the vicinity of the thin film transistor, including a portion that constitutes a source electrode and a portion that does not constitute a source electrode. Features of thin film transistors.
スタにおいて、 上記の半導体膜がアモルファスシリコン薄膜であること
を特徴とする薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein the semiconductor film is an amorphous silicon thin film.
スタにおいて、 上記のゲート絶縁膜が窒化シリコン膜であることを特徴
とする薄膜トランジスタ。(4) The thin film transistor according to claim 1, wherein the gate insulating film is a silicon nitride film.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23965384A JPS61116871A (en) | 1984-11-13 | 1984-11-13 | Thin film transistor |
| GB08527474A GB2169746B (en) | 1984-11-13 | 1985-11-07 | Thin film transistor |
| DE19853539794 DE3539794A1 (en) | 1984-11-13 | 1985-11-09 | THIN FILM TRANSISTOR |
| US07/235,728 US4843438A (en) | 1984-11-13 | 1988-08-19 | Thin film transistor |
| US07/304,278 US4918494A (en) | 1984-11-13 | 1989-01-31 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23965384A JPS61116871A (en) | 1984-11-13 | 1984-11-13 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61116871A true JPS61116871A (en) | 1986-06-04 |
Family
ID=17047900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23965384A Pending JPS61116871A (en) | 1984-11-13 | 1984-11-13 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61116871A (en) |
-
1984
- 1984-11-13 JP JP23965384A patent/JPS61116871A/en active Pending
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