JPS61181164A - Manufacture of thin-film field-effect transistor - Google Patents
Manufacture of thin-film field-effect transistorInfo
- Publication number
- JPS61181164A JPS61181164A JP2225385A JP2225385A JPS61181164A JP S61181164 A JPS61181164 A JP S61181164A JP 2225385 A JP2225385 A JP 2225385A JP 2225385 A JP2225385 A JP 2225385A JP S61181164 A JPS61181164 A JP S61181164A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- photosensitive resin
- resin film
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010408 film Substances 0.000 claims abstract description 54
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052804 chromium Inorganic materials 0.000 abstract description 5
- 239000011651 chromium Substances 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 4
- 239000011159 matrix material Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 abstract description 2
- 239000007772 electrode material Substances 0.000 description 5
- 238000000354 decomposition reaction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、薄膜電界効果トランジスタの製造方法、特に
平坦化ゲート構造を有する薄膜電界効果トランジスタの
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a thin film field effect transistor, and in particular to a method for manufacturing a thin film field effect transistor having a planarized gate structure.
従来の技術
近年、液晶ディスプレイ用アクティブ・マトリクス基板
の研究開発が盛んとなっている、（たとえば、口径エレ
クトロニクス １９８２年１２−２０ Ｐ１３３１１
９８４年９−１０Ｐ２１１）。Prior Art In recent years, research and development of active matrix substrates for liquid crystal displays has become active (for example, Aperture Electronics, 1982, 12-20, P13311
9-10 P211).
アクティブ・マトリクス基板とは、画素の１つ１つにス
イッチング用トランジスタを作り込んだもので、これに
よりクロストークをなくし、液晶ディスプレイをより高
精細、高コントラストとすることができる。このスイッ
チング用トランジスタは、以前は単結晶シリコンが用い
られていたが、透過形にできないため画面が暗く、カラ
ー化ができない、大面積パネルは困難である等の理由か
ら、現在では非晶質シリコン、多結晶シリコン等を半導
体薄膜として用いた薄膜電界効果トランジスタが主流と
なっている。An active matrix substrate is one in which a switching transistor is built into each pixel, which eliminates crosstalk and allows for higher definition and higher contrast LCD displays. This switching transistor used to be made of single-crystal silicon, but it is now made of amorphous silicon because it cannot be made into a transmissive type, resulting in a dark screen, cannot be made into color, and is difficult to produce large-area panels. , thin film field effect transistors using polycrystalline silicon or the like as a semiconductor thin film have become mainstream.
第２図に従来の薄膜電界効果トランジスタの一構成例を
示す。これはスタガー型と呼ばれるものでラし、他にも
いくつかの構成例があるが（Ｓ、Ｍ、Ｓｚｅ著 Ｐｈｙ
ｓｉｃｓ ｏｆ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒＤｅｖｉ
ｃｅｓ ） 、ゲート絶縁膜、半導体薄膜、ノくツシペ
ーション膜が連続的に形成できるため、この型が一般的
に用いられている。１はガラス、石英等の透光性絶縁性
基板で、その表面にゲート電極２が形成され、ゲート絶
縁膜３を介して島状に半導体薄膜４が形成され、その表
面にソース電極６、ドレイン電極７が配設されている。FIG. 2 shows an example of the configuration of a conventional thin film field effect transistor. This is called a staggered type, and there are several other configuration examples (Phys.
sics of Sem1conductorDevi
ces), a gate insulating film, a semiconductor thin film, and a cutting film can be formed continuously, so this type is generally used. Reference numeral 1 denotes a transparent insulating substrate made of glass, quartz, etc., on the surface of which a gate electrode 2 is formed, an island-shaped semiconductor thin film 4 is formed with a gate insulating film 3 interposed therebetween, and a source electrode 6 and a drain electrode are formed on the surface of the substrate. An electrode 7 is provided.
また、半導体薄膜４の表面にはパッシベーション膜５が
設けられている。Further, a passivation film 5 is provided on the surface of the semiconductor thin film 4.
しかし、この構造の薄膜電界効果トランジスタでは、ゲ
ート電極２が最下層にあし、その上にゲート絶縁膜３、
半導体薄膜４を堆積しているため、ゲート絶縁膜３がゲ
ート電極２の段差部で段切れを起こしたり、クラックが
入ったりして、ゲート電極２とソース電極６、ドレイン
電極７間でショートシたり、リークしたりしていた。こ
のような各電極間でのショートやリークは、そのまま線
欠陥や点欠陥となし、液晶ディスプレイにとっては致命
的である。However, in a thin film field effect transistor with this structure, the gate electrode 2 is the lowest layer, and the gate insulating film 3 is formed on top of the gate electrode 2.
Because the semiconductor thin film 4 is deposited, the gate insulating film 3 may break or crack at the step portion of the gate electrode 2, resulting in short circuits between the gate electrode 2, source electrode 6, and drain electrode 7. or leaked. Such short circuits and leaks between electrodes directly result in line defects or point defects, which are fatal to liquid crystal displays.
そこで、第３図のように、ゲート電極２を、透光性絶縁
性基板１に設けられた凹部に埋設した平坦化構造を有す
る薄膜電界効果トランジスタが考案されている。（特開
昭５８−４８４６６号公報）この構造の薄膜電界効果ト
ランジスタの製造方法は、第４図ａに示すように、まず
透光性絶縁性基板１に選択的に感光性樹脂膜９を形成し
、これをマスクとして、基板１表面をエツチングして凹
部を形成する。次に第４図すに示すように、感光性樹脂
膜９を残したまま、全面にゲート電極材料２を被着形成
した後、第４図Ｃに示すように、感光性樹脂膜９を除去
して凹部に埋設されたゲート電極２を形成する。次いで
、第４図ｄに示すように、ゲート絶縁膜３、半導体薄膜
４、パッシベーション膜６を堆積し、第４図ｅに示すよ
うに島状にパターニングした後、第４図ｆに示すように
パッシベーション膜６にコンタクトホールヲ設ｆｆだ後
、ソース電極６、ドレイン電極７を形成して完成する。Therefore, as shown in FIG. 3, a thin film field effect transistor having a flattened structure in which a gate electrode 2 is buried in a recess provided in a transparent insulating substrate 1 has been devised. (Japanese Unexamined Patent Publication No. 58-48466) A method for manufacturing a thin film field effect transistor having this structure is as shown in FIG. Then, using this as a mask, the surface of the substrate 1 is etched to form recesses. Next, as shown in FIG. 4, gate electrode material 2 is deposited on the entire surface while leaving the photosensitive resin film 9, and then, as shown in FIG. 4C, the photosensitive resin film 9 is removed. Then, a gate electrode 2 buried in the recess is formed. Next, as shown in FIG. 4d, a gate insulating film 3, a semiconductor thin film 4, and a passivation film 6 are deposited and patterned into an island shape as shown in FIG. 4e, and then as shown in FIG. 4f. After forming contact holes in the passivation film 6, a source electrode 6 and a drain electrode 7 are formed to complete the process.
発明が解決しようとする問題点
しかしながら上記の製造方法では感光性樹脂膜をつけた
まま、ゲート電極材料を被着するのであるから、被着時
の温度はせいぜい１ｏｏ″Ｃまでであり、あまり高温に
はできない。このため、被着強度が弱く、ゲート電極材
料を全面に被着形成後、リフトオフしてゲート電極を形
成する際、ゲート電極として残すべきところまではがれ
てしまうことがあし、ゲート断線が生じやすいという問
題点があった。Problems to be Solved by the Invention However, in the above manufacturing method, the gate electrode material is deposited with the photosensitive resin film still attached, so the temperature at the time of deposition is at most 10''C, which is not too high. For this reason, the adhesion strength is weak, and when the gate electrode material is deposited on the entire surface and then lifted off to form the gate electrode, it may peel off to the part that should remain as the gate electrode, resulting in gate disconnection. There was a problem in that it was easy for this to occur.
本発明の目的は、前記問題点に鑑み、ゲート断線を生じ
ることなく平坦化ゲート構造を有する薄膜電界効果トラ
ンジスタを製造する方法を提供することにある。SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a method for manufacturing a thin film field effect transistor having a flattened gate structure without causing gate disconnection.
問題点を解決するための手段
上記問題点を解決するために、本発明の平坦化ゲート電
極構造の製造方法は、透光性絶縁性基板表面に選択エツ
チングによりゲート電極を形成し、その除用いた感光性
樹脂膜を残したまま、所望の厚さの透光性絶縁膜を全面
に被着形成し、その後前記感光性樹脂膜を除去して、前
記透光性絶縁膜に埋設された平坦化ゲート電極構造を形
成することを特徴とする。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a planarized gate electrode structure of the present invention involves forming a gate electrode on the surface of a light-transmitting insulating substrate by selective etching, and removing the gate electrode. A light-transmitting insulating film of a desired thickness is deposited on the entire surface while leaving the photosensitive resin film in place, and then the photosensitive resin film is removed to remove the flat surface buried in the light-transmitting insulating film. It is characterized by forming a gate electrode structure.
作用
上記のような製造方法では、最初にゲート電極を形成す
るため、ゲート電極材料の被着温度を２ｏｏ℃以上にす
ることができ、被着強度を上げることができる。しかも
、上記構造を製造する方法として、いわゆるリフトオフ
法を用いているため、きわめて簡単に自己整合的に製造
できる。Effect: In the above-described manufacturing method, since the gate electrode is formed first, the deposition temperature of the gate electrode material can be set to 200° C. or higher, and the deposition strength can be increased. Furthermore, since the so-called lift-off method is used as a method for manufacturing the above structure, it can be manufactured extremely easily and in a self-aligning manner.
実施例
以下、本発明の実施例について、図面を参照しながら説
明する。第１図２Ｌ −ｇは本発明の薄膜電界効果トラ
ンジスタの製造方法を示したものである。第４図と対応
する部分には同一の番号がつけである。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIGS. 1-2L-g show a method for manufacturing a thin film field effect transistor according to the present invention. Parts corresponding to those in FIG. 4 are numbered the same.
まず、第１図ａに示すように、ソーダガラス基板１上に
、ゲート電極材料としてクロムを基板温度２００″Ｃで
２０００人、電子ビーム蒸着し、次に第１図すに示すよ
うに、その表面に選択的に感光性樹脂膜９を形成し、こ
れをマスクとしてクロム薄膜２をエツチングしてゲート
電極２を形成する。その後、第１図ｇに示すように、感
光性樹脂膜９を残したまま、全面に窒化シリコン膜をＮ
２−ＮＨ３−ＳｉＨ４混合ガスのグロー放電分解法によ
り２０００人堆積した後、第１図ｄに示すように、感光
性樹脂膜９を除去して平坦化ゲート電極を形成する。First, as shown in Fig. 1a, chromium was deposited as a gate electrode material on a soda glass substrate 1 by electron beam evaporation at a substrate temperature of 200''C by 2000 people. A photosensitive resin film 9 is selectively formed on the surface, and using this as a mask, the chromium thin film 2 is etched to form the gate electrode 2. Thereafter, as shown in FIG. 1g, the photosensitive resin film 9 is left behind. Leave a silicon nitride film on the entire surface.
After 2,000 layers are deposited by a glow discharge decomposition method using a 2-NH3-SiH4 mixed gas, the photosensitive resin film 9 is removed to form a planarized gate electrode, as shown in FIG. 1d.
次に、第１図ｅに示すように、ゲート絶縁膜として窒化
シリコン膜３をＮ２− ＮＨ，−ＳｉＨ４混合ガスのグ
ロー放電分解法により５ｏｏｏ人堆積し、半導体薄膜と
して非晶質シリコン膜４をＳｉＨ４ガスのグロー放電分
解法により１５００人堆積し、さらにパッシベーション
膜として窒化シリコン膜５を１０００人堆積する。なお
、この三層の膜は真空を破ることなく連続的に堆積した
。その後、第１図ｆに示すように、上部窒化シリコン膜
５、非晶質シリコン膜４を所定の形状に順次選択エツチ
ングする。最後に、第１図ｇに示すように上部ｆｆｌ化
シリコン膜５にコンタクトホールを開口し、その抜工Ｔ
Ｏを全面に被着形成し、それを選択エツチングしてソー
ス電極６、ドレイン電極７を形成する。Next, as shown in FIG. 1e, 5000 silicon nitride film 3 was deposited as a gate insulating film by a glow discharge decomposition method using a N2-NH, -SiH4 mixed gas, and an amorphous silicon film 4 was deposited as a semiconductor thin film. 1500 layers are deposited by glow discharge decomposition method of SiH4 gas, and 1000 layers of silicon nitride film 5 is further deposited as a passivation film. Note that this three-layer film was deposited continuously without breaking the vacuum. Thereafter, as shown in FIG. 1f, the upper silicon nitride film 5 and the amorphous silicon film 4 are sequentially selectively etched into a predetermined shape. Finally, as shown in FIG.
O is selectively deposited on the entire surface and selectively etched to form a source electrode 6 and a drain electrode 7.
発明の効果
以上のようにして製造された平坦化構造を有する薄膜電
界効果トランジスタは、リーク電流も少なく、またゲー
ト電極配線、ソース電極配線の断線もない等、高精細大
型アクティブ・マトリクス基板を歩留まりよく製造する
には有用なものである。Effects of the Invention The thin film field effect transistor with a flattened structure manufactured as described above has low leakage current, and there is no disconnection of gate electrode wiring or source electrode wiring, etc., and has a high yield rate for high-definition large active matrix substrates. It is useful for good manufacturing.
第１図は本発明の薄膜電界効果トランジスタの製造工程
を示した図、第２図は従来の薄膜電界効果トランジスタ
の断面図、第３図は平坦化ゲート電極構造を有する薄膜
電界効果トランジスタの断面図、第４図は従来の平坦化
ゲート電極構造を有する薄膜電界効果トランジスタの製
造工程を示した図である。
１・・・・・・透光性絶縁性基板、２・・・・・・ゲー
ト電極、３・・・・・・ゲート絶縁膜、４・・・・・・
半導体薄膜、６・・・・・・パッシベーション膜、６・
・・・・・ソース電極、７・・・・・・ドレイン電極、
８・・・・・・透光性絶縁膜、９・・・・・・感光性樹
脂膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第１図
第２図
第３図
第４図
第４図
手続補正書働側
昭和６０年６３２０日Fig. 1 is a diagram showing the manufacturing process of the thin film field effect transistor of the present invention, Fig. 2 is a sectional view of a conventional thin film field effect transistor, and Fig. 3 is a sectional view of a thin film field effect transistor having a flattened gate electrode structure. 4 are diagrams showing the manufacturing process of a thin film field effect transistor having a conventional planarized gate electrode structure. 1... Translucent insulating substrate, 2... Gate electrode, 3... Gate insulating film, 4...
Semiconductor thin film, 6... Passivation film, 6.
...Source electrode, 7...Drain electrode,
8...Transparent insulating film, 9...Photosensitive resin film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 2 Figure 3 Figure 4 Figure 4 Procedural amendment form working side 6320, 1985
Claims (1)
ート電極表面にゲート絶縁膜、半導体薄膜、パッシベー
ション膜を堆積し、前記パッシベーション膜に選択的に
設けられたコンタクトホール上にソース、ドレイン電極
を形成して薄膜電界効果トランジスタを製造するに際し
、前記ゲート電極を選択エッチングにて形成した後、マ
スクとして用いた感光性樹脂膜を残したまま、所望の厚
さの透光性絶縁膜を全面に被着形成し、その後、前記感
光性樹脂膜を除去して、前記透光性絶縁膜に埋設された
ゲート電極を形成することを特徴とする薄膜電界効果ト
ランジスタの製造方法。A gate electrode is formed on the surface of a light-transmitting insulating substrate, a gate insulating film, a semiconductor thin film, and a passivation film are deposited on the surface of the gate electrode, and source and drain electrodes are formed on contact holes selectively provided in the passivation film. After forming the gate electrode by selective etching, a transparent insulating film of a desired thickness is deposited on the entire surface while leaving the photosensitive resin film used as a mask. A method for manufacturing a thin film field effect transistor, comprising: depositing the photosensitive resin film on the transparent insulating film, and then removing the photosensitive resin film to form a gate electrode embedded in the transparent insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225385A JPS61181164A (en) | 1985-02-07 | 1985-02-07 | Manufacture of thin-film field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225385A JPS61181164A (en) | 1985-02-07 | 1985-02-07 | Manufacture of thin-film field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61181164A true JPS61181164A (en) | 1986-08-13 |
Family
ID=12077618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2225385A Pending JPS61181164A (en) | 1985-02-07 | 1985-02-07 | Manufacture of thin-film field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61181164A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63251098A (en) * | 1987-04-07 | 1988-10-18 | Kanegafuchi Chem Ind Co Ltd | Production of (r)-3-halogeno-1,2-propanediol |
| JPH02143462A (en) * | 1988-11-24 | 1990-06-01 | Sony Corp | Thin film transistor |
| EP3675169A4 (en) * | 2017-08-21 | 2021-04-21 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method for manufacturing flexible display panel, and flexible display panel |
-
1985
- 1985-02-07 JP JP2225385A patent/JPS61181164A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63251098A (en) * | 1987-04-07 | 1988-10-18 | Kanegafuchi Chem Ind Co Ltd | Production of (r)-3-halogeno-1,2-propanediol |
| JPH0475760B2 (en) * | 1987-04-07 | 1992-12-01 | Kanegafuchi Chemical Ind | |
| JPH02143462A (en) * | 1988-11-24 | 1990-06-01 | Sony Corp | Thin film transistor |
| EP3675169A4 (en) * | 2017-08-21 | 2021-04-21 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method for manufacturing flexible display panel, and flexible display panel |
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