JPS61110205A - Programmable controller - Google Patents

Abstract

PURPOSE:To eliminate restrictions placed when a sequence circuit is designed and, at the time, to improve the responsiveness, by making process by selecting the event processing minimum unit of a program in accordance with an interrup tion signal. CONSTITUTION:A preset state signal Pi in putted through an interface 3 is written in a RAM12 and this signal is read out as a past state signal Li and inputted in an event processing circuit 13. The device 13 detects the occurrence of an event by comparing the signals Pi and Li with each other and discriminates the necessity and priority of the event processing, and then, sends an interruption signal Ii to a CPU1. The CPU1 refers to an event dealing table corresponding to the interruption and makes processing works by selecting the event processing minimum unit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention executes a preset program based on status signals indicating various states of the controlled object and outputs control signals to control the controlled object. The present invention relates to a programmable controller (hereinafter abbreviated as PC) equipped with an arithmetic processing means.

[Conventional technology]

FIG. 6 is a block diagram showing the configuration of a general PC.

In the figure, 1 is a central processing unit (hereinafter abbreviated as CPU) as arithmetic processing means, 2 is an output interface for control signals, 3 is an input interface for status signals from status detection means (not shown), and 4 is a random access memory ( 5 is a user program memory, 6 is a system program memory, and 7 is a system console.

When the status signal via the input interface 3 meets a predetermined condition, the predetermined control signal is output via the output interface 2 regardless of the order of control signals output in the past, or the status signal is taken into account. control signals are output in a predetermined order, and these operations are determined by a program successively output from the user program memo IJ5.

Therefore, the PC user must create a program suitable for the controlled object in advance and store it in the user program memory 5 using the system console 7 (the CPU is programmed using the 1111 in the system program memory 6 according to the control algorithm). It interprets the contents, creates a control signal according to the conditions of the status signal, and outputs it via the output interface 2 to control the controlled object.

By the way, there are three types of control algorithms for determining the relationship between status signals and control signals of this type of PC: a relay circuit simulation method, a table lookup method, and a process walk method.

Figures 7 and 8 are circuit connection diagrams showing the relay circuit simulation method, and in these figures, "
The part indicated as "input" indicates the status signal from the input interface 3, and in FIG.
In FIG. 8, due to the signal logic rlJ rOJ,
represents the logic of the corresponding state signal, the part denoted as "output" indicates the control signal from the output interface 2;
In the figure, the logic of the corresponding control signal is represented by energization or deenergization of the relay coil, and in FIG. 8, the signal logic rlJ rOJ.

FIG. 9 is a flow diagram showing the control algorithm of the relay circuit simulation method. In the figure, 8a and 8b indicate specific conditions of the status signal, and OK indicates that the condition is met, and NG indicates that the condition is not met. Condition 8a?
When OK, control output 9a2; when NG, control output 9
al, and in either case, the judgment is made under condition 8b.

FIG. 10 is a diagram showing an example of a table used in the table lookup method, in which the table number (TABLENO), status signal logic (INPUT), control signal logic (0[
ITPUT) are stored in correspondence. Therefore, this table is read out in order of table number.

FIG. 11 is a flow diagram showing the control algorithm in the table lookup method.
BLE NO001 continues and the condition of INPIIT is checked and if it is OK, the control output becomes 9c and 0 in this table.
The control signal RY2-1. shown in IITPUT. After outputting Ll=1, the process moves to condition 8d (ie, TABLHN0002), and if condition 8c is NG, the process immediately moves to condition 8d.

FIGS. 12 and 13 are diagrams showing the process step system, respectively. FIG. 12 shows the case where the process table is stored in the memory, and FIG. 13 shows the case where the process table is set on a pin board. In FIG. 13, 10 is a pin board panel, and 11 is a control pin. FIG. 14 is a flowchart showing the control algorithm of the step-by-step method. For example, if the condition 8f is the condition LS2=1 of 5TEP NO01 in FIG.
The control signals for 5OLI-1 and 5OL2-0 shown in the figure are output, and if NG, the process does not proceed to the next step until the conditions become OK. Note that some of the steps shown in FIGS. 9, 11, and 14 are omitted from explanation, but 8 (
9 (with an alpha lower case suffix) indicates the condition of the status signal, and 9 (with an alpha vent lower case suffix) indicates the control signal to be output via the output interface 2.

[Problem that the invention seeks to solve]

Since the conventional PC is configured as described above, the above three types of control algorithms are used depending on the object to be controlled. However, the conventional PCs described above inherently have the following problems.

First, regarding the design of sequential circuits, that is, programming, the relay circuit simulation method and table lookup method output control signals that correspond to the conditions determined by the current state signal, regardless of the order of control signals output in the past. Therefore, if sequential control is to be expressed using these methods, a complicated asynchronous sequential circuit will be required, and this asynchronous sequential circuit will need to be designed and its operation confirmed. On the other hand, in the step-by-step method, it is not possible to describe the case where a control signal is output whenever a predetermined condition of a status signal is satisfied, regardless of sequence control, that is, an emergency stop, an interlock, etc.

Regarding the output responsiveness of control signals to changes in state signal input, in the relay circuit simulation method and table lookup method, the CPU 1 scans the state signal input based on the processing program and cyclically processes all instructions. Therefore, the response speed becomes extremely slow. On the other hand, in the step-by-step method, only one condition judgment (for example, 8" in Fig. 14) is made at a certain point in time, so
Although the response of the corresponding control output (also 9f) is performed at high speed, it is impossible to speed up the response of all control outputs by simultaneously performing multiple condition determinations.

The present invention was made to solve such problems,
The purpose of this invention is to eliminate constraints on sequential circuit design and to obtain a programmable controller with excellent responsiveness.

[Means for solving problems]

The programmable controller according to the present invention includes a state signal storage means for storing a state signal output from the state detection means, a current state signal manually input to the storage means, and a past state signal stored in the storage means. and event processing means for comparing the comparison result, processing the comparison result, and outputting an interrupt signal to the arithmetic processing means.

(Operation) In the present invention, the event processing means compares the past state signal and the current state signal stored in the state signal storage means to detect changes in various states of the controlled object, that is, the occurrence of an event. Furthermore, the necessity and priority of control arithmetic processing regarding the detected event are determined, and an interrupt signal is output to the arithmetic processing means based on the result of this determination. Based on the interrupt signal, the arithmetic processing means selects and executes one of the minimum event processing units of the program that is preset corresponding to each event.

〔Example〕

The present invention will be explained below based on the embodiments shown in FIGS. 1 to 4. Note that the same reference numerals are used for the same or equivalent parts as in the conventional example, and the explanation thereof will be omitted. Figures 1 and 2
The figures are block diagrams showing the configuration of the PC in this embodiment, and in each figure, reference numerals 12 and 13 indicate a past state signal memory as a state signal storage means and an event processing device as an event processing means provided according to the present invention. . The past state signal memory 12 is composed of a readable and writable RAM, and receives the current state signal Pi (t=1~
nun is a state signal (the same applies hereinafter) is written, and this written state signal is read out as a past state signal Li and input to the event processing device 13. On the other hand, as shown in FIG. 2, the event processing device 13 receives the current state signal Pi and the past state signal L.
EOR circuit (exclusive OR circuit) using i and human power 14
1 and the AN provided on the output side of this EOR circuit 14i.
A logic circuit provided for each state signal consisting of a D circuit (AND circuit) 15i, and an event mask signal (interrupt Necessity information) Mi
is stored for each state signal, and the corresponding AND circuit 15i
The event mask memory 16 that is stored in
The interrupt priority determination circuit 17 inputs the output from the D circuit 15i and outputs an interrupt signal 1i to the CPUI according to a preset priority. The priority level of the interrupt priority determination circuit 17 is set such that the most recently generated interrupt signal is set to the lowest priority level.

On the other hand, FIGS. 3 and 4 are flowcharts of the event processing minimum unit of the processing program executed by cpUl when an interrupt occurs, and explanatory diagrams showing the relationship between the event processing minimum unit group and the event correspondence table.

In the figure, the event processing minimum unit group 18 consists of a plurality of event processing minimum units 18j (j = 1 to mum is the number of minimum processing units, the same applies hereinafter), which are selected based on an event correspondence table 19i provided for each status signal. Ru. Each of the above event processing minimum units 18j is a condition determination unit 8hj.
and a control output section 9hj.

Next, the operation of this embodiment configured as described above will be explained. First, each EOR circuit 1 of the event processing device 13
4i, each current state signal Pi input via the input interface circuit 3 and the past state signal Li stored in the past state signal memory 12 corresponding to the signal Pi are compared and determined. Here, if the above-mentioned signals Pi and LiO values are different, that is, the state of the corresponding part of the controlled object changes (
If an event) occurs and the status signal changes, EOR
The output value of the circuit 141 becomes "1" (true), and the occurrence of the event is detected. The output value of the EOR circuit 14i is masked by the AND circuit 15i using the corresponding event mask signal Mi of the event mask memory 16. Here, by arbitrarily setting the event mask memory 16 for human power that does not require event processing depending on the object to be controlled, it is possible to prevent unnecessary events from occurring in terms of control. That is, the value of the event mask signal Mi is "0"
In this case, even if the value of the EOR circuit 14i is rlJ (event occurrence), this information is not transmitted to the interrupt priority determination circuit 17. Therefore, the output value of the EOR circuit 141 is
” (event occurrence) and the event mask signal Mi
Only when the value of rlJO, the output value of the AND circuit 15i is also "1".
”, and the interrupt signal I is passed through the interrupt priority judgment circuit F.
f is output to the CPUI. The above interrupt priority determination circuit 1
Reference numeral 7 indicates the output value of each AND circuit 15i with a higher priority, and here outputs an interrupt signal 1i corresponding to an event to the CPUI in the order of input occurrence.

Next, the action of the CPUI when a necrosis occurs will be explained based on FIGS. 3 and 4. When the CPUI receives the interrupt signal 1i from the event processing device 13, it displays the event correspondence table 191 (FIG. 4) corresponding to the interrupt.
, and processes and executes several event processing minimum units 18j shown in the event correspondence table 19i. As shown in FIG. 3, in each event processing minimum unit 18j, the CPU evaluates the condition 8hj including the current state signal Pi, and when the condition 8hj is satisfied (OK), the control output 9hj
and performs predetermined control on the controlled object. If the condition 8hj is not satisfied (NG), this event processing minimum unit 18j is ended without any processing, and the processing moves to the next event processing minimum unit 18j+1. Therefore, according to this embodiment, the occurrence of an event is detected without scanning the input status signal of the CPUI, and the necessity and priority of processing of the detected event is determined, and an interrupt is applied to the CPUI. The response speed to the occurrence of is extremely fast. Further, by managing the settings of the event mask memory 16 and the interrupt priority determination circuit 17 of the event processing device 13, programming of the sequential circuit becomes easy.

FIG. 5 shows an example in which the CPUI is multi-CPU. In this example, when an event occurs, the management CP
U1a receives the interrupt signal Ii from the interrupt priority determination circuit 17, and the corresponding event correspondence table 19 is generated as in the above embodiment.
Refer to i. If there is a plurality of event processing minimum units 18i indicated by the event correspondence table 19i, the processing of each of the event processing minimum units 18i is performed by the processing CPUs 1b to 1.
Assign to x. When the number of event processing minimum units 18i exceeds the number of processing CPUs 1b to 1x, the management CPU
The event processing minimum rank 18i corresponding to the large number of U1a is buffered, and the processing CPU 1b-
1x sequentially.

By doing so, even faster processing becomes possible.

In each of the above embodiments, only the human-powered state signal is stored in the past state signal memory I2 and event processing is performed, but event processing (a change is treated as an event) is also performed for the output signal and internal memory of the PC. It goes without saying that it can be done.

〔Effect of the invention〕

As explained above, according to the present invention, the state signal storage means and the event processing means are provided, the occurrence of an event is detected and processed by each of the above means, and only the events that require control are processed by the calculation processing means. This has the advantage that a programmable controller with excellent responsiveness and no restrictions on sequential circuit design can be obtained.

[Brief explanation of drawings]

1 and 2 are block diagrams showing one embodiment of the programmable controller according to the present invention, FIG. 3 is a flow diagram of the minimum event processing unit, and FIG. 4 shows the relationship between the minimum event processing unit group and the event correspondence table. 5 is a block diagram showing another embodiment, FIG. 6 is a block diagram showing the general configuration of the conventional example, and FIGS. 7 to 9 are diagrams of the relay circuit simulation method in the conventional example. Connection diagrams or flow diagrams; FIGS. 10 and 11 are diagrams and flow diagrams showing an example of a table using the table look-up method; FIGS. 12 through 14 are diagrams showing an example of a table and a pin board using the process step-by-step method. It is a diagram or flowchart showing a battle. ■...Arithmetic processing means, 12...Status signal storage means,
13...Event processing means, 141°15i...Logic circuit, 16...Memory, 17...Interrupt priority determination circuit, Pi...Current state signal, Li...Past state signal, Ii... ...Interrupt signal, Mi...Interrupt necessity information. In addition, in the figures, the same reference numerals are used for the same or corresponding parts. Agent Masu Oiwa (2 others) Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 11 Figure 13 Figure 12 Figure 14

Claims (2)

[Claims] (1) Comprising arithmetic processing means for executing a preset program and outputting control signals for controlling the control object based on the status signals output from the state detection means for detecting various states of the control object. In the programmable controller, a state signal storage means for storing the state signal output from the detection means compares a current state signal inputted to the storage means with a past state signal stored in the storage means; and event processing means for processing the comparison result and outputting an interrupt signal to the arithmetic processing means, and the arithmetic processing means selects and executes the minimum event processing unit of the program based on the interrupt signal. A programmable controller featuring: (2) The event processing means detects the occurrence of an event based on the memory in which interrupt necessity information is stored for each status signal, the current status signal, and the past status signal, and stores the detected event and the memory. a logic circuit provided for each status signal that generates an interrupt signal based on correspondingly stored interrupt necessity information; and the arithmetic processing means that processes the interrupt signal from each logic circuit according to a preset priority. 2. The programmable controller according to claim 1, further comprising an interrupt priority determination circuit that outputs an output to an interrupt priority determination circuit.