JPH0792690B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention outputs a control signal for controlling a control target by executing a preset program based on a status signal indicating various states of the control target. The present invention relates to a programmable controller (hereinafter abbreviated as PC) equipped with control means for controlling.

[Conventional technology]

FIG. 6 is a block diagram showing the configuration of a general PC. In the figure, 1 is a central processing unit (hereinafter abbreviated as CPU) as an arithmetic processing unit, 2 is an output interface for control signals, 3 is an input interface for a state signal from a state detection unit (not shown), and 4 is a random access memory ( Hereinafter, abbreviated as RAM), 5 is a user program memory, 6 is a system program memory, and 7 is a system console. The CPU 1, RAM 4, and system program 6 constitute a control means.

When the status signal through the input interface 3 meets a predetermined condition, the predetermined control signal is output through the output interface 2 regardless of the order of the control signals output in the past, or the status signal is considered. However, the control signals are output in a predetermined order, and these operations are determined by the program read from the user program memory 5.

Therefore, the user of the PC creates a program suitable for the control target in advance and stores it in the user program memory 5 using the system console 7. The CPU 1 interprets the contents of the user program memory 5 according to the control algorithm in the system program memory 6, creates a control signal according to the condition of the status signal, and outputs it through the output interface 2 to control the controlled object.

By the way, there are three types of control algorithms that determine the relationship between the status signal and the control signal of this type of PC: a relay circuit simulation method, a table lookup method, and a process step method.

FIG. 7 and FIG. 8 are circuit connection diagrams showing the relay circuit simulation method, respectively, and the portion shown as “input” in these figures shows the status signal from the input interface 3, and in FIG. Contact or open, in FIG. 8 by signal logic "1""0",
The part indicating the logic of the corresponding status signal, the part indicated as “output” shows the control signal from the output interface 2,
In the figure, energization or de-energization of the relay coil is shown, and in FIG. 8, the logic of the corresponding control signal is represented by "1" or "0" of the signal logic.

FIG. 9 is a flowchart showing the control algorithm of the relay circuit simulation method. In the figure, 8a and 8b indicate specific conditions of the status signal, and OK indicates a case where this condition is met, and NG indicates that it does not. When the condition 8a is OK, the control output is 9a2, and when the condition 8a is NG, the control output is 9a1. In either case, the condition 8b is judged.

FIG. 10 is a diagram showing an example of a table used in the table lookup method, in which a table number (TABLE NO), a status signal logic (INPUT), and a control signal logic (OUTPUT) are stored in association with each other. Therefore, this table is read in the order of table numbers. FIG. 11 is a flow chart showing a control algorithm in the table lookup method.
Read TABLE NO 001 at and check the INPUT conditions, and if it is OK, the control output will be 9c and the control signal shown at OUTPUT of this table will be output.
After outputting RY2 = 1, L1 = 1, condition 8d (that is, TABLE NO
002), if condition 8c is NG, immediately move to condition 8d.

12 and 13 are diagrams showing the step progress method,
FIG. 12 shows a case where the process table is stored in the memory,
FIG. 13 shows the case where the process table is set in the pinboard. In FIG. 13, 10 is a pin board panel and 11 is a control pin. FIG. 14 is a flow chart showing a control algorithm of the step progress method. For example, the condition 8f is shown in FIG.
If the condition LS2 of O 01 is 1, the control output 9f outputs the control signal of SOL = 1 and SOL2 = 0 shown in FIG. 12 only when OK, and if NG, until the condition becomes OK. Do not proceed to the next step. Although some of the steps shown in FIG. 9, FIG. 11 and FIG. 14 have been omitted from the description, 8 (with a suffix in lower case alphabet) indicates the condition of the status signal, and 9 (suffix in lower case alphabet) Indicates the control signal output via the output interface 2.

[Problems to be solved by the invention]

Since the conventional PC is configured as described above, the above three types of control algorithms are used according to the control target. However, the above-mentioned conventional PCs inherently have the following problems.

First of all, regarding the design of the sequential circuit, that is, the programming, in the relay circuit simulation method and the table lookup method, the control signal corresponding to the condition determined by the state signal at the present time is output regardless of the order of the control signals output in the past. Therefore, if attempting to express sequential control by these methods, a complicated asynchronous sequential circuit is required, and the design of this asynchronous sequential circuit and its operation confirmation are required. On the other hand,
In the step progress method, it is not possible to describe a case where a control signal is output whenever a predetermined condition of a status signal is satisfied, that is, an emergency stop, an interlock, etc., regardless of sequence control.

Regarding the output responsiveness of the control signal to the change of the status signal input, in the relay circuit simulation method and the table lookup method, the CPU1 scans the status signal input based on the processing program and cyclically processes all the instructions. Therefore, the response speed is very slow. On the other hand, in the step progress method, only one condition judgment (for example, 8f in FIG. 14) is performed at a certain time point, so the response of the corresponding control output (also 9f) is performed at high speed,
It is impossible to make a plurality of condition judgments at the same time to speed up the response of all control outputs.

The present invention has been made to solve the above problems,
The purpose of the present invention is to obtain a programmable controller with excellent responsiveness and eliminating restrictions on sequential circuit design.

[Means for solving problems]

The programmable controller according to the present invention has a condition that a predetermined number of input signals among input signals (each current state signal Pi) which are detection outputs of a plurality of detecting means for detecting a state of a controlled object are in a predetermined state. Event processing, which is the information that consists of the input status condition (condition 8hj) that is confirmed to be satisfied in the above and control output information 9hj that is executed based on the satisfaction of this input status condition, and is the minimum unit information of the processing information that controls the control target An input signal storage means (past state signal memory 12) that has control means capable of executing the processing of the minimum unit 18j, and stores, for each detection means, information indicating the state of the input signal that is the detection output of the detection means; , The current input signal Pi and the stored content Li of the input signal storage means indicating the input signal in the past are judged whether or not they match, and if they do not match, an event signal is output. And means (EOR circuit 14i),
Event-corresponding processing content that stores information that enables selection of a predetermined number of event processing minimum units in which the state of the input signal is involved in the input state condition from the event processing minimum unit group that is a group of event processing minimum units And a storage means (event correspondence table 19i).

[Operation] In the present invention, the current input signal and the stored content of the input signal storage means indicating the past input signal are compared by the event signal output means, and if the current and past input signals do not match, the event signal Is output. Then, even when an event signal corresponding to any of the detection means is input to the control means, a predetermined number of minimum event processing units indicated by the stored content of the event-corresponding processing content storage means corresponding to the event signal are processed. , Executed by the control means.

〔Example〕

The present invention will be described below based on the embodiments shown in FIGS. 1 to 4. The same or corresponding parts as those of the conventional example are designated by the same reference numerals and the description thereof is omitted. 1 and 2
The figure is a block diagram showing the configuration of the PC in the present embodiment. In each figure, 12 and 13 are past state signal memory as state signal storage means and event processing device as event processing means provided by the present invention. . The past state signal memory 12 is composed of a readable / writable RAM and has a present state signal Pi (i = 1) input from a detection unit (not shown), for example, a state detection unit, via the input interface 3.
~ N: n is a state signal, the same applies hereinafter), and the written state signal is read as a past state signal Li and input to the event processing device 13.
On the other hand, the event processing device 13 has an EOR circuit (exclusive OR circuit) 14i to which the current state signal Pi and the past state signal Li are input, as shown in the internal configuration of FIG. 2, and the EOR circuit 14i. AND circuit (AND circuit) 15i provided on the output side
And a logic circuit provided for each status signal, and an event mask signal (interrupt necessity information) Mi indicating whether or not to interrupt the CPU 1 when a change occurs in various states of the controlled object, that is, an event. Event mask memory 16 that is stored for each signal and input to the corresponding AND circuit 15i
And an interrupt priority determination circuit 17 which inputs the output from each AND circuit 15i and outputs an interrupt signal Ii to the CPU 1 in accordance with a preset priority. The priority of the interrupt priority determination circuit 17 is set so that the interrupt signal generated most recently is the lowest here.

On the other hand, FIGS. 3 and 4 are a flow chart of the event processing minimum unit of the processing program executed by the CPU 1 when an interrupt occurs, and an explanatory diagram showing the relationship between the event processing minimum unit group and the event correspondence table. In the figure, an event processing minimum unit group 18 is a plurality of event processing minimum units 18 that constitute processing information for controlling a control target by a programmable controller.
j (j = 1 to m: m is the minimum processing unit number, the same applies hereinafter), and is selected based on the event correspondence table 19i provided for each state signal. The minimum unit for processing each event is 18i
Are input state conditions such as condition 8hj and control output information 9hj.

Next, the operation of the present embodiment configured as described above will be described. First, by the respective EOR circuits 14i of the event processing device 13, the respective input signals input via the input interface circuit 3, for example, the respective current state signals Pi and the input signal storage means, for example, in the past state signal memory 12, are stored. The past state signal Li stored corresponding to the present state signal Pi is compared and determined. That is, each EOR circuit 1 of the event processing device 13
A past state signal memory 12 is provided corresponding to 4i, and this corresponds to a plurality of detecting means, that is, each state detecting means via the interface 3. That is, each state detecting means is provided with the past state signal memory 12, the EOR circuit 14i and the event correspondence table described later. Here, if the values of the signals Pi and Li are different, that is, if the status signal changes due to a change (event) in the status of the corresponding part of the controlled object, the event signal output means, for example, the EOR circuit 14i.
Output value, that is, the event signal becomes "1" (true), and the occurrence of the event is detected. The output value of the EOR circuit 14i is masked by the corresponding event mask signal Mi of the event mask memory 16 by a mask circuit, for example, an AND circuit 15i. Here, for an input that does not require event processing according to the control target, the event mask memory 16 can be arbitrarily set to prevent the occurrence of events that are unnecessary for control. That is, if the value of the event mask signal Mi is "0", this information is not transmitted to the interrupt priority determination circuit 17 even if the value of the EOR circuit 14i is "1" (event occurs). Therefore, the output value of the AND circuit 15i also becomes "1" only when the output value of the EOR circuit 14i is "1" (event occurrence) and the value of the event mask signal Mi is "1". After that, the interrupt signal Ii is output to the CPU1. The interrupt priority judgment circuit 17 outputs to the CPU 1 the interrupt signal Ii corresponding to the event signal in the order of occurrence of inputs, whichever has the highest priority among the output values of the AND circuits 15i.

Next, the operation of the CPU1 when an interrupt occurs is shown in FIG. 3 and FIG.
It will be described with reference to the drawings. When the interrupt signal Ii is input from the event processing device 13, the CPU 1 refers to the event correspondence processing content storage means corresponding to the interrupt, for example, the event correspondence table 19i (FIG. 4), and refers to the event correspondence table 19i.
Processes and executes some event processing minimum units 18j. As shown in FIG. 3, the minimum unit of each event processing is 18
In j, the CPU 1 evaluates the condition 8hj including the current state signal Pi, that is, the condition 8hj which is satisfied on condition that a predetermined number of input signals including the current state signal Pi are in a predetermined state, and the condition 8hj is satisfied ( OK), the control output information 9hj is processed,
Predetermined control is performed on the controlled object. If the condition 8hj is not satisfied (NG), the event processing minimum unit 18j is terminated without performing any processing, and the process proceeds to the next event processing minimum unit 18j + 1. Therefore, according to the present embodiment, the occurrence of an event is detected regardless of the scanning of the input state signal of the CPU1, and the necessity or the priority of the processing of the detected event is determined and the CPU1 is interrupted. The response speed to the occurrence of is very fast. Further, by managing the settings of the event mask memory 16 and the interrupt priority determination circuit 17 of the event processing device 13, the programming of the sequential circuit becomes easy.

FIG. 5 shows an embodiment in which the CPU 1 is a multi-CPU. In this example, when an event occurs, the management CPU 1a receives the interrupt signal Ii from the interrupt priority determination circuit 17 and refers to the corresponding event correspondence table 19i as in the above embodiment.
Minimum event processing unit 18j shown in the above event correspondence table 19i
If there is more than one, the minimum event processing unit 18
The processing of j is assigned to the processing CPUs 1b to 1x. When the number of event processing minimum units 18j exceeds the number of processing CPUs 1b to 1x, the management CPU 1a has a large number of event processing minimum units 18j buffered, and the processing CPUs 1b to 1x that have finished processing are buffered.
Sequentially assigned to. By doing so, it is possible to perform even faster processing.

In each of the above-described embodiments, only the input state signal is stored in the past state signal memory 12 and the event processing is performed, but the event processing (change is regarded as an event) is also performed on the output signal of the PC and the internal memory. It goes without saying that you can do it. Further, since the event processing minimum unit is selected according to the event correspondence table 19i, it is not necessary to store a plurality of the same event processing minimum units, and there is an effect that the memory capacity can be saved. Also, event correspondence table 19
By changing the contents of i, the operation can be partially changed without affecting the whole process, which has the effect of facilitating debugging.

Further, since the AND circuit 15i functioning as a mask circuit and the interrupt priority determining circuit 17 functioning as a priority determining circuit are provided, there is an effect that programming of the sequential circuit can be facilitated.

〔The invention's effect〕

As described above, according to the present invention, for each detection means for detecting the state of the controlled object, it is determined whether or not the input signal storage means and the current and past input signals match, and if they do not match. For example, an event signal output means for outputting an event signal, and an event corresponding processing content storage means for storing information enabling selection of a predetermined number of event processing minimum units in which the state of the input signal is involved in the input state condition. Even when an event signal corresponding to any of the detecting means is input to the control means, processing by a predetermined number of event processing minimum units selected based on the stored content of the event corresponding processing content storage means corresponding to the event signal Since the control means is executed, when a change occurs in the input signal, the processing related to the event signal is immediately executed and the input signal is processed. Reduction is prevented the occurrence of dead time such as time required for scanning the locations not, it is possible to increase the processing speed of the programmable controller, a significant increase in the memory capacity can be prevented, the effect of further debugging can be easily.

[Brief description of drawings]

1 and 2 are block diagrams showing an embodiment of a programmable controller according to the present invention, FIG. 3 is a flow chart of the minimum unit of event processing, and FIG. 4 shows the relationship between the minimum unit of event processing and the event correspondence table. FIG. 5 is a block diagram showing another embodiment, FIG. 6 is a block diagram showing a general configuration of a conventional example, and FIGS. 7 to 9 show a relay circuit simulation method in the conventional example. Connection diagram or flow diagram, FIGS. 10 and 11 are diagrams and flow diagrams showing an example of a table of the table lookup method,
FIG. 12 to FIG. 14 are diagrams or flow charts showing an example of a step-progressing type table and pin board. 1 ... Arithmetic processing means, 12 ... Status signal storage means, 13 ...
Event processing means, 14i, 15i ... Logic circuit, 16 ... Memory, 17 ... Interrupt priority determination circuit, Pi ... Current state signal,
Li ... Past status signal, Ii ... Interrupt signal, Mi ... Interrupt necessity information. In the drawings, the same reference numerals are used for the same or corresponding parts.

Claims (2)

[Claims] 1. A programmable control system having a plurality of detection means for detecting a state of a controlled object and controlling the controlled object based on predetermined processing information while referring to respective input signals which are detection outputs of the respective detecting means. In the controller, this is information consisting of an input state condition that is confirmed to be satisfied on condition that a predetermined number of the input signals are in a predetermined state, and control output information that is executed based on the satisfaction of this input state condition. Input signal storage means for storing the input signal, which is the detection output of the detection means, for each of the detection means, having a control means capable of executing the processing of the minimum unit of event processing which is the minimum unit information of information, It is determined whether or not the current input signal and the stored contents of the input signal storage means indicating the input signal in the past match. If they do not match, the state of the input signal is involved in the input state condition from the event signal output unit that outputs an event signal and the event processing minimum unit group that is a collection of the event processing minimum units that form the processing information. A case in which the event signal corresponding to any of the detecting means is input to the control means, Also, the programmable controller is characterized in that the control means executes processing by a predetermined number of the minimum event processing units selected based on the stored content of the event corresponding processing content storage means corresponding to the event signal. 2. An event mask memory that stores information indicating whether or not to mask the event signal, and a mask circuit that prevents the event signal from being transmitted to the next stage based on the stored contents of the event mask memory. A priority determination circuit that outputs the event signal to the next stage according to a preset priority, and the event signal that has passed through the mask circuit and the priority determination circuit is transmitted to the control means. The programmable controller according to claim 1.