JPS61107232U - - Google Patents
Info
- Publication number
- JPS61107232U JPS61107232U JP1984192340U JP19234084U JPS61107232U JP S61107232 U JPS61107232 U JP S61107232U JP 1984192340 U JP1984192340 U JP 1984192340U JP 19234084 U JP19234084 U JP 19234084U JP S61107232 U JPS61107232 U JP S61107232U
- Authority
- JP
- Japan
- Prior art keywords
- buffers
- activated
- positive integer
- tristate
- wired
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Pulse Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984192340U JPS61107232U (enExample) | 1984-12-19 | 1984-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984192340U JPS61107232U (enExample) | 1984-12-19 | 1984-12-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107232U true JPS61107232U (enExample) | 1986-07-08 |
Family
ID=30749762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984192340U Pending JPS61107232U (enExample) | 1984-12-19 | 1984-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107232U (enExample) |
-
1984
- 1984-12-19 JP JP1984192340U patent/JPS61107232U/ja active Pending
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