JPS61102047A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61102047A JPS61102047A JP22460284A JP22460284A JPS61102047A JP S61102047 A JPS61102047 A JP S61102047A JP 22460284 A JP22460284 A JP 22460284A JP 22460284 A JP22460284 A JP 22460284A JP S61102047 A JPS61102047 A JP S61102047A
- Authority
- JP
- Japan
- Prior art keywords
- region
- wiring
- layer
- diffusion region
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路の素子電極及び配線の構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of element electrodes and wiring of integrated circuits.
従来、高耐圧集積回路素子においては耐圧を確保するた
めに高比抵抗のサブストレートまたはエピタ中シャル層
を用いている几め、その高比抵抗の半導体上の配線にそ
れよりも大きな電圧(半導体がN型の場合は低い電圧、
P型の場合は高い電圧)が絶縁膜を介して加わつ九とき
高比抵抗の半導体層が容易に反転し、チャ7ネルリーク
が発生したり、耐圧劣化等の問題が生じる。そのため配
線はそのような事が起こらない所を通すようにしなけれ
ばならず、配線の自由度が非常に小さくなる、
マ九、チャンネルリークや耐圧劣化が生じないように考
慮して配線しても、電界により絶縁膜上に集まってくる
イオンのために高比抵抗層が反転する事がある。Conventionally, high-voltage integrated circuit devices have used a high-resistivity substrate or an epitaxial layer to ensure voltage resistance, and a higher voltage (semiconductor is N type, the voltage is low,
When a high voltage (in the case of P type) is applied through the insulating film, the high resistivity semiconductor layer is easily reversed, causing problems such as channel leakage and breakdown voltage deterioration. Therefore, the wiring must be routed in a place where such things will not occur, and the degree of freedom in wiring will be extremely small. , the high resistivity layer may be inverted due to ions that gather on the insulating film due to the electric field.
本発明の目的はチャンネルリークや耐圧劣化の生じない
高耐圧集積回路素子を得ることにある。An object of the present invention is to obtain a high voltage integrated circuit element that does not suffer from channel leakage or breakdown voltage deterioration.
本発明によれば半導体領域内の素子領域から導出される
電極は半導体領域と素子領域とのなすPN接合を極力お
おうように広く形成され、素子領域間の配線は電極上に
層間絶縁膜を介して形成さn几上層配線でなされる半導
体集積回路を得る。According to the present invention, the electrode led out from the element region in the semiconductor region is formed widely so as to cover the PN junction formed between the semiconductor region and the element region as much as possible, and the wiring between the element regions is formed on the electrode via an interlayer insulating film. A semiconductor integrated circuit is obtained, which is formed using n-layer wiring.
本発明によれば素子領域と配線との間の金属層で素子領
域をおおっているので、配線に加わる電圧や配線にもと
づく電界によって生じるイオ/の集中等の影響を素子領
域が受けることはなく、素子領域の極性反転や耐圧劣化
を生じることがない。According to the present invention, since the element area is covered with a metal layer between the element area and the wiring, the element area is not affected by the concentration of ions caused by the voltage applied to the wiring or the electric field based on the wiring. Therefore, polarity reversal and breakdown voltage deterioration in the element region do not occur.
このためチャ/ネルリークも防止でき、高耐圧の半導体
集積回路を得ることができる。また、配線の自由匿も大
きく、この点でも半導体集積回路の集積密度を向上でき
る。Therefore, channel/channel leakage can also be prevented, and a semiconductor integrated circuit with high breakdown voltage can be obtained. Furthermore, the freedom of wiring is great, and in this respect as well, the integration density of semiconductor integrated circuits can be improved.
次に、図面を参照して、本発明をより詳細に説明する。 Next, the present invention will be explained in more detail with reference to the drawings.
第4図囚、但)は従来の半導体装tを示したもので、半
導体基板11上に半導体層1’に有し、この半導体層1
は分離拡散領域5で多数の島状領域に分離されるととも
に、島状領域内では半導体層1と半導体基板11との間
に埋め込み領域6を有している。さらに島状領域にはベ
ース拡散領域2とエミッタ拡散領域3とコレクタ電極取
出拡散領域4とを有している。半導体J#1上に形成さ
n7’c酸化膜9の開孔を介して各拡散領域2,3.4
から電極10が取り出されており、を極10は層間絶縁
膜8を介して上層配線7と交差している。FIG. 4(a) shows a conventional semiconductor device t, which has a semiconductor layer 1' on a semiconductor substrate 11.
is separated into a number of island-like regions by a separation diffusion region 5, and has a buried region 6 between the semiconductor layer 1 and the semiconductor substrate 11 within the island-like region. Furthermore, the island-like region has a base diffusion region 2, an emitter diffusion region 3, and a collector electrode extraction diffusion region 4. Each diffusion region 2, 3.4 is formed on the semiconductor J#1 through an opening in the n7'c oxide film 9.
An electrode 10 is taken out from the electrode 10, and the electrode 10 intersects with the upper layer wiring 7 via the interlayer insulating film 8.
各拡散領域2,3.4から導出される電極10は位置合
せの余裕を見込んだ広さで形成されるので、例えば、ベ
ース拡散領域2から導出された電極10はベース拡散領
域2上に形成されベース・コレクタ接合に達していない
。エミッタ拡散領域3上の電極lOも同様である。この
ため、上層配線7に高電圧が加わると半導体層1に反転
チャンネル13が生じて、ベース拡散領域2と分離拡散
領域5間にリーク1r流を生じる。また上層配#i17
に加わる高電圧により、その下のPN接合を形成するP
型もしくはN型領域の不純物濃度が増して接合耐圧を劣
化せしめることもある。Since the electrodes 10 led out from each diffusion region 2, 3.4 are formed with a width that allows for alignment margin, for example, the electrode 10 led out from the base diffusion region 2 is formed on the base diffusion region 2. and does not reach the base-collector junction. The same applies to the electrode lO on the emitter diffusion region 3. Therefore, when a high voltage is applied to the upper layer wiring 7, an inversion channel 13 is generated in the semiconductor layer 1, and a leakage current 1r is generated between the base diffusion region 2 and the isolation diffusion region 5. Also upper layer #i17
The high voltage applied to the P
The impurity concentration in the type or N-type region may increase, degrading the junction breakdown voltage.
第1図囚、(B)は本発明の一実施例を示すもので、第
4図と同じものには同じ参照符号を付して説明を省略す
る。ベース拡散領域2.エミッタ拡散領域3から導出さ
れる電極10は導出された領域が隣接する領域と形成す
るPN接合上を極力おおうように広く形成されている。FIG. 1(B) shows an embodiment of the present invention, and the same parts as in FIG. 4 are given the same reference numerals and the explanation thereof will be omitted. Base diffusion region 2. The electrode 10 led out from the emitter diffusion region 3 is formed wide so that the led out region covers as much as possible the PN junction formed with the adjacent region.
素子間の配線は全て上層配線7で形成されている。□上
層配線7同志が交叉する所では電極10を交叉用配線と
して用いている。All wiring between elements is formed by upper layer wiring 7. □An electrode 10 is used as a crossing wiring at a place where the upper layer wirings 7 intersect with each other.
電極10はこの電極10が導出された領域とその隣接す
る領域とのなすPN接合を越えて広く形成されているの
で、上層配線7に加わる高電圧によって生じる極性反転
チャ/ネル13はベース拡散領域2と分離拡散領域5間
で電極lOの下には生じない。従って、ベース拡散領域
2と分離拡散領域5間にリーク電流は生じない。又ベー
ス拡散゛ 領域2と半導体層1とで形成されるPN接
合の不純物濃度も上層配線7に加わる電圧によって変化
しないので、耐圧劣化も生じない。上層配線7に加わる
電圧によって生じる層間絶縁膜8に生じるイオ7の集積
も電極10下のPN接合に影響を与えることはない。同
様の効果はエミッタ拡散領域3から導出される電極10
丁の領域にも生じる。Since the electrode 10 is formed widely beyond the PN junction formed between the region where the electrode 10 is led out and its adjacent region, the polarity inversion channel/channel 13 caused by the high voltage applied to the upper layer wiring 7 is formed in the base diffusion region. 2 and the separation diffusion region 5 and does not occur under the electrode IO. Therefore, no leakage current occurs between the base diffusion region 2 and the isolation diffusion region 5. Further, since the impurity concentration of the PN junction formed between the base diffusion region 2 and the semiconductor layer 1 does not change due to the voltage applied to the upper layer wiring 7, no breakdown voltage deterioration occurs. The accumulation of ions 7 in the interlayer insulating film 8 caused by the voltage applied to the upper layer wiring 7 does not affect the PN junction below the electrode 10. A similar effect can be obtained from the electrode 10 derived from the emitter diffusion region 3.
It also occurs in the area of Ding.
第2図は半導体層lに拡散抵抗11’i形放した場合の
実施例で、拡散抵抗21の両端から導出される電極10
′は拡散抵抗11の領域をそnぞれ広くおおって、上層
配線7に接続領域12で接続され、上層配線7で他の素
子との接続がなされている、
第3図囚、(B)は半導体層lに横方向トランジスタを
形成した場合の実施例である。半導体層lの島状領域に
は反対導電型のエミッタ領域23と環状のコレクタ領域
22と同一導電型のベース1極導出領域24が形成され
ている。これら各領域22゜23.24から導出で詐る
電極lO/′はそれぞれの領域上を広くおおっている。FIG. 2 shows an embodiment in which a diffused resistor 11'i type is provided in the semiconductor layer l, and electrodes 10 led out from both ends of the diffused resistor 21 are shown.
' widely covers the region of the diffused resistor 11, is connected to the upper layer wiring 7 in the connection region 12, and is connected to other elements through the upper layer wiring 7, Fig. 3 (B). This is an example in which a lateral transistor is formed in a semiconductor layer l. An emitter region 23 of opposite conductivity type, an annular collector region 22, and a base unipolar lead-out region 24 of the same conductivity type are formed in the island-like region of the semiconductor layer l. The electrode lO/' derived from each of these regions 22°, 23.24 widely covers each region.
上層配線7の交叉に環状コレクタ領域22につらなる電
極10“でなされている。The electrode 10'' is connected to the annular collector region 22 at the intersection of the upper layer wiring 7.
これら第2図および第3図の実施例でも第1図の実施例
と同様の効果がある。The embodiments shown in FIGS. 2 and 3 also have the same effect as the embodiment shown in FIG.
このように、本願発明によればチャノネルリークがなく
、高耐圧で集積度の高い集積回路を得ることができる。As described above, according to the present invention, it is possible to obtain an integrated circuit with no channel leakage, high breakdown voltage, and high degree of integration.
第1図囚、(B)は本発明の一実施例を示す平面図およ
び断面図である。
第2図は本発明の他の実施例を示す平面図である。
第3図(5)、 (B)は本発明の更に他の実施例を示
す平面図および断面図である。
第4図(5)、(B)は従来の半導体装置を示す平面図
および断面図である。
1・・・・・・半導体装、2・・・・・・ベース拡散領
域、3・・・・・・エミッタ拡散領域、4・・・・・・
コレクタ電極導出拡散領域、5・・・・・・分離拡散領
域、6・・・・・・埋込み領域、7・・・・・・上層配
線、8・・・・・・層間絶縁膜、9・・川・酸化膜、1
0.10’ 、10“・・・・・・電極% 11・・
・・・・半導体基板、12・・・・・・接続領域、21
・・・・・・拡散抵抗、22・・・・・・環状コレクタ
領域、23・・・・・・エミ、り領域、24・・・・・
・ベース電極導出領域。
、ノ
N、−一′
猶21
早3TiJFIG. 1(B) is a plan view and a sectional view showing an embodiment of the present invention. FIG. 2 is a plan view showing another embodiment of the invention. FIGS. 3(5) and 3(B) are a plan view and a sectional view showing still another embodiment of the present invention. FIGS. 4(5) and 4(B) are a plan view and a sectional view showing a conventional semiconductor device. 1...Semiconductor device, 2...Base diffusion region, 3...Emitter diffusion region, 4...
Collector electrode lead-out diffusion region, 5... Separation diffusion region, 6... Buried region, 7... Upper layer wiring, 8... Interlayer insulating film, 9...・River・Oxide film, 1
0.10', 10"... Electrode% 11...
... Semiconductor substrate, 12 ... Connection region, 21
... Diffusion resistance, 22 ... Annular collector region, 23 ... Emitter region, 24 ...
・Base electrode lead-out area. , NON, -1' 21 early 3TiJ
Claims (1)
領域と、半導体領域上に前記素子領域から導出され該素
子領域をほぼおおって延長される電極と、該電極上に層
間絶縁膜を介して形成される上層配線とを有し、素子領
域間の配線は前記上層配線を介して行なわれることを特
徴とする半導体装置。An element region of one conductivity type formed in a semiconductor region of another conductivity type, an electrode led out from the element region on the semiconductor region and extended to almost cover the element region, and an interlayer insulating film formed on the electrode. 1. A semiconductor device comprising an upper layer wiring formed through the upper layer wiring, and wiring between element regions is performed through the upper layer wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59224602A JPH0622236B2 (en) | 1984-10-25 | 1984-10-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59224602A JPH0622236B2 (en) | 1984-10-25 | 1984-10-25 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61102047A true JPS61102047A (en) | 1986-05-20 |
JPH0622236B2 JPH0622236B2 (en) | 1994-03-23 |
Family
ID=16816292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59224602A Expired - Lifetime JPH0622236B2 (en) | 1984-10-25 | 1984-10-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0622236B2 (en) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5141978A (en) * | 1974-10-07 | 1976-04-08 | Suwa Seikosha Kk | HANDOTA ISOCHI |
JPS5489594A (en) * | 1977-12-27 | 1979-07-16 | Nec Corp | Manufacture for integrated circuit |
JPS5643005U (en) * | 1979-09-11 | 1981-04-20 | ||
JPS57106153A (en) * | 1980-12-24 | 1982-07-01 | Nec Corp | Semiconductor device |
JPS57176749A (en) * | 1981-04-24 | 1982-10-30 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS57181141A (en) * | 1981-04-30 | 1982-11-08 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-10-25 JP JP59224602A patent/JPH0622236B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5141978A (en) * | 1974-10-07 | 1976-04-08 | Suwa Seikosha Kk | HANDOTA ISOCHI |
JPS5489594A (en) * | 1977-12-27 | 1979-07-16 | Nec Corp | Manufacture for integrated circuit |
JPS5643005U (en) * | 1979-09-11 | 1981-04-20 | ||
JPS57106153A (en) * | 1980-12-24 | 1982-07-01 | Nec Corp | Semiconductor device |
JPS57176749A (en) * | 1981-04-24 | 1982-10-30 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS57181141A (en) * | 1981-04-30 | 1982-11-08 | Toshiba Corp | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPH0622236B2 (en) | 1994-03-23 |
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