JPS61102047A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the polarity inversion, etc. of a diffusion region by previously forming an electrode coating an adjacent P-N junction additionally onto an opening in an oxide film coating the region while being positioned on the base of an inter-layer insulating film when the diffusion region is shaped to the surface layer section of a semiconductor substrate, the opening is bored to the oxide film and an upper layer wiring is formed through the inter-layer insulating film. CONSTITUTION:A semiconductor layer 1 with a buried region 6 is formed insularly by an isolation diffusion region 5, and a base region 2 and an emitter region 3 positioned in the base region 2 are diffused and formed to the surface layer section of the layer 1 and a collector leading-out region 4 to the semiconductor layer 1 respectively. The whole surface is coated with an oxide film 9, openings are bored, an upper layer wiring 7 is applied onto the oxide film 9 through an inter-layer insulating film 8, an the wiring 7 is connected to each region, but electrodes 10 coating adjacent P-N junctions are each shaped previously onto the openings in the regions 2 and 3 while being positioned on the base of the film 8 at that time. These electrodes 10 are connected to the wiring 7 through the openings formed to the film 8. Accordingly, no polarity inversion, withstanding-voltage deterioration, etc. is generated in the regions 2 and 3 in the presence of the added electrodes 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of element electrodes and wiring of integrated circuits.

[Conventional technology]

Conventionally, high-voltage integrated circuit devices have used a high-resistivity substrate or an epitaxial layer to ensure voltage resistance, and a higher voltage (semiconductor is N type, the voltage is low,
When a high voltage (in the case of P type) is applied through the insulating film, the high resistivity semiconductor layer is easily reversed, causing problems such as channel leakage and breakdown voltage deterioration. Therefore, the wiring must be routed in a place where such things will not occur, and the degree of freedom in wiring will be extremely small. , the high resistivity layer may be inverted due to ions that gather on the insulating film due to the electric field.

[Problem that the invention seeks to solve]

An object of the present invention is to obtain a high voltage integrated circuit element that does not suffer from channel leakage or breakdown voltage deterioration.

[Means for solving problems]

According to the present invention, the electrode led out from the element region in the semiconductor region is formed widely so as to cover the PN junction formed between the semiconductor region and the element region as much as possible, and the wiring between the element regions is formed on the electrode via an interlayer insulating film. A semiconductor integrated circuit is obtained, which is formed using n-layer wiring.

[Effect]

According to the present invention, since the element area is covered with a metal layer between the element area and the wiring, the element area is not affected by the concentration of ions caused by the voltage applied to the wiring or the electric field based on the wiring. Therefore, polarity reversal and breakdown voltage deterioration in the element region do not occur.

Therefore, channel/channel leakage can also be prevented, and a semiconductor integrated circuit with high breakdown voltage can be obtained. Furthermore, the freedom of wiring is great, and in this respect as well, the integration density of semiconductor integrated circuits can be improved.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 4(a) shows a conventional semiconductor device t, which has a semiconductor layer 1' on a semiconductor substrate 11.
is separated into a number of island-like regions by a separation diffusion region 5, and has a buried region 6 between the semiconductor layer 1 and the semiconductor substrate 11 within the island-like region. Furthermore, the island-like region has a base diffusion region 2, an emitter diffusion region 3, and a collector electrode extraction diffusion region 4. Each diffusion region 2, 3.4 is formed on the semiconductor J#1 through an opening in the n7'c oxide film 9.
An electrode 10 is taken out from the electrode 10, and the electrode 10 intersects with the upper layer wiring 7 via the interlayer insulating film 8.

Since the electrodes 10 led out from each diffusion region 2, 3.4 are formed with a width that allows for alignment margin, for example, the electrode 10 led out from the base diffusion region 2 is formed on the base diffusion region 2. and does not reach the base-collector junction. The same applies to the electrode lO on the emitter diffusion region 3. Therefore, when a high voltage is applied to the upper layer wiring 7, an inversion channel 13 is generated in the semiconductor layer 1, and a leakage current 1r is generated between the base diffusion region 2 and the isolation diffusion region 5. Also upper layer #i17
The high voltage applied to the P
The impurity concentration in the type or N-type region may increase, degrading the junction breakdown voltage.

FIG. 1(B) shows an embodiment of the present invention, and the same parts as in FIG. 4 are given the same reference numerals and the explanation thereof will be omitted. Base diffusion region 2. The electrode 10 led out from the emitter diffusion region 3 is formed wide so that the led out region covers as much as possible the PN junction formed with the adjacent region.

All wiring between elements is formed by upper layer wiring 7. □An electrode 10 is used as a crossing wiring at a place where the upper layer wirings 7 intersect with each other.

Since the electrode 10 is formed widely beyond the PN junction formed between the region where the electrode 10 is led out and its adjacent region, the polarity inversion channel/channel 13 caused by the high voltage applied to the upper layer wiring 7 is formed in the base diffusion region. 2 and the separation diffusion region 5 and does not occur under the electrode IO. Therefore, no leakage current occurs between the base diffusion region 2 and the isolation diffusion region 5. Further, since the impurity concentration of the PN junction formed between the base diffusion region 2 and the semiconductor layer 1 does not change due to the voltage applied to the upper layer wiring 7, no breakdown voltage deterioration occurs. The accumulation of ions 7 in the interlayer insulating film 8 caused by the voltage applied to the upper layer wiring 7 does not affect the PN junction below the electrode 10. A similar effect can be obtained from the electrode 10 derived from the emitter diffusion region 3.
It also occurs in the area of Ding.

FIG. 2 shows an embodiment in which a diffused resistor 11'i type is provided in the semiconductor layer l, and electrodes 10 led out from both ends of the diffused resistor 21 are shown.
' widely covers the region of the diffused resistor 11, is connected to the upper layer wiring 7 in the connection region 12, and is connected to other elements through the upper layer wiring 7, Fig. 3 (B). This is an example in which a lateral transistor is formed in a semiconductor layer l. An emitter region 23 of opposite conductivity type, an annular collector region 22, and a base unipolar lead-out region 24 of the same conductivity type are formed in the island-like region of the semiconductor layer l. The electrode lO/' derived from each of these regions 22°, 23.24 widely covers each region.

The electrode 10'' is connected to the annular collector region 22 at the intersection of the upper layer wiring 7.

The embodiments shown in FIGS. 2 and 3 also have the same effect as the embodiment shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain an integrated circuit with no channel leakage, high breakdown voltage, and high degree of integration.

[Brief explanation of drawings]

FIG. 1(B) is a plan view and a sectional view showing an embodiment of the present invention. FIG. 2 is a plan view showing another embodiment of the invention. FIGS. 3(5) and 3(B) are a plan view and a sectional view showing still another embodiment of the present invention. FIGS. 4(5) and 4(B) are a plan view and a sectional view showing a conventional semiconductor device. 1...Semiconductor device, 2...Base diffusion region, 3...Emitter diffusion region, 4...
Collector electrode lead-out diffusion region, 5... Separation diffusion region, 6... Buried region, 7... Upper layer wiring, 8... Interlayer insulating film, 9...・River・Oxide film, 1
0.10', 10"... Electrode% 11...
... Semiconductor substrate, 12 ... Connection region, 21
... Diffusion resistance, 22 ... Annular collector region, 23 ... Emitter region, 24 ...
・Base electrode lead-out area. , NON, -1' 21 early 3TiJ

Claims (1)

[Claims] An element region of one conductivity type formed in a semiconductor region of another conductivity type, an electrode led out from the element region on the semiconductor region and extended to almost cover the element region, and an interlayer insulating film formed on the electrode. 1. A semiconductor device comprising an upper layer wiring formed through the upper layer wiring, and wiring between element regions is performed through the upper layer wiring.