JPS6097774A - Image processor - Google Patents

Abstract

PURPOSE:To obtain satisfactory image realization by executing half-tone processing after performing variable-power processing for the picture data which are inputted. CONSTITUTION:An image signal, which is converted to an electrical signal by a CCD image sensor, is inputted to a half-tone processing circuit 32 after performing variable-power processing in a variable-power processing circuit 31. In the variable-power processing circuit 31, the image signal, which is given to a D-FF 44 by synchronizing to a clock phi2, is sampled by a clock phi3 which divides a clock phi1 based on a scale-factor specifying signal, and as a result, the variable-power processing completes. The image signal, which is subjected to the variable-power processing, is inputted to a comparator 48 of the half-tone processing circuit 32, compared with a threshold signal, and outputted as a binary signal. This threshold signal can be obtained by addressing and reading a dither matrix which is read beforhand in a dither ROM49 by count values of counters 50 and 51.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device that handles image information all at once.

[Prior art]

Conventionally, in devices that handle digital image data,
However, as the scope of application has expanded from facsimile machines to copying machines, high lI! processing has not been necessary. ] Demand for high quality images is increasing, and halftone processing for halftone printing of photographs and the like is becoming necessary.

In this type of Nakaichicho tone processing, for example, a plurality of black and white dot images are constructed as one block, as in the case of dithering, and the number of black or white dot images in this block is used to create pseudo-halftones. Most of them reproduce.

However, when digital image data is padded or thinned out, scaling processing for enlarging or reducing the K-like image has been proposed.

However, when halftone processing and scaling processing are combined in this way, image quality may deteriorate as explained below. In other words, when image data is subjected to halftone processing using the dithering method and then subjected to scaling processing, the size of a collection of pixels (pixel matrix) of a specified size for halftone reproduction changes. As a result, the white/black area per fist area changes, making it impossible to obtain a predetermined gradation and reproducing an image with accurate density. In order to prevent this, it is possible to change the dither pattern or vary the dither output according to the magnification ratio 75-' These are not preferred because they complicate the circuit configuration and increase the size.

〔the purpose〕

The present invention has been made in consideration of the above points, and an object of the present invention is to provide an image processing device that can achieve good 1ibi image reproduction even when halftone processing and variable magnification processing are combined. .

〔Example〕

Hereinafter, the present invention will be further explained in detail using the drawings.

FIG. 1 is a diagram showing the structure of a digital copying machine to which the present invention is applied. A is a reader that photoelectrically converts and reads the original to be copied, and B is a printer that records an image on the recording target based on an image signal output from the reader A. In the reader A, the original to be copied is placed face down on the original glass 3, and its placement reference is on the rear left side when viewed from the front.

The original is pressed onto the original glass by the original cover 4. The document is illuminated by the fluorescent lamp 2, and the reflected light passes through the lens 6 and the C0D.
An optical path is formed to condense light onto the plane of I. The mirror 7 and the mirror 5 are arranged to move at a relative speed of 2:1. This optical unit uses a DC Zarpo motor to apply PLL, so the constant speed path is 468mm/
sec. The resolution in this sub-scanning direction is 16 nes.
/ma. The document size that can be processed is A5 to A3, and the document placement direction is A5. B5. Each A4 size is vertically oriented, and B4° and A3 sizes are horizontally oriented.

Next, regarding the main scanning direction, during main scanning, the maximum width rl of A4 is 1297m+n depending on the above-mentioned placement direction of the original tree.

And in order to resolve this with 16pe71/B,
4752 (=297X16) as the number of bits of C0DI
Since a pit is required, this device uses a 2688-bit C
Two CD array sensors were used and driven in parallel. Therefore, 161 ines/mln, 180 gates/sec
Based on the conditions, the main scanning period (=CCD accumulation time) is T=
Sat=-1-1-v-r+ 180 X l 6 Next, referring to FIG. 1, the outline of printer B placed under reader A will be described. The image signal processed by the reader A and made into bit serial is input to the laser scanning optical system unit 25 of the printer B. This unit consists of a semiconductor laser, a collimator lens, and a rotating polyhedron.
It consists of an Fθ lens and a tilt correction optical system.

The image signal from the reader is applied to a semiconductor laser and electrically
The diverging laser light is converted into parallel light using a collimator lens, and is irradiated onto a polyhedral mirror rotating at high speed.
The laser beam is thereby scanned onto the photoreceptor 8. The rotation speed of this polyhedral mirror is 2.60 rpm.

and.

During the scanning, the number is about 400, and the effective image is between 297 and 297 in the A4 horizontal size. Therefore, the signal frequency applied to the semiconductor laser at this time is approximately 201111z (NRz).

Laser light from this unit is incident on the photoreceptor 8 via the mirror 24.

This photoreceptor 8 includes, for example, three layers including a conductive layer, a photosensitive periphery, and an insulating layer.
Consists of layers. Therefore, process components are arranged thereto which make it possible to form an image. 9 is a front static eliminator;
10 is a front static elimination lamp, 11 is a primary charger, 12 is a secondary charger, 13 is a front exposure lamp, 14 is a developer, 15 is a paper feed cassette, 16 is a paper feed roller, 17 is a paper feed guide, 1
8 is a registration roller, 19 is a transfer charger, 20 is a separation roller, 21 is a conveyance guide, 22 is a fixing device, and 23 is a tray. The speed of the photoreceptor 8 and the conveyance system is the same as the forward path of reader A (180 mm/sec. Therefore, the speed when copying by combining reader A and printer B is A4
That's 30 sheets/minute. Further, printer B uses a separating belt on the front side to separate the copy paper that is in close contact with the photosensitive drum 8, but because of this, the image corresponding to the belt is missing. If the signal is added even more than that, the toner will be developed and the separation belt will be stained by the toner, which will also stain subsequent sheets of paper. The 8th gate is designed to cut the video electrical signal for print output.

Also, if toner adheres to the leading edge of the copy paper, when it is fixed, it will wrap around the fixing roller and cause a jam, so cut the electrical signal on the league A side to prevent the toner from adhering to the leading edge of the paper. ing.

The copying machine in this example has intelligence such as image editing, but this intelligence is on the League A side and CCDI
In any case, when the signal read by the reader A is processed and output from the reader A, a signal with a constant number of bits (4752) and a constant speed is output. As for the intelligent function, o25→2.
Enlarging/reducing to any magnification within the 0x range, cropping function to extract only the specified area, movement function to move the cropped image to any location on the copy paper, There is a function to recognize the original document. In addition, there is a halftone processing function using sidither processing and an AE function depending on the key specification. Furthermore, it has a composite function that combines these individual intelligent functions.

FIG. 2 is a block diagram of a circuit that performs scaling and halftone processing of the above-mentioned intelligent processor (IK&N) on an image signal obtained by reading a document with reader A. The image signal serially output from the CCDI of the reader A is input to the scaling processing circuit 31, and is subjected to scaling processing into an image signal according to a set magnification.

The variable magnification process here refers to the variable magnification process in the main scanning direction of the CCDI, in which the image signal input for each pixel is sampled at a frequency of A×α (α>1) in synchronization with the frequency A. By inflating the data, the expansion is α times, A×
By thinning out the image signal by sampling at a frequency of β (0≦β<1), the image signal is reduced by a factor of β. Incidentally, the magnification in the sub-scanning direction is changed by changing the sub-scanning speed in the reader A according to the magnification ratio.

The image signal subjected to the scaling process by the scaling processing circuit 31 is input to the halftone processing circuit 32 . The input image signal is data of a predetermined bit having halftone information per pixel (hereinafter referred to as a multi-value signal), and is binarized and multi-valued by the halftone processing circuit 1 using, for example, a dither method. A pseudo-halftone conversion process using pixels is performed to obtain a binary signal output.

3 to 5 show the states of image signals in the second illustrated circuit configuration. FIG. 3 shows a pixel matrix on a document of an image signal input from the CCDI to the scaling processing circuit 31.

In this embodiment, it is assumed that the halftone processing circuit 32 performs 17th floor true halftone reproduction using a 4×4 teaser matrix. The numbers 1 to 32 in the matrix of FIG. 3 are the pixel numbers of each pixel in the pixel matrix.

This corresponds to the numerical values in the matrix shown in FIGS. 4 and 5.

During reduction by 0.5 times, pixels in the main scanning direction are extracted (thinned) at a ratio of one pixel out of every two pixels in the magnification processing circuit 31. On the other hand, when enlarging by %2, the magnification processing circuit 31 inflates the rII11 element in the main scanning direction by a factor of 2. and,
The image thinned out or padded in this way (4×47 for dither processing in the halftone processing circuit 32 in No. 4)
Configure the IJ box as shown in Figures 4 and 5, respectively, and
Dither processing is performed using an X4 dither matrix. Therefore,
The scaled and halftone-processed binary E signal outputted from the halftone processing circuit 32 to a subsequent processing unit such as a printer has a good appearance in which the size of the dither matrix has not changed.

As described above, according to the circuit configuration shown in the second diagram, when scaling processing is performed after halftone processing, the size of the dither matrix changes, and the white/black area per unit area changes greatly. It is possible to prevent the inconvenience of not being able to obtain a predetermined gradation.

FIG. 6 shows a detailed configuration example of the second illustrated circuit.

Reference numerals 31 and 32 are a scaling processing circuit and a halftone processing circuit shown in the second diagram, respectively.

In the scaling processing circuit 31, an oscillation circuit 41 generates a basic operation clock φ1 when performing a scaling operation. The clock φ1 is frequency-divided at a constant rate by a frequency dividing circuit 42, and the divided output is used as an operating clock φ2 of a pre-stage circuit (not shown) that sends out image data. The pre-stage circuit here is, for example, an A/D converter that A/D converts the analog output of a line image sensor such as C0DI. This pre-stage circuit outputs an image signal for each pixel in synchronization with the clock φ2, and sends this to the D flip-flop 44.
Adjust the timing. The output signal D1 of the D flip-flop 440 is input to the next-stage D flip-flop 45, sampled at the clock φ3, and outputted as an output signal D2 to complete the scaling process.

The clock φ3 is a clock signal obtained by frequency-dividing the clock φ1 by the programmable frequency dividing circuit 43 according to the multiplying factor designation signal. For example, the programmable frequency dividing circuit 3 includes:
TI's 5N7497°5N74167 can be used. The magnification designation signal for controlling the frequency division ratio may be fixed, for example, with a switch, or may be made variable using a microcomputer or the like.

Further, the D flip-flops 44 and 45 are 5, for example, TI
For example, the frequency dividing circuit 42 is 5N74LS74A from TI
A counter such as the 5N74L8161 manufactured by Co., Ltd. may be used, or the same as the programmable frequency dividing circuit 43 may be used with a fixed frequency division ratio. In this way, in the variable magnification processing circuit 31, (r
Yo picture 1't3: (Pa's human powered clock frequency (6
An oscillator that generates a clock frequency φ1 greater than 2 is prepared, and a clock φ3 obtained by dividing the oscillator according to the magnification ratio is used to operate the magnification, so that it is possible to expand the scope of use and to make it as small as 11.

The output signal D2 of the D flip-flop 45 is input to the comparison circuit 48 of the halftone processing circuit 32.

The threshold value M' D 5 from the D flip-flop 47 is input to the comparison circuit 48, and by comparing this threshold signal D5 and the output signal D2, a binary signal D3 is output. Threshold signal D51''l: The dither matrix written in advance in the dither ROM 49 is sent to the sub-scanning counter 50.
and the count value of the main scanning counter 51,
The D flip 70
It is outputted from the knob 47 in synchronization with the output of the D flip-flop 47.

The sub-scanning counter 50 counts the main-scanning interval signals input from the previous stage circuit. The main scanning section signal is output for each scan of C0DI, and therefore the sub-scanning counter 5
0 counts the number of sub-scanning lines in the reader AIC and outputs the count value. Further, the main scanning counter 51 counts the clock φ3 outputted from the programmable frequency dividing circuit 43 of the scaling processing circuit 31, and outputs the count value.

The D flip-flop 47 also includes a variable magnification processing circuit 31.
The clock φ3 from the programmable frequency dividing circuit 43 is inputted and driven. As mentioned above, since the D7 lip 70 tube 45 of the scaling processing circuit 31 is also driven by the clock φ3 from the programmable frequency dividing circuit 43, the two inputs (D2, D5) to the comparison circuit 48 are synchronized. In addition, the sub-scanning counters 50 and 51 are TI's 5N74LS191.
As a dither ROM49, it is 2716 from inte 1 company.
However, TI's 5N74LS85 could be used as the comparison circuit 48. As the D flip-flop 47, the aforementioned 5N74LS74A manufactured by TI is used.

The binary signal D3 outputted from the comparator circuit 48 is outputted to a double buffer (not shown) at the subsequent stage in synchronization with the clock φ3 at the D free lag flop 46. As mentioned above, the synchronization of the clock φ3 is not constant due to the scaling specification, so this double buffer is used to store the clock and then output it to the printer B at a predetermined speed.

Next, a more detailed explanation will be given using the timing chart shown in FIG.

In FIG. 7, each signal D1 to D5'', φ
1 to φ3 are shown. Here, clock φ1
=2X clock φ2. Clock φ1≧Clock φ3≧0
It is assumed that there is a frequency relationship of , and FIG. 7 illustrates the timing when clock φ3=0.75×clock φ1.

The image signals are outputted in the order of the numbers in the figure in synchronization with the clock φ2 from the frequency dividing circuit 42. The timing is adjusted by the D flip-flop 44 and outputted as an output signal D1.

In the programmable frequency dividing circuit 43, a waveform like the illustrated clock φ3 is obtained by setting the frequency division rate control line so as to divide the clock φ1 at a frequency division rate of 0.75.

When the output signal D1 is sampled by the D clip flop 45 using the clock φ3, the output signal D2 is obtained. By regarding one cycle of clock φ3 as one image data, the image signal 1.4.7... is sampled twice, so the output signal D2 is the input image signal D.
The amount of data is 1.5 times that of 1.1 in the main scanning direction.
This means that the area has been expanded five times.

Further, when reducing the size, the frequency of the clock φ3<the frequency of the clock φ2 may be set, and when the magnification is equal to 1, the frequency of the clock φ3=the frequency of the clock φ2 may be used.

On the other hand, in synchronization with the output signal D2 subjected to the scaling process as described above, the D flip-flop 4
7, a threshold signal D5 for which the binarization process is not completed is output. That is, the threshold signal D5 is sequentially outputted so as to correspond to each data of the output signal D2. The comparison circuit 48 compares the output signal D2 and the threshold signal D5 and outputs a binary signal D3 to the D flip-flop 46 at the timing shown in FIG.

Clock φ3 is also input to the D7 lip 70 knob 46,
As shown in FIG. 7, the binary number D4 is outputted to the double buffer at the subsequent stage.

In this embodiment, a digital copying machine has been described, but the present invention can be similarly applied to other image processing devices such as a facsimile, an image file, and a microfilm league.

〔effect〕

As explained above, according to the present invention, even if halftone processing and scaling processing are performed in combination on input image data, image processing can be performed without adversely affecting halftone processing and without deteriorating image quality. It is.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the structure of a digital copying machine to which the present invention is applied, FIG. 2 is a block diagram showing the basic configuration of an image processing circuit, and FIGS. 3 to 5 are diagrams showing the state of the 1ilji image signal.
Fig. 6 is a diagram showing the detailed circuit configuration of Fig. 2, and Fig. 7 is a diagram showing the state of signals in each part of Fig. 6, where A is the reader and B
1 is a printer, 1 is a CCD, 31 is a scaling processing circuit, 32 is a halftone processing circuit, 41 is an oscillation circuit, 43 is a programmable frequency dividing circuit, 48 is a comparison circuit, and 49 is a dither ROM. Applicant Canon Co., Ltd.

Claims (1)

[Claims] 1. An image processing apparatus comprising: after performing scaling processing on an input image signal, performing halftone processing for pseudo-reproducing halftones on the scaled image signal.