JPS6097776A - Picture processor - Google Patents

Abstract

PURPOSE:To achieve optional magnification or reduction of a picture by simple constitution by sampling input picture data by the output of the divided frequency which is larger than the input frequency of picture data, and by increasing or decreasing the number of the picture data. CONSTITUTION:An analoque signal from a line image sensor such as a CCD is added to a D-FF44 of a variable power processor 31 by synchronizing with a clock phi2 after executing A/D conversion. An output signal D1 of this D-FF44 is inputted to the next stage D-FF45, an output signal D2 is hereby outputted by sampling by a clock phi3, and the variable-power processing completes. Here, the clock phi3 is a clock signal which is obtained by dividing a clock phi1 in accordance with a magnification signal by a programmable frequency dividing circuit 43, and the dividing ratio is set voluntarily. Input picture data are sampled by the clock which is divided in accordance with this variable power ratio, and therefore, the voluntary magnification and reduction can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device that electrically handles image information.

[Prior art]

For example, when reading a document image photoelectrically and recording the image based on the obtained image signal, the image can be enlarged or reduced optically and then read. In this case, there is a method of changing the recording pixel density.

However, these methods are not very preferable due to problems such as increased size and complexity of the device.

〔the purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to provide an image processing device that can achieve arbitrary enlargement or reduction of an image with a simple configuration without increasing the size or complexity of the device. With the goal.

〔Example〕

Hereinafter, the present invention will be explained in more detail using the drawings.

FIG. 1 is a diagram showing the structure of a digital copying machine to which the present invention is applied. A is a printer that photoelectrically converts and reads a document to be copied, and B is a printer that records an image on a recording material based on an image signal output from the reader A. In the reader A, the original to be copied is placed face down on the original glass 3, and its placement reference is on the rear left side when viewed from the front.

The original is pressed onto the original glass by the original cover 4. The document is illuminated by a fluorescent lamp 2, and an optical path is formed such that the reflected light is focused on the surface of the CCDI via a mirror 5.7 and a lens 6. The mirror 7 and the mirror 5 are arranged to move at a relative speed of 2:1. This optical unit uses a DC servo motor to apply PLL and has a constant return speed of 468 tnm/
See. The resolution in this sub-scanning direction is 16/1n
es/my. The size of documents that can be processed is A5
~A3 size, and the document placement direction is A5. B5.
Each A4 size is placed vertically, and the B4°A3 size is placed horizontally.

Next, regarding the main scanning direction, during main scanning, the maximum horizontal width of A4 paper is 297 my depending on the orientation in which the document is placed. And in order to resolve this at 16 pel/mm, C
Since 4752 (=297x16) bits are required as the number of bits for 0DI, this device uses 2688 bits of CC.
Two D-array sensors were used and driven in parallel.

Therefore, 16 /1nes/mfn, 180y
From the +i/Scc condition, the feed speed is f = father = , 26
28 T 347.2 pse. -7,7419 ktlz.

Next, the appearance of printer B placed under reader A in FIG. 1 will be described. The image signal processed by the reader A and made bit-serial is input to the laser scanning optical system unit 25 of the printer B. This unit consists of a semiconductor laser, a collimator lens, and a rotating polygon mirror.

It consists of an Fθ lens and a tilt correction optical system.

The image signal from the reader is applied to a semiconductor laser and electrically
The diverging laser beam is converted into parallel light by a collimator lens, and is irradiated onto the polyhedron Mi 2- which rotates at high speed, thereby scanning the photoreceptor 8 with the laser beam. The rotation speed of this polyhedral mirror is 2.60 Orpm. Its running width is about 400tw, and the effective image is 297 dragons of A4 horizontal size. Therefore, the signal frequency applied to the semiconductor laser at this time is approximately 20 kHz (NR
z). The laser beam from this unit is transmitted to the mirror 24.
The light is incident on the photoreceptor 8 via the.

As an example, this photoreceptor 8 has three parts: NM = photosensitive layer - insulating layer.
Consists of rm. Therefore, process components are arranged thereto which make it possible to form an image. 9 is a pre-static eliminator, 10 is a pre-static eliminator 2 pump, 11 is a primary charger, 12 is a secondary charger, 13 is a front exposure lamp, 14 is a developer, 15
16 is a paper feed cassette, 16 is a paper feed roller, 17 is a paper feed guide, 18 is a registration roller, 19 is a transfer charger, 20 is a separation roller, 21 is a conveyance guide, 22 is a fixing device, and 23 is a tray. The speed of the photoreceptor 8 and the transport system is 180 vm/Sec, the same as the forward path of the reader A. Therefore,
Reader A and printer B are pressed to copy, and the A4 size is 3 (1 sheet/minute).Also, printer B is placed on the front side to separate the copy paper that is in close contact with the photosensitive drum 8. A separation belt is used, but as a result, the image corresponding to that belt is missing.If a signal is placed on that peak, it will be developed, and the toner will stain the shunt belt, which will cause problems in subsequent images. Since this would result in staining the paper, the League A side had in advance cut off the video electrical signal of the printout for this separation belt.
If toner adheres to the leading edge of the copy paper, it will be fixed when it is fixed.
The electric signal is also cut off on the reader A side to prevent toner from adhering to only the two leading edges of the paper, as this may cause a jam when the toner wraps around the fixing roller.

The copying device in this example has intelligence such as image editing, but this intelligence is done on the League A side by processing the signal read by CCDI, and at the stage of output from reader A, no Also, a signal at a constant speed is output with a constant number of bits (4752). As for the intelligence function, 0.5 → 2.0
Enlarging/reducing to any magnification within the magnification range, cropping function to extract only the specified area, movement function to move the cropped image to any location on the copy paper, placed on the document table It has functions such as recognizing manuscripts. In addition, there is a halftone processing function using dither processing and an AE function depending on the key specification. Furthermore, it has a composite function that combines several of these intelligent functions.

FIG. 2 is a block diagram of a circuit that performs magnification and halftone processing of the aforementioned intelligent functions on an image signal obtained by reading a document with reader A. The image signal serially output from the CCDI of the reader A is input to the scaling processing circuit 31, and is subjected to scaling processing into an image signal according to a set magnification.

Here, magnification processing refers to magnification processing in the main scanning direction of CCDI, in which the image signal is input for each pixel in synchronization with frequency A, and is sampled at a frequency of A × α (α>1). A
The image signal is thinned out by sampling at a frequency of ×β (O≦β<1), thereby performing reduction by a factor of β. Incidentally, the magnification in the sub-scanning direction is changed by changing the sub-scanning speed in the reader A according to the magnification ratio.

The image signal subjected to the scaling process by the scaling processing circuit 31 is input to the halftone processing circuit 32 . The signal is predetermined pit data having halftone information per pixel (hereinafter referred to as a multi-value signal), and the halftone processing circuit 1 uses, for example, a dither method to binarize and use multiple pixels. Performs halftone conversion processing to obtain a binary signal output.

3 to 5 show the states of image signals in the second illustrated circuit configuration. FIG. 3 shows a pixel matrix on a document of an image signal input from the CCDI to the scaling processing circuit 31.

In this embodiment, it is assumed that the halftone processing circuit 32 uses a 4.times.4 dither matrix to reproduce halftones of 17 degrees. The numbers 1 to 32 in the matrix of FIG. 3 are the pixel numbers of each pixel in the pixel matrix, and correspond to the numbers in the matrix shown in FIGS. 4 and 5.

During reduction by 0.5 times, pixels in the main scanning direction are extracted (thinned) at a ratio of one pixel out of every two pixels in the magnification processing circuit 31. On the other hand, when the image is enlarged by 2 times, the pixels in the main scanning direction are inflated by 2 times by the variable magnification processing circuit 31. Then, the halftone processing circuit 32 uses the thinned out or padded image signal in this way.
4×4 matrices for dithering are constructed as shown in FIGS. 4 and 5, respectively, and dithering is performed using the 4×4 dithering matrix. Therefore, mid-tone jukujM! The scaled and halftone-processed binary code outputted from the circuit 32 to a subsequent processing unit such as a printer is a good one in which the size of the dither matrix does not change. In this way, according to the circuit configuration shown in the second diagram, when scaling processing is performed after halftone processing, the size of the dither matrix changes, and the white/black area per unit area changes to 1J thick, resulting in a predetermined This makes it possible to prevent the inconvenience of not being able to obtain gradation.

FIG. 6 shows a detailed configuration example of the second illustrated circuit.

Reference numerals 31 and 32 are a scaling processing circuit and a halftone processing circuit shown in the second figure, respectively.

In the scaling processing circuit 31, the oscillation circuit 41 &:l: generates a basic operation clock 931 when performing a scaling operation. The clock signal 1 is frequency-divided by a frequency divider circuit 420 at a constant rate, and the divided output is used as a clock signal 2 of a pre-stage circuit (not shown) for transmitting image data. The pre-stage circuit referred to here is an A/D converter that converts an analog output of a line image sensor such as an EVA or a CCDI into an A/D converter. This pre-stage circuit outputs an image No. 45 for each pixel in synchronization with the clock 2, and the timing is adjusted by a D slip flop 44. The output signal 1) t of the D flip-flop 44 is input to the next-stage D flip-flop 45, sampled by the clock 3, and output signal 1) 2. The scaling process is completed.

The clock 963 is a clock signal obtained by frequency-dividing the clock 961 by the programmable frequency dividing circuit 43 according to the multiplying factor designation signal. As the programmable frequency dividing circuit 3, for example, 5N7j97°5N74167 manufactured by TI Corporation can be used. The magnification designation signal for controlling the frequency division ratio may be fixed, for example, by a switch, or may be changed in angle using a microcomputer or the like. In addition, the D flip-flop 44.45 is, for example, TI's 5N74L.
S74A, the frequency dividing circuit 42 is, for example, TI's 5N74LS.
A counter such as 161 may be used, or the same circuit as the programmable frequency dividing circuit 43 may be used with a fixed frequency division ratio.

In this way, the scaling processing circuit 31 prepares an oscillator that generates a black frequency 〆, a black frequency 〆, which is greater than 2, for inputting an image signal, and divides the oscillator according to the scaling factor. Since the clock 963 is used to perform the scaling operation, arbitrary enlargement and reduction can be performed.

The output signal D2 of the D-clip flop 45 is the intermediate 14I
The signal is input to the comparison circuit 48 of the 4-processing 1til path 32. The threshold signal D5 from the D flip-flop 47 is input to the comparator circuit 48, and this value sign D5 and the output signal D
2, a binary code D3 is output. The threshold signal D5 addresses the dither matrix stored in the dither ROM 49 in advance using the count values of the sub-scan counter 5o and the main scan counter 51, and
9 is read out, and further, D flip-flop, D is read out at p47.
It is output in synchronization with the output of the flip 70 tube 47.

The sub-scanning counter 5o counts the main-scanning section signals input from the previous stage circuit. The main scanning section signal is 1 of C0DI.
It is output for each scan, so the sub-scanning counter 5
o counts the number of sub-scanning lines in reader A.
r: Yes, it outputs the count value. Also,
The main scanning counter 51 counts the clock y3 outputted from the programmable frequency dividing circuit 43 of the variable magnification processing circuit 31, and outputs the count 1.

The D flip-flop 47 also includes a variable magnification processing circuit 31.
The clock 52f3 from the programmable frequency dividing circuit 43 of
is input and driven. As mentioned above, D of the variable magnification processing circuit 31
Since the flip-flop 45 is also driven by the clock signal 3 from the programmable frequency dividing circuit 43, two inputs D2. D5 becomes synchronized. The sub-scanning counters 50 and 51 can be 5N74LS191 from TI, the dither ROM 49 can be 2716 from 1nte1, the comparison circuit 48 can be 5N74LS85 from TI, and the D flip-flop 47 can be the one described above. TI's 5N74. LS74A is used.

The binarized signal D3 output from the comparison circuit 48 is outputted to a subsequent double buffer (not shown) in synchronization with the clock signal 3 by a D flip-flop 46. As mentioned above, this double buffer does not have a constant cycle of the clock 3 due to the scaling specification, so it stores -J11, and then outputs it at a predetermined speed.7. f knee N) if f (I H4'Ch enter' - then the 7th
A more detailed explanation will be given using the timing chart shown in the figure.

In Fig. 7, each signal on Fig. 6 l) 1 to D5°96
1 to 3 are shown. Let's do it here, clock 9.
61=2x black, ri02. Clockda1≧Clock3
It is assumed that there is a relationship of ≧00 frequency, and FIG. 7 illustrates the timing when clock 9132075×clock O1.

The image signals are outputted in the order of numbers in the figure in synchronization with the clock signal 2 from the frequency dividing circuit 42. This signal is timed by a D flip-flop 44 and output as an output signal D1.

In the programmable frequency divider circuit 43, a waveform like the illustrated clockfish 3 can be obtained by setting the frequency division rate control line to 4>f, which divides the clock 〆1 by a frequency division rate of 0.75.

When the output 'hj number 1] 1 is sampled by the flip-flop 45 using the clock 963, the output signal D is obtained.
It will look like 2. One period of the clock 963 is sampled twice with 11 metaphysical data J-h, ;'1 ;">If'"I) crystal white 4i IW '-3-/7N1, 4.7... Therefore, the output signal D2 has 1.5 times the data size of the input image signal D1, which means that the data has been expanded 1.5 times in the main scanning direction.

Also, when reducing the size, it is sufficient to set the frequency of the clock 913 (clock 913) to 20, and when using the same magnification, the clock 963 = clock 20.
The frequency should be set to .

On the other hand, a threshold signal D5 for the 211α conversion process is output from the dither ROM 49 via the D flip-flop 47 in synchronization with the output signal '%D2 which has been subjected to the scaling process as described above. That is, the threshold signal D5 is sequentially output so as to correspond to each data of the output (r number D2).The comparator circuit 48 compares the output signal I) 2 and the value mark D5 to obtain a binary value of 18. No.D3
is output to the D flip-flop 46 at the timing shown in FIG. The clock y3 is also input to the D flip-flop 46, and as a result, the binary signal D4 is output to the double buffer at the subsequent stage as shown in FIG. It is similarly applicable to other image processing devices such as facsimiles, U+JI image files, microfilm leagues, etc.

〔effect〕

As explained above, according to the present invention, in response to the request for expansion and reduction of both ends, simple 1. [This can be dealt with through configuration, and even more so in the first year of middle school. ] This enables good image reproduction even with a combination of X processing and enlargement processing. Furthermore, if the frequency of the oscillation output is set to 100%, it becomes possible to change the magnification at a finer rate.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the structure of a digital copying machine to which the present invention is applied, and FIG. 2 is a block diagram showing the basic configuration of an image processing circuit.
j1, 31'), 1 to 51"'l are diagrams showing the state of the image signal, FIG. 6 is a diagram showing the detailed circuit structure of FIG. 2,
Figure 7 is a 7I diagram showing the state of the signals at each part of the 6th.
A is a reader, 13 is a printer, °1 is a CCU, 31 is a scaling circuit, 32 is a halftone processing circuit, 41 is an oscillation circuit, 43 is a programmable frequency dividing circuit, 48 is a comparison circuit, and 49 is a dither ROM. be. Canon Co., Ltd.

Claims (1)

[Claims] (1) The number of image data can be increased or decreased by sampling the input image data using a frequency-divided output obtained by dividing the oscillation output with a frequency higher than the input frequency of the image data by an arbitrary frequency division ratio. Characteristic image processing device. (2. An image processing apparatus according to claim (1), characterized in that halftone processing is performed on image data using a threshold signal output in synchronization with the frequency-divided output.