JP2901062B2 - Image forming device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more specifically, an original image is two-dimensionally, one of which is electrically connected using a one-dimensional array-shaped optical sensor, and is substantially orthogonal thereto. The direction is applied to a digital color copier or the like which performs resolution scanning by physical movement to obtain original image data, performs signal processing on the image data, sends the processed signal to image forming means, and reproduces an image. The present invention relates to an image forming apparatus that can be used.

(Prior art)

Such an image forming apparatus has a so-called frame memory, and it can be easily analogized that a copy image can be obtained by operating data on the memory. However, such a frame memory requires a large capacity,
It has the disadvantage of being very expensive.

〔Purpose〕

The present invention has been made in view of such a point, and has as its object to easily swap document images.

〔Constitution〕

To achieve the above object, a first means is an image forming apparatus which scans an original by scanning with a scanner and reads the image data on a recording sheet, and stores the read image data for one line. Setting means for setting an initial value corresponding to a position to be swapped by setting from the operation unit; and a first means for giving a write address to the storage means by counting a clock synchronized with the image data from 0. An address counter; a second address counter that counts a clock synchronized with the image data from an initial value set in the setting unit to provide a read address to the storage unit; When a predetermined value that is a number matches the count value of the second address counter, The count value of the second address counter and a comparator means for 0, is characterized in that swap in the image data of one line.

Further, the second means is characterized in that the setting means in the first means can be set so as to change the initial value for each line.

Hereinafter, a specific description will be given based on an embodiment of the present invention.

FIG. 1 is a block diagram of a digital color copying machine for explaining one embodiment of the present invention. 100 is a scanner unit (hereinafter referred to as SC), 200 is an image processor (hereinafter I)
P), 400 is a memory unit (hereinafter referred to as MU), 600 is a printer unit (hereinafter referred to as PU), 7
00 is a system controller (hereinafter referred to as SCON), 75
0 is a console unit (hereinafter referred to as CU), 900 is a digitizer tablet (hereinafter referred to as DG), 950 is a sorter unit (hereinafter referred to as ST), and 980 is an ADF unit (hereinafter referred to as ST).
AD).

2 (a) is a system block diagram of the digital color copying machine shown in FIG. 1, FIG. 2 (b) is a drawing connection diagram, and FIGS. 2 (c) to (f) are partial views. . The same reference numerals as those in FIG. 1 correspond to the same parts.

1 and 2, C indicates cyan, M indicates magenta, Y indicates yellow, R indicates red, G indicates green, B indicates blue, and BK indicates black.

In FIG. 2, the logic circuit is treated as positive logic, and a high voltage is High or 1 and a low voltage is Low or 0.
Described as As shown in FIG. 2 (g), A is a NAND gate, B is a NOR gate, C is an AND gate, D is an OR gate, E is a simple gate,
Then, F is the exclusive OR XOR.

First, among the configurations of the present invention, the SC100, IP200, MU400, PR600, SCON700, and CU750, which are the main parts,
The outline of those operations will be described.

(1) System Controller (SCON) 700 This is a computer that performs overall control of the digital color copying machine system of the present invention and is a stored program type computer.

 For example, each element can be configured as follows.

CPU704 ··· Intel 8086 RAM712 ··· Nidec Corporation µPD43256 × 4 (128KBYT
E) ROM (PROM) 713 ··· Intel27512 × 10 (640KBYTE) Interrupt controller 710 ··· Intel8259 × 3 cascade connection (22 inputs) Timer / counter 711 ··· Intel8254 × 3 (9 timers) / Counter) Printer interface 703 ···· Intel8255 (MODE
2) (Parallel type) Scanner interface 709 ··· Ditto console interface 708 ··· Intel8251 (serial communication type I / O) Image processor sign toughness 701 ··· Intel82
55 (MODE0) x 3 Memory unit interface 702 ··· Intel8255 Digitizer tablet interface 707 ··· Intel
8251 (Serial communication type I / O) Sorter interface 706 ··· Same as above ADF interface 705 ··· Same as above Other components such as a clock generator and a control signal decoder are omitted, but are omitted.

(1-1) SC100 interface Physically, there are 8-bit bidirectional data lines and several control lines.

The instruction for SC is called SC command, At the time of data reception and data transmission completion, a signal is automatically input to the interrupt controller 710, and an interrupt service routine is automatically executed.

(1-2) PR600 interface Physically the same as SCI / F.

PR commands include: In addition, this signal pulse may not be generated by PR, but may be generated by, for example, SCON or IP, and supplied to another system.

This signal pulse is output from the interrupt controller 71.
It is input to 0 and is processed in real time.

(1-3) Interface to IP200 This interface is for output only.

γ _{0 to} γ ₂ ····· Set the γ characteristics (density characteristics) of the copy for the original (group 8) MIRROR1 ··· Instruction to create a mirror image copy in the main scanning direction SWAP1 ··· In the main scanning direction Instruction to create a replacement copy of the image LEFT / ▲ ▼ ・ ・ ・ ・ Direction of creation of moving image copy in the main scanning direction INVERSE ・ ・ ・ ・ Instruction to create density inversion copy OUT / ▲ ▼ ・ ・ ・ ・ Area processing (blanking, partial color transform, partially quality processing selection) inside or outside of the instruction a ₅ to a ₉ · · · · region processing, the upper address of the image movement RAM 5bit and address comparators data D ₀ in ~ D ₁₁・ ・ ・ ・ Data of RAM for area processing and image movement (12bi
t) ▲ ▼ ・ ・ ・ ・ Region processing, chip select of image movement RAM (enable) CLR ・ ・ ・ ・ Region processing, clearing of lower 6 bits address counter of image movement RAM, and scaling RAM address counter clear pulse ▲▲ · · · · the two write pulses ALL · · · · domain processing is not performed instruction RAM (when applied to the entire surface) CH _GCO ~ ₅ ···· color conversion contents indicated UCR · · ·・ Instruction on whether to perform UCR (UNDER-COLOR-REMOVAL: under color removal) MAX ・ ・ ・ ・ The highest density signal among C, M, and Y signals that have undergone complementary color generation and color correction Is extracted and sent to all C, M, Y, and BK signal lines (to change the size of the next step of IP200 described later). ) ZD ₀ ~ ₁₁ data .... zooming _{RAM (12bit) CKIND 0 ~ 2} ···· image quality processing, 8 kinds of selection CGATE ···· shea Indication of whether to send data MGATE ... Instruction of sending magenta YGATE ... Instruction of sending yellow BKGATE ... Instruction of sending black (1- 4) Interface with MU400 This interface is for output only.

SYMMETRY2 ··· Used when making a target copy in the sub-scanning direction.

MIRROR2 ··· Used when making a mirror image copy in the sub-scanning direction.

SWAP2: Used when making a replacement copy in the sub-scanning direction.

COMPSD ··· Serial data of input data registers of three sets of 24-bit comparators inside the MU DSHIFT ··· Shift pulse of the above register (shift register) MMODE1 ··· MU is a normal FIFO (first in, first out) ) Instruction to operate in mode MMODE2 .... Instruction to operate MU in write mode MMODE3 .... Instruction to operate MU in read mode MSTART .... Used for resetting.

VDENA ··· Instructs whether the address counter of the MU memory can be counted up (1-5) Interface to CU750 <Input> Imports key-in information from various keyboards, CU
When receiving data from the 750, the serial communication type I / O port
Since 708 generates an interrupt signal to 710, it is possible to quickly cope with a change in information of the CU 750.

<Output> Outputs data to be displayed on the console.

(1-6) Interface with DG900 <Input> Import XY coordinate data.

<Output> Sends buzzer and display lamp data.

The I / O port 707 is of an asynchronous serial communication type, and generates an interrupt signal to the signal 710 at the time of reception and transmission.

(2) Scanner Unit (SC) 100 First, referring to FIG. 1, a document 1 is placed on a platen (contact glass) 2 and fluorescent lamps 3 ₁ , 3 ₂ for illuminating the document.
1st mirror which is illuminated by and whose reflected light can move
4 _1, is reflected by the second mirror 4, _second and third mirror 4 _3, through the imaging lens 5 enters the dichroic prism 6, wherein three wavelengths of light,-intensity (R), green (G) and It is split into blue (B). The split light enters the CCDs 7r, 7g, and 7b, which are solid-state imaging devices, respectively. That is, the red light is incident on the CCD 7r, the green light is incident on the CCD 7g, and the blue light is incident on the CCD 7b.

Fluorescent lamp 3 _1, 3 ₂ and the first mirror 4 ₁ is mounted on the first carriage 8, the second mirror 4 ₂ and the third mirror 4 ₃ is mounted on the second carriage 9, a second carriage 9 is first carriage 8 of
By moving at half speed, the optical path length from the document 1 to the CCD is kept constant, and the first and second carriages are scanned from right to left when reading the original image. Carriage drive pulley 11 fixed to the shaft of carriage drive motor 10
The first carriage 8 is connected to a carriage driving wire 12 wound around the vehicle, and the wire 12 is wound around a moving pulley (not shown) on the second carriage 9. Thus, the first carriage 8 and the second carriage move forward (original image reading scan) and return (return or forward direction original image reading scan) by forward and reverse rotation of the motor 10, and the second carriage 9 moves to the first carriage.
It moves at half the speed of the carriage 8.

When the first carriage 8 is at the home position shown in FIG. 1, the first carriage 8 is detected by a home position sensor 39 which is a reflection type photo sensor. When the first carriage 8 is driven to the right in the exposure scan and deviates from the home position, the sensor 39 does not receive light (carriage is not detected). When the first carriage 8 returns to the home position by return, the sensor 39 returns to the home position. Light reception (carriage detection) occurs, and the carriage 8 is stopped when the state changes from non-light reception to light reception.

Referring now to FIG. 2, the outputs of the CCDs 7r, 7g, and 7b are converted to 8-bit digital values by the A / D converters 102r, 102g, and 102b, that is, 256-level density signals.
It will be sent as a signal. Its value is 255 in white,
0 for black.

The control of the SC 100 is performed by the scanner controller 101.

The scanner controller 101 includes a CCD driver, a motor driver,
It is composed of those including various sensor input ports and SCON700I / F.

(3) Image processor (IP) 200 γ-correction processing (γ-Compensation) In accordance with the characteristics of SC reading density gradation and PR print density gradation, make the gradation of the original and copy linear. Is performed.

γ conversion processing (γ-Change) Processing for creating a copy having a γ characteristic different from that of the original, for example, a copy in which highlights are emphasized, a high contrast copy, or the like is performed.

Is one of the eight special γ characteristics, including the 3 bit signal from SCON, and the next block
R, G and B are output in 8 bits each.

Block 202 (see FIG. 3 for details) Mirroring 1 (MIRROR1) When the MIRROR1 signal from SCON is high, the arrangement of pixel data in the main scanning direction is inverted and output.

Swap 1 (SWAP1) The SWAP1 signal from SCON is high and the RAM shown in FIG.
224 loaded with appropriate data and LSY while scanning
When A ₆ to A ₁₁ in synchronization with the count value of the NC is given from SCON, replacement of the main scanning direction of the image.

Shift Part 1 RAM 224 to the appropriate data are loaded in advance, and when A ₆ to A ₁₁ in synchronization with the count value of LSYNC during scanning is given from the SCON, image positions of the same amount or a sub-scanning direction on the entire surface Are moved in different amounts. Movement direction is from SCON
Determined by LEFT / ▲ ▼ signal High / Low.

Appropriate data SWITCH output RAM224 are preloaded, and when A ₆ to A ₁₁ in synchronization with the count value of LSYNC during scanning is given from the SCON, block 202 High a SWITCH signal, Low
Output alternately.

This output is output to blocks 207C, M, Y, and BK for blanking part of the image (trimming processing), block 206 for partially changing the image quality processing, and partial color conversion. Is output to block 203.

Inverse (inversion) When the INVERSE signal from SCON is high, each bit of R, G, B 8 bits is inverted and output. The copy is therefore a negative image.

Next, a detailed description of the block 202 will be described with reference to FIGS.
This will be described with reference to FIGS. 5 and 6.

FIG. 3 is a circuit diagram of the image processor IP,
(A) is a drawing combination diagram, and (b) and (c) are partial views.

Two sets of RAM for each color (263r, g, b and 266r,
g, b). These RAMs are used as toggle buffer memories. When one set is taking in image data (writing to memory: memory write), one set is exposing data (reading memory: reading memory). . Switching between read and write is performed by JKFF every 1 LSYNC.
This is done by reversing 262.

FIG. 6 is an operation timing chart of the image processor IP. Assuming that the Q output of 262 goes high in the first LSYNC, one input of the OR gate 234 goes low, and VCLK (pulse generated by FIG. This pulse is also LSYN because there are 4752 pixels
4752 are generated between C and the next LSYNC. When the rising portion of the pulse (at the middle position of one pixel data) rises, a rising pulse is applied to the ▲ ▼ terminals of RAM 266r, RAM 266g and RAM 266, and the pixel data is written. The address at this time is the memory write counter (WR-
(CTR) 252.

Since the VCLK is also input to the CLK of the counter 252, the image data is sequentially written in the higher address direction.

On the other hand, in the RAMs 263r, 263g, and 263b, since one input of the OR gate 233 is High, the symbol ▼ is not active. Instead, if one of the three inputs of the NAND gate 264 connected to the output of the OR gate 259 is high, the input becomes low and the output is enabled, that is, the memory read is performed. Note that MM3 (248) is a retriggerable monomultivibrator whose output pulse width is set slightly longer than the cycle of VCLK. Therefore, as shown in FIG. 6, high output is continuously performed during generation of VCLK. .

Also, at this time, since the inputs of the bus drivers 268r, 268g, and 268b are high, the output is in a high impedance state,
The A input side is selected for the multiplexers 269r, g, and b.
The data is output to the next block 203 via R gates 230 ₀ r, g, b to 230 ₇ r, g, b.

The XOR gate is for inverting data when the INVERSE signal input is high, that is, for performing negative / positive inversion.

A memory read counter (RD-CTR) 251 is a presettable UP / DOWN counter, and can set the start of addressing and the addressing direction arbitrarily. Note that 250 and 261 are multiplexers for switching the address input of each RAM. A is output when the A / B input is high, and B when the A / B input is low. When the output of JKFF262 is inverted at the next LSYNC, RAM266r,
g and b operate in the read mode, and the RAMs 263r, g and b enter the write mode. Hereinafter, this repetition is performed.

 Next, the RAM 224 and its related configuration will be described.

RAM224 consists of 1024 words (WORD) x 12bit, 32W
One set that uses ORD as one set and 32 sets is composed of RD-CTR251 preset data (1 word) and “SWITCH” output switching comparison data of 31W.
ORD can be set.

FIG. 4 is an explanatory diagram of the address data of the RAM 224.
Here, DSFx is for the preset of RD-CTR251, and DSWx- ₁ to ₃₁
Is the data for SWITCH.

FIG. 5 is a write cycle timing chart of the RAM 224. Data write to the RAM 224 is performed as shown in FIG. Although higher address 5bit (A9～A5) is carried out at the input than SCON, lower 5bit counter 222 1 ▲ ▼ pulse is incremented (from the SCON) each, since the next 11111 _B becomes 00000 _B, Does not require input from SCON.

Also, when it is not necessary to write all data,
For example, Dsf ₁ , Dsw1-1, and Dsw1-2 are written, and Dsw1-3 to Dsw1 to Dsw1 are written.
When sw1-31 is not required, CLR prior to writing the next Dsf ₂
Is output from one pulse SCON, and the counter 222 needs to be cleared.

228,225 is a bus driver and 239 is a multiplexer. When ▲ ▼ = Low, 228,225 can be output, 239 has high impedance, and outputs A _{9 to} A ₅ and D _{11 to} D ₀ signals from SCON. It can be correctly given to the RAM 224.

The writing to the RAM 224 is performed before the copy operation.

 Next, reading of the RAM 224 will be described.

Reading of the RAM is performed when image data is sent from the SC 100. This is shown in FIG.

At this time, CS1 and ▲ ▼ are kept High, and CLR is kept Low.

A _{9 to} A ₅ are sent from SCON at appropriate timing as upper addresses during memory read.

D ₁₁ to D ₀ is not a memory, for the one comparison input of the comparator 254, sent from SCON.

Also, it is assumed that DSWx _{-1 to} DSWx _-31 in the RAM 224 are stored from the lowest address to the lowest value.

A ₉ to A ₅ is a is appropriately provided from the previous LSYNC which valid image data is started is sent from the SC100.

237 is a shift register of four stages, the A ₉ to A ₅ of RAM 224, S
It is provided to provide A _{9 to} A ₅ data given by CON with a delay of three LSYNC values. Also, data that is not delayed is used. This selection is made by the multiplexer 239.

Reference numeral 249 denotes a 13-bit counter, which is counted up by a continuous pulse CLK0 (having the same cycle as VCLK).

When b ₁₂ , b ₉ , and b _{8 of} this counter all become High, A
The output of the ND gate 244 becomes High, and the Q output of the RSFF242 becomes Hi.
gh, and the multiplexer 239 has an A input, that is, A ₉ before the delay.
Give ~A ₅ input to the RAM224.

Then, the output b ₂ of the counter 249 becomes High RSFF242 is reset, the multiplexer 239 B side, i.e. 3LSYNC
The address data delayed by a minute is supplied to the RAM 224 again.

 Note that RSFF242 is also reset by LSYNC.

_{That, b 12, b 9, b} 8 = become a High is CLK0 is 4864 th than _{LSYNC, b 12, b 9,} b 8 = High, become a b ₂ = High is
It is also the 4871st.

This value is set so as to be a value after the effective main traveling is completed.

Accordingly, in the valid image section, the RAM 224 is accessed with the address data delayed by 3 LSYNC, and the read data is input to the A input of the comparator 252. B input of the comparator is connected to the upper 12bit of _{RD-CTR251 (b 12 ~b 1} ). The comparator 252 outputs OUT = High only when the A and B inputs match.

Therefore, as long as the DSW data is not the same, the high output is performed only for 1 VCLK pulse. This output pulse is output to counter 22
It is also connected to the 2 CLK input, which is incremented.

The increment is also performed by LSYNC, and the clear is performed by Q = High of the RSFF242 described above.

Accordance connexion, A input of meaningful comparators lower address (A ₄ ~A ₆₎ is not 0 in the RAM 224, is started from the first read data, every time the comparator 252 is a match output, increments the RAM addresses Will compare the new RAM data with the output of the WR-CTR 251.

The OUT terminal of the comparator 252 is also connected to the CLK input of the JKFF 253, and toggles the coincidence output every time it is output.

The output of this JKFF253 is sent to the SWITCH
The output is input to the OR gate 212 in FIG.

XOR gate 260 is simply for inverting the output of JKFF253.

Next, when the RSFF 242 outputs High, that is, when accessing the RAM 224 with the data before the delay of A _{9 to} A ₅ from SCON, the output of the AND gate 223 is High and the counter 222 is cleared, The lower 5 bits (A _{4 to} A ₀ ) are 0,
The head of each set in the figure, that is, the value of DSW _x is read.

During this output, next to LOAD input of the RD-CTR251 is High, the read data of the memory the upper 12bit of RD-CTR251 (i ₁₂ ~
i ₁ ).

In FIG. 6, the output of the counter 222 indicates the case where the comparator 252 outputs the coincidence signal four times.

Further, Dsf ₁ ~ ₆ phrase at the output of the counter 251, RAM 2
It indicates that the first address to the sixth set in 24 are preset to the counter 251.

Image Pro Seth in service IP image processing, D ₁₁ to D ₀ is RAM22
Although it does not act on 4, the comparator 254 is effective as an A input, and one B input is connected to the output of RD-CTR. The comparator 254 outputs High only when A and B match. At this time, RSFF256 is set (Q is set to High), and RD-CTR251 is cleared.

The Q output of RSFF256 is output from the XOR gate 257 and OR gate 259
And input to the NAND gates 264 and 265. Therefore, when SWAP1 = High, and Q and LEFT / ▲ of RSFF256
▼ When only one of the inputs is high, the output of the RAM to be read (either 268r, g, b or 266r, g, b) is enabled, that is, the image data is output to the next block 203. . Not enabled (▲ ▼ input = High)
At this time, since the output of this RAM is high impedance, and therefore is pulled up, it is all High (= 255) and equal to white data.

FIG. 6 shows these operations in various cases.

Incidentally, the read of the RAM 224, to use a A ₉ to A ₅ of A ₉ to A ₅ and 3LSYNC after delay before the delay, the image data processed by the RD-CTR is, block 207C which blanking processing is performed, M, Y, B
There is a delay of 3LSYNC before being processed by K, and the S
This is because the WITCH output is used here. That is, this is to synchronize the image processing in the sub-scanning direction.

-Block 203 Color change (Color Change) Converts any color signal of R, G, B to a specific level with a 6-bit signal of CCHG ₀ to ₅ from SCON700. That is, a print process of a color different from the original image is performed.

Block 204 Color correction processing Color reproduction of color copy is performed by reading the original with a scanner, separating the pixels with R (red), G (green), and B (blue), and compensating for the color signals of those signals, that is, R, Complementary color conversion to C (cyan), M (magenta), and Y (yellow) signals that independently absorbs G and B wavelengths, and adds BK (black) required for three colors or for undercolor removal described below This is achieved by printing with the four colors of toner and ink.

If dots of each color are printed in the same position and printed, each dot can be represented by subtractive color mixture, but it is also possible to print at different screen angles for each color to remove color moiré. Can be done. In this case, C, M, and Y, R, G, and B of the secondary color, and K in which three colors are overlapped in one pixel
It is well known that eight colors of paper W (White) appear at random, and the color reproduction in this case can be represented by a Neugebauer equation that predicts a mixed color state from a halftone dot area of each color.

By the way, C, M, and Y color materials do not have ideal spectral reflection characteristics, but have a component that absorbs unnecessary colors called sub-absorption. In this case, different color materials are used depending on how the color materials overlap. Will be reproduced.

Therefore, the toner and ink having this side absorption are simply referred to as R,
If it is used as it is as a complementary color of G and B, the color will be cloudy and the desired color will not be reproduced. So, in the color reproduction problem,
A so-called color correction process for removing the influence of the sub-absorption and performing color reproduction faithful to the original image is required.

The simplest color correction processing is linear masking using a 3 × 3 matrix. If Dr, Dg, and Db are R, G, and B densities, And the components of the coefficient matrix can be obtained from the spectral characteristics of the color material.

If this method does not provide sufficient correction, use Dr ² , Dr D
By performing non-linear masking in consideration of the secondary terms such as g, color reproduction with higher accuracy can be obtained. In this embodiment, non-linear masking is employed.

For the color correction in the block 204, in order to perform high-speed image signal processing, the correction calculation result is stored in advance as 8-bit data (each color) in the ROM, and the input data is connected to the address line (24 bits) of the ROM. There is a method of obtaining a result (reading a memory).

UCR (under color removal) BP (black printing) When black is reproduced with the three colors C, M, and Y, the lack of density occurs in high density areas mainly due to the effect of surface reflection.

In order to prevent this problem, reduce the consumption of ink and toner, and reduce the fixing energy,
Removal of the gray component, that is, the same amount of C, M, and Y components from a certain color, or under color removal (UCR), and printing with black toner or ink equivalent to the removed gray. Or called BP (Black Print).

The UCR ratio can be selected arbitrarily, and if it is 100%,
There are advantages such as minimum consumption of toner.

When the UCR signal from the SCON700 is high, 100% UCR processing is performed, and the data is output in 6 bits for each of C, M, Y, and BK.

When the UCR signal is low, no UCR processing is performed, and the output of BK becomes 0.

max (maximum density extraction, output) When the MAX signal from the SCON700 is High, the minimum value of the input R, G, B signals from the block 203, that is, the signal corresponding to the maximum density in the original image is extracted, and the complement of that value is extracted. Are output to the next block 205 as 6-bit data of C, M, Y, and BK. At this time, the above-mentioned processes are stopped.

When the MAX signal is Low, the function stops, and
Works.

Block 205 scaling processing Before performing scaling processing (that is, before SC scanning), block 20
5 It is necessary to store the scaled data in the RAM for scaled data. This data is calculated by SCON700 according to the magnification (25% to 400%, 1% step).
With the ▼ = Low, “ZD ₀ to ₁₁ values are output and ▲ ▼
This is achieved by repeating the cycle of “generating one pulse”. The amount of data stored in this way is 1W
ORD (= 12bit) × 400, image data C, M, Y each 6bit
Is automatically scaled and output to the next block 206.

Block 206 Eight types of filter processing dither processing are selected with 3-bit data (CKIND ₀ to ₂ ) from SCON700.

For example, when CKIND ₀ to ₂ = 0, the whole surface smoothing filter processing +64
Level dither processing.

When CKIND ₀ to ₂ = 8, the halftone dot image portion is automatically separated from characters and line drawings, and the halftone dot image portion is subjected to smoothing filter processing + 64 level dither processing. For character and line drawing parts, sharpening filter processing +2
Perform level dither processing.

Filter processing Part 1: When sampling the original spatial frequency f ₀ of the moire removing processing halftone by dot document in a periodic pitch f _1, through Deizafuiruta frequency f _2, and outputs the printer of dots frequency f ₃ It will result in an _{f 0 -f 1, f 0 -f} 2 , etc. beats, i.e. moiré.

 A smoothing filter process for this is performed.

The filter of the embodiment is There is.

Part 2: Image sharpening (MTF correction) processing Laplacian ▽ ² f, which is the second derivative of the original image number f
It is well known that reducing the multiple of the constant causes an overshoot on both shoulders of the eclipsed edge and improves the sharpness, or MTF.

Laplacian filters typically include In this case, the differential calculation is performed only in the X and Y directions.Bokeh occurs in the rotation target, so if the calculation is performed in the 45 ° direction or in a multi-direction with a larger matrix size, more ideal results will be obtained. In this embodiment, a matrix size of 5 × 5 is used.

Dither processing The density gradation required for color copying is 64 gradations. However, with current recording techniques, such as electrophotography, thermal transfer, ink jet, etc., it is almost impossible to express this gradation in one dot, and at most several levels of gradation can be expressed by dot size or dot density modulation. Not just.

Therefore, in general, an area gradation method such as a density pattern method or a dither method is often used. The density pattern method corresponds to a plurality of output dots for one input data, and the dither method corresponds to one output dot for one input data.
The dither method, in which the number of gradations is the same, naturally provides a higher resolution.

In this embodiment, the dither method is adopted, and
It is used together with the 8-level modulation in the dot.

 This method is generally called a multi-value dither method.

In the dither method, the configuration of a threshold matrix plays an important role in tone reproducibility and resolution, and can be generally classified into the following two types.

a. Dot concentration type (Typical example Fatting type) b. Dot distributed type (Typical example Bayer type) Also, all thresholds in the threshold matrix are set to be the same,
Substantial binarization is also possible.

In this embodiment, according to CKIND ₀ to ₂ signals from SCON700,
One of these various threshold matrices is selected, the input signals C, M, Y, and BK each having 6 bits are processed into C, M, Y, and BK each having 3 bits, and output to the next block.

-Block 207 C, 207 M, 207 Y, 207 BK Image of unit 400 (MU) by combining each signal of CGATE, MGATE, YGATE, BKGATE from SCON700, AREA signal of block 202 and ALL signal from SCON The gate functions to pass data or not (corresponding to passing white data).

 This detailed circuit is shown in FIG.

 The values of the three bits of each color from the block 206 are as follows: 7: 1 pixel is the lowest (blank), 6 to 1: 1 is the intermediate density, and 0: 1 is the maximum density.

(4) Memory unit (MU) 400 FIG. 8 is a block diagram of the MU 400, (a) is a drawing connection diagram, (b) to (e) are partial views, and this memory unit is as follows. Has the functions of the following three modes.

Memory mode 1: The memory mode operates as a delay circuit that outputs C, M, and Y image data with a predetermined delay, and can be said to be a FIFO (First-In, First-Out) memory.

The amount of delay is from the BK photoreceptor 44BK of PR600 (Fig. 1).
It is delayed by a pixel corresponding to the length up to the C, M, Y photoconductors 44C, 44M, 44Y. Specifically, 110mm, 44
Since M is 220 mm and 44Y is 330 mm, the pixel density is 16 dots / mm, and the effective image width in the main scanning direction is 297 mm. C data: 16 × 110 × 16 × 297 = 8,863,520 pixels M data: 16 x 220 x 16 x 297 = 16,727,040 pixels Y data: 16 x 330 x 16 x 297 = 25,090,560 pixels Each data from IP200 is delayed and output to PR600.

This mode operates when the MMODE1 signal from SCON is high.

Memory mode 2: Write C, M, Y data from IP200 to memory. At this time, data is not output to PR600 (it may be output). This mode operates when the MMODE2 signal from SCON is high.

Memory mode 3: Data stored in memory mode 2 is output to PR600. The M and Y data are delayed with respect to the C data and output with M: 8,363,520 pixels and Y: 16,727,040 pixels, respectively.

This mode operates when the MMODE3 signal from SCON700 is High.

Reference numerals 401 ₀ to _{14 in} FIG. 8 denote memory blocks, which are shown in FIG.
1,048,576 words × 1 bit RAM combined 12 pieces, 1,048,57
Operate as a 6 word x 12 bit RAM.

The operation timing chart of the 1MDRAM in FIG. 9 is shown in FIGS.
3 The meaning and time of the symbols shown in FIG. 13A are as shown in FIG. 13B.

The memory blocks of the MU 400 correspond to the three modes of the MU and one of the following.

Memory mode 1 → memory read / write cycle Memory mode 2 → memory write cycle Memory mode 3 → memory read cycle Other → memory refresh cycle Note that in memory mode → 1 to 3, memory blocks with ▲ ▼ input high Automatically perform a memory refresh cycle. The circuit for this refresh is omitted for the sake of simplicity. It is also omitted in the timing chart (FIG. 27).

These memory control signals are provided by the timing signal generator 40
6 (FIG. 8) or a combination of other signals. This is shown in FIG.

This figure explains the timing of the memory, and the mode is not switched at such a short interval when a copy is made.

CLK0 is a continuous pulse with a frequency equal to the input speed of one pixel, generated by the control signal generator 211 in IP200.
Supplied to MU400. The frequency is 7MHz.

Outputs of timing generator 406 ▲ ▼, ▲ ▼,
ROW / ▲ ▼, WR1, LOAD are continuous waves having a frequency of 1/4 of CLK0, and the duty and phase of High and Low are different from each other as shown in FIG. Address clock ACLK is also 1/4 of CLK0
Although it is a pulse with a period, it is 1/4 (1
A pulse of 6 x 297 mm = 4752 pixels / 4) is generated continuously.
It stays low until the next LSYNC is input.
The repetition of generating pulses is performed.

This is shown in FIG. FIG. 14 shows a state in which the ACLK is continuously generated.

Although the OE (output enable) of the decoders 1 to 3 (417 ₁ to ₃ ) is complicated in an actual circuit, one of MMODE1, MMODE2, and MMODE3 is set to High for the sake of simplicity. , It is assumed that the OE input becomes High.

<Refresh> When all of MMODE1 to MMODE3 are Low, decoders 1 to 3
3 (417 ₁ to ₃ ) outputs ▲ ▼ to ▲ ▼ are all Hig
h. Accordingly, the outputs of the OR gates 408 ₀ to ₁₄ become High, and all the inputs of the memory blocks 401 ₀ to ₁₄ ▲ ▼ are High.
Since only ▲ ▼ is input, the refresh cycle shown in FIG. 13 is started.

<Read / Write> When MMODE1 input is High, decoder 1 (417 ₁ )
Any of ▼ to ▲ ▼ is Low output. In the decoder 2 (417 ₂ ), any one of ▼ to ▼ becomes Low output. Decoder 3 (417 ₃ ) is ▲ ▼ ~
One of ▲ ▼ becomes Low, ▲ ▼, ▲
It is assumed that ▼ does not become Low (the reason will be described later). Then, one Lo of the decoder 3 (417 ₃ )
w One of OR gates 408 ₁₂ to ₁₄ corresponding to output ▲ ▼
One outputs Low when the ▲ ▼ output of the timing signal generator 406 outputs a Low, Memoriburotsuku MB ₁₂ ~ ₁₄
In any one of (401 ₁₂ to ₁₄ ), a low pulse is input as shown in FIG. Since the ▲ inputs of the remaining two blocks remain High, they remain in the refresh cycle. Similarly,
Low output ▲ ▼ of decoder 2 is MB _{7 to} MB ₁₁ (401 ₇ to ₁₁ )
Is activated, and the remaining 4 blocks are not activated.

The low output CS of the decoder 1 (417 ₁ ) is connected to the OR gates 408 ₀ to ₄ , 4
One of the terminals 12,413 is set to Low input and OR gate 4
08 When Low is input to ₀ to ₄ , one of MB _{0 to} MB ₄ is ORed
When input to gate 412 or 413, inverter 439
Input High, Output Low. Therefore, AND gate 410 or 411
Output and Low, because eventually the Low at one terminal of the OR gate 408 ₅ or 408 ₆ is input, MB ₅ or MB ₆ is Akuteibu,
That is, only one of MB _{0 to} MB ₆ becomes ▲ = Low, becomes active, and the remaining six blocks remain inactive.

Multiplexer 2 (MP × 2: 409) has SEL input = Hi
X _{0 to} X ₁₁ are output to Z _{0 to} Z ₁₁ at gh, and Y ₀ to
Y ₁₁ is output. MMODE1 = In High X side is selected, MB _5, MB ₆ will be addressed to the value of the output of the address counter 1 (421 _1).

On the other hand, the output of AND gate 408 is the same as WR1 output of 406, the output of NOR gate 407 becomes an inversion of this, a pulse of "memory ▲ ▼" in FIG. 10 is Memoriburotsuku MB ₀ to 14 ▲ ▼ terminal.

In addition, Low / ▲ of the timing signal generator 406
▼ output, MPX3 (418), MPX4 ( 419), becomes the SEL input of MPX5 (420), SEL = when the High X ₀ ~ ₉ side is output, Y ₀ ~ ₉ side when SEL = Low is outputted Will be.
Therefore, the lower 10b of the address counters ₁ to ₃ (421 ₁ to ₃ )
it is input as the low address of each memory block,
The upper 10 bits are input as a COLUMN address.

▲ ▼, ▲ ▼, ▲
The operation timings of ▼ and A _{0 to} A ₉ coincide with the “read / write cycle” shown in FIG. 10, and the data existing in the RAM until then is output to DO ₀ to ₁₁ and Di ₀ to ₁₁ Will be written (stored) with the new data.

When <write> MMODE2 is High, ▲ ▼ output of the decoder 1-3 (417 _1-3), ▲ ▼ ₀ ~ ▲ ▼ only any one Low next _4, 417 ₁ of CS5, CS6 is a Low (This situation will be described later).

The output of decoder 1 (417 ₁ ) activates one of MB _{0 to} MB ₄ , and the output of decoder 2 (417 ₂ ) outputs MB _{7 to} MB ₁₁
And one of the Akuteibu, the output of the decoder 3 (417 _3), the one of the _{MB 5, MB 6, MB 12} ~MB 14 to Akuteibu.

Also, one of the inputs of the NOR gate 407 is always High, that is,
Since the output is always Low, ▲ ▼ of MB _{0 to} MB ₁₄
The input is always Low.

Incidentally, MB _5, MB address inputs A ₀ to A ₉ in _6, PMX2 (409)
Is low, the address counter 3 (42
The value of the output of the 1 ₃₎ is input.

▲ ▼, ▲ ▼, ▲
▼, The operation timing of A _{0 to} A ₉ coincides with the “write cycle” in FIG. 11, and the data applied to the input terminals Di _{0 to} Di ₉ is output while the outputs DO _{0 to} DO ₁₁ remain high impedance. Will write.

<Lead> When the MMODE3 input is High (MMODE1 and MMODE2 are Low), both inputs of the NOR gate 407 are Low and the output is High. Therefore, the ▲ ▼ inputs of MB _{0 to} MB ₁₄ become High.

 Others are the same as the case of <lead>.

In this case, ▲ ▼, ▲ ▼, ▲
The timings of ▼ and A _{0 to} A ₉ coincide with the “read cycle” in FIG. 12, so that new data is not input (write), and the data stored so far is output to the output terminals DO _{0 to} DO 9.
₁₁ will be output.

The input of A ₀ to A ₉ in MB _5, MB ₆ is given by the output value of MMODE1 (read-write mode) the address counter 1 (421 _1), the MMODE2 (write mode) and MMODE3 (read mode) In the same manner as given by the output value of the address counter 3 (421 ₃ ), the input data Di ₀ to _{11 of} MB ₅ and MB ₆ ,
The output data DO ₀ to DO ₁₁ are also switched according to the mode. The input data is switched by the MPX1 (403) and the output is switched by the demultiplexer DMPX (404).

MPX1 (403) outputs an input on the X side when SEL = High. When SEL = Low, Y side input is output. DMPX
(404) is output to A side when SEL = High, and B side becomes high impedance. When SEL = Low, output to B side,
The A side becomes high impedance.

402 _{Y, M, C} are serial / parallel converters, 3 bit
× 4 data is converted to 12-bit data.

405 _{Y, M, C} are parallel / serial converters, 12 bit
The data is converted to 3 bits × 4 data. That is, these converters, which perform the exact opposite operation of 402 _{Y, M, C} , are only needed to lower the operating frequency of the memory or memory control circuit.

MPX1 (403), since each SEL input of DMPX (404) is are directly connected to MMODE1 line, after all, when the MMODE1 = High, the input data of MB _{5, 6} is Y (yellow) data, MB _{5 , 6} are also output as Y data. When MMODE2 = High, the input data of MBs ₅ , ₆ is CDi ₀ which is C (cyan) data.
Data _1-3 are light, when the MMODE3 = High, are stored in the MB _{5, 6,} CD ₀₀ ~ ₂ data as C data
Will be output to

<Memory addressing in memory mode 1> At this time, SYMETRY2 = Low MIRROR2 = Low SWAP2 = Low MMODE1 = High MMODE2 = Low MMODE3 = Low VDENA = High is maintained during operation.

Then, the value of the data setting SW1 (416 ₁ ) = 16 × 330 × 16 × 297 × 1/4 =
6,272,640 Data setting SW2 (416 ₂ ) value = 16 x 220 x 16 x 297 x 1/4 =
4,181769 Data setting SW3 (416 ₃ ) value = 16 x 110 x 16 x 297 x 1/4 =
It is set to 2,090880.

One MSTART pulse is included, and all counters ₁ to ₃ (421 _1
3 ), all are cleared, and the ACLK from the timing signal generator 406 is applied to several gates (438, 441,.
...), The value is incremented by one each time ACLK is added.
Via 18,419,420, the Lo of each memory block
Join the w, COLUMN address.

On the other hand, the 4-bit outputs of the counters 1 to 3 are
417 Input to ₁ to ₃ and decode signal also ▲ ▼ ₀ to ▲
▼ Output to ₆ . ▲ ▼ output switches at 2 ²⁰ =
10,48,576 units.

On the other hand, the output of the counter _1-3, comparators 415 _1-3
The output 0 outputs High when it matches with the data setting switches ₁ to ₃ respectively. This output is
AND gate 426 ₁ ~ _3, OR gate 428 ₁ ~ _3, AND gate 423 ₁ to _3,
OR gate 431 _1-3, a monostable multivibrator MM _1-3 (430
Via ₁ to ₃ ), set the CLR terminal of each counter ₁ to ₃ to High for a very short time to clear it. After that, the above is repeated. Since the left input of the time AND gate 423 _1-3 always is Low, the output of AND gate 427 _1-3 is always Low, the output of the comparator 425 _1-3 not at all contribute to the counter CLR. This is shown in FIG.

Here, t0 = t1 = t2 = t3 = t4 ≠ t5. That is, there are unused components in the memory block 6.

The memory block 7 need not be accessed because it is not accessed. However, the following problem, that is, "when a counter error occurs in the counter, etc., the positional relationship of all pixel data thereafter becomes out of order. In other words, the pixels of the image are out of order, and the copy cannot be made correctly. "

For this reason, even if the count value goes out of order, it is more desirable to limit the error to the main scanning line and not to continue the error in the next main scanning line. Therefore, the counter is configured, for example, as shown in FIG. That is, the counter may be divided into lower 11 bits and upper 13 bits, and the lower 10 bits may be cleared every LSYNC.

At this time, the number of pixels of one scanning line is 9572, and ACLK is 11
Since it is 88, the memory also has the disadvantage that considerable unused components occur per scan line.

Therefore, a memory address control circuit which has a narrow range in which image data is disturbed when an error occurs and has a high effective use rate of a memory is desirable, but details are omitted since it is not directly related to the present invention. Only this time, Memoriburotsuku is required one more will be MB ₆ also used.

From the above, reading and writing are performed simultaneously, and addressing occurs in the cycle set by SW ₁ to ₃ (416 ₁ to ₃ ). Therefore, the data to be read is always from the time when only the set number is written. You can see that it is late.

<Addressing in memory mode 2> Counters ₁ to ₃ (421 ₁ to ₃ ) as address counters
Is used in the same manner as in the memory mode 1, MMODE2 and VDENA are kept high in the memory mode 2 and low in the other modes. At this time, the output of the inverter 450 becomes Low and is input to the AND gates 432 ₁ to ₃ , so that 426 ₁ to _{3 become} H
igh will not be output. That is, the comparator 415
Be _1-3 match output, the counter so will not be cleared, each decoder will be sequentially addressed from CS ₀ to CS _4. In addition, although it is output sequentially after CS ₅ ,
It will not be accessed because the target RAM is gone.
The above timing is shown in FIG.

<Addressing in memory mode 3> The counters ₁ to ₃ (421 ₁ to ₃ ) are used as the address counter because VDENA and MMODE3 are used as in modes 1 and 2.
High, otherwise low. FIG. 19 is an addressing timing chart in the memory mode 3 (MMODE3). When one START pulse is input, each counter 1
３3 are cleared and increase with the input of ACLK. Since at this stage RSFF1 remains is reset by START pulse, Q output Low, the output of Yotsute AND gates 434 ₁ to ₃ is Low.

Further, since it is the other input is also Low of OR gates 433 _1-3, OE decoders _1-3 (Autopu bracts enable) is
It remains Low.

Therefore, the CS outputs of decoders ₁ to ₃ (417 ₁ to ₃ ) are all Hig.
h, that is, the memory is not activated and remains in the refresh cycle. Each memory keeps counting up, the counter 1 has 24 bits, and the address input value of the comparator 1 is the data setting SW1 (416 ₁ ) (set value is 6,272,640)
If there is a match with the, the comparator outputs a High to the Q terminal, via dei rate line 422 _1, excisional the RSFF1, AND
High output of gate 426 _1, OR gate 428 _1, the AND gate 43
2 _1, OR gate 431 _1, monostable multivibrator MM ₁ (430 ₁₎
, The CLR input of the counter 1 is set to High for a moment, so that it is cleared.

The Q output of RSFF1 is also connected to the AND gates 434 _1,
RSFF1 is excisional (Q = High) 434 ₁ output from the time H
igh, and the 433 _first output is High, slave connexion, the output of the decoder 417 ₁ from this time becomes enabled, ▲ ▼ any is to be output, memory access is initiated.

After excisional of RSFF1 is, comparator 425 ₁ of the output is 1 input of the AND gate 427 _1, the Q output of RSFF1 is summer and the other input, the clear after the counter 1, A-side setting of the comparator 425 ₁ It is performed any number of times when the value (parallel output value of S / P converter 440) and the output value of counter 1 match.

 The above operation is shown in FIG.

In addition, the serial / parallel converter 440
CMPSD, by sending in synchronization with DSHIFT pulses from the data D ₁ to D ₂₉ as the timing shown in FIG. 20 the DSMIFT data, the output value of 24bit is set.

The output terminals DO ₀ to DO ₁₁ of the memory are all pulled up to High. Therefore, the memory output is high impedance except when read is enabled.
The value output to PR400 is 111B (corresponding to a blank).

In the above description, the number of memories corresponding to the number one less than the recording color component is provided as the memory. However, the number of the memories may be equal to the number of all the recording color components. In such a case, the configuration is effective for matching the reading position of each color component (taking resist).

(5) Printer Unit 600 Next, the printer unit (PR) will be described.

Referring to FIG. 2, the outputs of the CCDs 7r, 7g, and 7b are subjected to analog / digital conversion and subjected to necessary processing to obtain recording color information of black (BK), yellow (Y), magenta (M), and cyan. (C) Each of the 3 bits is converted into an octalized signal for recording energization.

For each of the octalized signals, C, M, and Y are memory units 400
, BK is directly from IP200 Printer Unit PR600
Are input to the laser drivers 112bk, 112y, 112m, and 112c, and the respective laser drivers are connected to the semiconductor lasers 113bk, 113y, and 113m.
And 113c, a laser beam modulated with a recording color signal (binary signal) is emitted.

FIG. 1 is referred to again. The emitted laser beams are reflected by the rotating polygon mirrors 13bk, 13y, 13m and 13c, respectively, and f
Through the -θ lenses 14bk, 14y, 14m and 14c, to the fourth mirror 15b
k, 15y, 15m and 15c and the fifth mirrors 16bk, 16y, 16m and 16c are reflected by the polygon mirror, and the polygon mirror 17b is a cylindrical lens 17b.
After passing through k, 17y, 17m and 17c, the photosensitive drums 18bk, 18y, 18m and 18c are irradiated with an image.

The rotating polygon mirrors 13bk, 13y, 13m, and 13c are fixed to the rotating shafts of the polygon mirror driving motors 41bk, 41y, 41m, and 41c, and each motor rotates at a constant speed and drives the polygon mirror at a constant speed. . By the rotation of the polygon mirror, the laser light is scanned in a direction perpendicular to the rotation direction (clockwise) of the photosensitive drum, that is, in a direction along the drum axis (this is referred to as a main scanning direction).

FIG. 21 is a detailed view of a laser scanning system of the cyan color recording apparatus, where 43c is a semiconductor laser.

At one end of the laser scanning (two-dot chain line) in the direction along the axis of the photosensitive drum 18c, a sensor 44c, which is a photoelectric conversion element, is provided so as to receive laser light. The start point of one-line scanning is detected at the time when the detection is made and the detection is changed to the non-detection. That is, the laser light detection signal (pulse) of the sensor 44c is processed as a laser scanning line synchronization pulse. The configurations of the magenta recording device, the yellow recording device, and the black recording device are exactly the same as those of the cyan recording device shown in FIG.

Referring again to FIG. 1, the surface of the photosensitive drum is uniformly charged by charge scorotrons 19bk, 19y, 19m, and 19c connected to a negative charge high voltage generator (not shown). When the laser beam modulated by the recording signal is applied to the uniformly charged photoreceptor surface, the charge on the photoreceptor surface is reduced by the photoconductive phenomenon to flow to the equipment ground of the drum body. Here, the laser is not turned on in a portion where the document density is high, and the laser is turned on in a portion where the document density is low. As a result, portions of the surface of the photosensitive drums 18bk, 18y, 18m, and 18c corresponding to portions where the document density is high have a potential of -800V, and portions corresponding to portions where the document density is low have a potential of about -100V. An electrostatic latent image is formed corresponding to the shading.
Each of the electrostatic latent images is referred to as a black developing unit 20bk,
Developed by the yellow developing unit 20y, the magenta developing unit 20m and the cyan developing unit 20c, and the black, black, and black are applied to the surfaces of the photosensitive drums 18bk, 18y, 18m and 18c, respectively.
A yellow, magenta and cyan toner image is formed.

The toner in the developing unit is positively charged by agitation, and the developing unit is biased to about -200 V by a developing bias generator (not shown). Correspondingly, a toner image is formed.

On the other hand, the recording paper 267 stored in the transfer paper cassette 22
The sheet is fed by the sheet feeding operation of the feed roller 23, and is sent to the transfer belt 25 at a predetermined timing by the registration roller 24. The recording paper placed on the transfer belt 25 is a transfer belt.
By the movement of 25, the photosensitive drums 18bk, 18y, 18m and 18c sequentially pass under the photosensitive drums 18bk, 18y, 18m and 18c.
, The black, yellow, magenta, and cyan toner images are sequentially transferred onto a recording sheet under the transfer belt by the action of a transfer corotron.

The transferred recording paper is then sent to the heat fixing unit 36, where the toner is fixed to the recording paper, and the recording paper is placed on a tray.
It is discharged to 37.

On the other hand, the residual toner on the photoreceptor surface after the transfer is removed by the cleaner units 21bk, 21y, 21m and 21c.

The recording devices for each color are arranged at a distance of 110 mm. The recording density is 16 dots / mm, the number of pixels in one main scanning line is 4752 dots, and the maximum number of pixels in the sub-scanning direction is 6720 dots.

Next, the printer controller 601 and its operation timing will be described. The printer controller includes a microcomputer unit including an output port with a driver for energizing each part of the printer, an input port for receiving an input from a sensor, an input / output interface with the SCON700, a CPU, a RAM, a ROM, an interrupt controller, and the like. It consists of a high-speed logic circuit for writing pixel data that is interfaced by the I / O section of the section.

First, turn on the system power switch 50.
When it is turned on, the PR600 section is also energized. ・ The temperature of the fixing unit 36 rises. ・ The constant speed rotation of the polygon mirror starts up. ・ The home positioning of the carriage 8 ・ The line synchronization clock (LSYNC) is generated (1.44KHz) ・ Clock for video synchronization (this is faster than CLK0: 7MHz)
(8.42MHz), ・ Initialize various counters, etc.

The line synchronous clock is a polygon mirror motor driver and IP20
0, SC100 and SCON700. The former uses this signal as a reference signal of a phase lock loop (PLL) servo, and the beam sensors 44bk, 44y, 4 which are feedback signals.
The beam detection signals of 4m and 44c are controlled so that they have the same frequency as the line synchronization clock and have a predetermined phase relationship.

As a signal for synchronizing the start of laser beam main scanning, detection signals (pulses) of the beam sensors 44bk, 44y, 44m, and 44c are used for each color (each sensor), and are used.
The frequency of the line synchronization signal and the detection signal of each beam sensor is
Since the signals are locked by the PLL and may cause the same but a slight phase difference, the scanning reference uses the detection signal of each beam sensor instead of the line synchronization signal. The video synchronization clock has a frequency of one dot (one pixel) for laser writing, and is supplied to the high-speed logic circuit for writing and the laser drivers 112bk, c, m, y.

The high-speed logic circuit for writing includes (1) two sets of image memories for one main scan (used as input toggle buffers), and (2) BK, C, M, and Y writing dot counters.

FIG. 22 is a timing chart of a print cycle.
When the warm-up operation is completed, the printer is ready for printing, and the PR 600 sends a “ready” status to the SCON 700. SCON is PR400 when the status of all other units is all "operable" and the copy button on the CU750 is pressed.
Sends a “Print Start” command to

When the PR receives this signal, the valid image data is input to the laser drivers 112BK, C, M, and Y with a delay of one main scanning line from the next LSYNC (because of the toggle buffer). , m, y. The write dot counters (BK, Y, M, C) are cleared at the rise of the detection signal of each beam sensor, and the count-up is performed by the video synchronization signal.

If the dot counter is between 1 and 400, it is dummy data and 401
Up to 5153 (4752 pieces) are writable values. Here, the dummy data is for adjusting the physical distance between the photosensitive drums 18bk, 18y, 18m and 18c of the beam sensors 44bk, 44y, 44m and 44c. Also, write data (7-0)
Is captured at the falling point of the video sync signal.

The first, second,... In the timing chart (FIG. 22)
The 6720 is the scanning line number of one main scanning line transferred to the same position in the sub-scanning direction on the transfer paper.

Writing to the toggle buffer memory is performed at the frequency of CLKO (7 MHz) supplied from IP200, and reading of one toggle buffer memory is performed using the video synchronization signal (8.42
MHz) cycle.

The difference between the two frequencies is that the effective scanning range of the laser beam is about 70% of the rotation angle of the motor 41c because the polygon mirror 13c is used as shown in FIG.
It is necessary to be faster.

In the microcomputer also has two sets of main scanning counter (LSYNC-CTR _{1, 2),} (a CTR ₁ in this case) one counter "print start" command from the SCON is cleared, the LSYNC Increment by 1 each time it enters. The LSYNC-CTR ₁ outputs an instruction to the laser drive circuit 112 _{BK, C, M, Y according} to the value as follows.

112bk The laser 43 _BK drive when LSYNC-CTR = 1 to 6,720, the other non-driving, the 112c laser 43 _c driven when LSYNC-CTR ₁ = 1760~8479, other non-driving, the 112m LSYNC- laser 43 _M drive when CTR ₁ = 3,520-102390, other non-driven, the laser 43 _Y driving time of the 112y LSYNC-CTR ₁ = 5286~12005, other non-driving, when making a plurality continuously Prints Receives the next “start” command from SCON700. At this time
If LSYNC-CTR ₁ is operating, clear LSYNC-CTR ₂ ,
Make a start.

The second image data controls the lasers 43 _{BK, C, M, and Y} as in the previous case. Further, when the third start signal is received, if LSYNC-CTR ₂ is operating, the first counter is cleared and the operation is started. Hereinafter, such a toggle operation is repeated to create a plurality of prints.
Therefore, even if random values for BK data from IP and C, M, Y data from MU are received outside the effective image section, the image is formed on the photoreceptor 18 _{BK, C, M, Y.} Never.

In fact, BK,
The output enable / disable flag for each color of C, M, and Y is set, and the logical AND of this flag and the above-mentioned LSYNC-CTR ₁ , ₂ is used to determine whether to output the laser 43 _{BK, C, M, and Y.} Do or not. This flag is set by a “color mode setting” command from SCON700.

(6) Console unit (CU) 750 Fig. 23 is a block diagram of the console unit.
FIG. 24 is a layout diagram of buttons and display means for operation display.

In FIG. 23, a console unit 750 includes a console board 750 ', a CPU 754, a matrix type or dynamic drive type I / O / decoder driver 756, an LCD controller 757, a video RAM (VIDEO RAM) 758, a RAM 759, a ROM 760,
Interrupt controller 761, serial I / O762, LCD driver
763.

The console board 750 'is a 512 × 256 dot L
It comprises a CD dot matrix display 751, an LED display group 752, and a switch matrix group 753. The switch matrix group 753 is composed of a group 1 and a group 2. The group 1 has 49 switches (normal push buttons) 765 to 813 in FIG. 24, and the group 2 has a transparent touch sensor button 753a-11 to 753. The touch sensor and the LCD dot matrix display 751 are provided at the same position in FIG. The touch sensor button is divided into eight in the horizontal direction and four in the vertical direction, and a total of 8 × 4 = 32
This constitutes a matrix of switches.

In FIG. 23, when the switch button of group 1 is pressed, the I / O / decoder driver 756 causes an interrupt signal 756a.
When the touch sensor switch of group 2 is pressed, the interrupt signal 756b is set high, and an interrupt subroutine is entered, and the ON / OFF status of all switches is checked by the CPU7.
54 can know. At this time, the information to be sent to SCON700 is sent to SCON7 via SCONI / F762 (serial I / O) immediately.
Sent to 00.

When some kind of display is required, the LED display group 752
Alternatively, it is displayed on the LCD dot matrix display 751.

The display can be changed by selecting one of the switch matrices 753.
One or more buttons are pressed, or a display command is received from SCON700.

 Next, a copy creation operation of the system will be described.

[1] Basic copy mode Scanner unit SC100 for making N copies
The image processor IP200 performs image processing on the data read by the SC100, and performs BK
The data is output directly to the printer unit PR600, and the C, M, Y data is output to the memory unit MU400. C,
The MU 400 that has received the M and Y data outputs the C data with a delay of C corresponding to a distance of 110 mm between the BK recording device and the C recording device in the PR 600. This 110mm is 110 × 16LSYNC = 176
0 main scanning lines, 1760 lines are 1760 x [297 mm (effective main scanning line length)
X 16 dots] = 8,363,520 pixels. This delay is generated and output to PR600. Similarly, M is 1,672,707 pixels,
Y is output to PR600 with a delay of 25,090,560 pixels. That is, the MU 400 is operated in the memory mode 1.

FIG. 25 is a timing diagram of the basic copy mode, in which (a) is a drawing combination diagram, (b) and (c) are partial views, and shows timings in the case of two-sheet repeat copy. In this case, set to 4-color full-color mode and use SCON70
0 is the BK, C, M, PR
Y, send all output enabled data. Various scan mode setting commands such as “A size reading” are sent to the SC 100. The UCR of IP200 is set to UCR execution. The 25th
In the figure, in the section of “SCON IP data output”, b is the output of what IP sets before image processing, for example, RA
For example, writing of M224.

B) IP is always output during image processing, it is valid,
For example, it may change on the way at UCR, D ₀ to ₁₁ or the like.

After the above, first, a "scan start command" is sent to the SC 100, and at the same time, the LSYNC counter in SCON (this is referred to as SYS-L-CTR) is cleared and the count is enabled.

SYS for the number of main scanning lines (number to number +) required for processing with IP200
When the count value of -L-CTR (hereinafter, this count value is called NIP) reaches, a "print start" command is output to PR600 and one pulse is output to MU400 after MSTART line.

Then, the BK of the image signal processed by the IP 200 is directly output to the PR, and the printing operation is performed immediately. C, M, and Y are input to the PR 600 with a delay of a predetermined number of pixels in the MU 400, and the printing operation of each color is performed. Here, the portion C outputs data stored in the MU (although there are others), but this value may be random.

However, in the PR600, as mentioned earlier, the LS in the PR600
Since the outputs of the lasers 43 _{BK, C, M, and Y} are controlled by the YNC-CTRs 1 and 2, this data is not printed.

When SYS-L-CTR in SCON reaches an appropriate value, it is cleared and a "start" command is sent to SC100 again.
Further, a “start” command is sent to the PR600. Note that no MSTART pulse is generated in the MU400.

By repeating the above, a repeat copy is created.

[2] High-speed copy mode To make N copies • One SC scan scan (at this time, IP processes the image and MU
Perform N times PR print operation (MU is MMODE3 at this time).

FIG. 26 is a timing chart of the high-speed copy mode,
(A) is a drawing combination diagram, and (b) and (c) are partial views showing timings when two copies are made.
When the High button (767) is pressed on the CU750 shown in Fig. 24, the CU
The display 767a is turned on by the 750 itself, and this information is immediately transmitted to the SCON 700. Then start button 8
When 13 is pressed, it is also sent to SCON700 immediately.

The SCON 700 sends a “scan mode setting” command to the SC 100 if necessary. If the IP needs to be set in advance, the SCON 700 sends the above data.

Next, the data of the above B is output to the IP, and MMODE2 of the MU is set to Hi.
Set to gh and send the "scan start" command to the SC. SY
When the SL-CTR counts the number of processing delay LSYNCs (nips) of the IP 200, one MSTART signal is sent to the MU 400.

Thus, first, the image data is stored in the MU 400. The sub-scan length that can be stored is When converted into the addressing of the address counters 421 ₁ to ₃ , it corresponds to 0 to 5,242,879. To increase the storage length in the sub-scanning direction, the memory blocks MBA and MB shown in FIG.
B and MBC may be added, and a chip select circuit may be added.

If the High button 767 is pressed while the “4Color” display 769a is lit on the CU750, the 769a is turned off and “3
"Color" display 768a.

In the three-color mode, when the SCON 700 outputs low data to IP, the UCR signal outputs low.

During the above, a “print mode setting” command is sent to PR600. This includes the information of "BK output not possible".

When all image data is stored in the MU, the SCON700
MMODE2 is set to Low, MMODE3 is set to High, an MSTART pulse is issued, and a “print start” command is sent to the PR600. Then, the counters 1 to 3 (421
₁ to ₃ ) start incrementing from 0, and from the counter that matches the value of the data setting switch 416 ₁ to ₃ , data is output from the memory addressed by the counter to the PR 600. The output is in the order of C, M, Y.

Each counter 421 ₁ to ₃ is an S / P converter for comparison from the following
The parallel output value becomes 440, and this is repeated.

In FIG. 26, each time is lengthened for easy viewing. Actually, send “Print Start” command, MSTA
The generation timing (t ₁ ) of the RT pulse is preferably generated immediately after the valid data of the SC 100 is processed by the IP 200.

It is preferable that the set value of the S / P converter is reduced to the limit of the valid data range [however, this set value is the address 1188 (= 4752 pixels × 1/1) used in one main scanning line.
4) must be an integer multiple of 4).

In this way, when making a large number of copies, it is not necessary to have the SC return time and print, so that the copy generation speed is greatly improved.

If an A4 size copy is made at 20 CPM when making a copy in the basic copy mode of [1] above, it will be about 26 CPM in this mode.

The 24-bit CMPSD data is sent to the MU 400 before the second MSTART pulse as shown in FIG.

[3] Swap copy mode in the main scanning direction In this mode, when the main scanning length of the original is 1 m and an arbitrary position in the main scanning direction of the original is 1x (0 <1x <1 m), the original
A mode that creates a copy in which the section from 1x to 1m is reproduced between 0 and (1m-1x) on the transfer paper, and the image between 0 and 1x on the original is reproduced between (1m-1x) and 1m on the transfer paper. It is.

In addition, it is possible to arbitrarily select the size of the original or the transfer paper, or to combine the scaling.

The setting and operation of this mode are performed as follows.
As a specific numerical example, a case where the document size and the transfer paper size are both A3 (main scanning length 273 mm), the swap position 1x = 120 mm, and the same size is described.

<Mode setting> First, press the button 783 on the CU750. Then, the display 783a is turned on, and at the same time, "Please enter a swap position" is displayed on the display 751 (see FIG. 24).

In response to this, 1x is input using the ten key buttons 816-0 to 816-9 and the enter button 808, in this case 120 is input. Then, "Swap position = 120 mm" is displayed on the LCD display. When the value of 1x has not been input, 1/2 of the main scanning length of the transfer paper, in this case, 148.5 mm is given as 1x as a default value.

<Operation> Referring to FIGS. 2, 3, 4, 5, 6, and 25, CU 750 transmits the above setting information to SCON 700 immediately after the setting input is performed.

The SCON 700 receiving these information sets the address 0 of the RAM 224 in the IP 200, that is, the Dsf1x × 1 of the memory map shown in FIG.
The value of 6/2, 1x = 120 in this example, 120 × 16/2 = 9
Write 60.

Also, as described above, this write operation is performed at the timing shown in FIG.

Subsequently, when the operator presses the start button 813, the SCO
The N700 outputs the following values to the following various signal lines to the IP200.

For D11 to D0, the effective main scanning reading length of the document x 16/2, in this example, both the document size and the transfer paper size are A3,
297 × 16/2 = 2376, and A9-A
0 is output for 5 and SWAP1 = 1, ALL = 1, LEFT / RI
GHT = 1.

The above output is assumed to be continuously maintained while the IP 200 processes the input image data.

The SCON700 also outputs various commands and signals to the SC100, MU400, and PR600. This timing is performed as shown in FIG.

Since this operation has been described in the section of [1] Basic copy mode, description thereof will be omitted.

From the above, the operation of each unit starts, and the image data of the document is input from the SC 100 to the IP 200.

When the image processing operation of the IP 200 is started, it operates according to the timing shown in FIG. That is, the number of VCLK pulses after the first LSYNC is counted by the counter 249,
When the count value reaches 4871, address 0 of RAM 224 is reached.
Is loaded as the preset value of RD-CTR251.

This load operation is performed every time LSYNC arrives, but since the values of A9 to A5 are always the same, the data to be loaded is always the same. In this example, twice the value stored previously, that is, 1920 is loaded.

Valid image data is sent from the SC100 from the second and subsequent LSYNCs, and these image data are temporarily stored in one of the toggle buffer memories 263r, g, b or 266r, g, b. Will be.

The relationship between the stored image data and the memory address is as follows. The image data at the main scanning start point is stored at address 0, the memory address is incremented as the scanning proceeds, and the input image data is stored in the memory at the same time. That is, the original image data is written to the memory in such a manner that the image position of the document and the address of the memory correspond to 1: 1.

The stored original image data is the next (third
The original image data is swapped at the stage of this read operation. Also this 1
The scanning line read operation consists of two steps, and operates as follows.

(Step 1 of Read) The initial value of the RD-CTR 251 immediately after the third LSYNC is twice the data of the address 0 of the RAM 224 as described above, and is 1920 in this example. Therefore, reading from the toggle buffer memory is started from address 1920 instead of address 0 in synchronization with the VCLK pulse.

The data at address 1920 is 120m from the main scanning start point of the original image
m, that is, the image data at the 1x position, and the image data in the sequential scanning direction is first sent out to the next step from the image data at this position.

The RD-CTR 251 is incremented for each pulse of VCLK, and this output value is used not only for read addressing of the toggle buffer memory but also as a B-side input signal of the comparator 254. on the other hand,
Upper 12 bits of A side input of this comparator (A12 to A1)
Are fixed to D11 to D0 from the SCON 700, and the least significant bit (A0) is fixed to 0. Therefore, when the RD-CTR 251 reaches twice the input value of D11 to D0, in this example, 4752, the comparator 254 clears the match signal 1 from the OUT terminal to the RD-CTR 251.

Therefore, the original image data output to the next process during this period is from the 1920th pixel data to the 4752th pixel data, that is, the section of 120 mm to 297 mm of the original image.

(Read Step 2) After RD-CTR251 is cleared, reading is performed from address 0 of the toggle buffer memory, and data is transferred to the next process until VCLK counts from LSYNC and reaches 4752 pulses, which is the number of effective pixels. Is output.

Accordingly, the image data of the original image output to the next process during this period is from the first pixel data to the 1919th pixel data, that is, the section from 0 mm to 120 mm of the original image.

By the read operation of the RAM 224 consisting of the two steps described above, the 0-1x section and the 1x-1m section of one scanning line of the original image are exchanged, that is, swapped and passed to the next step.

It is clear from the above description of the block 202 that the same operation is performed for the next main scanning line, and therefore the description is omitted.

By the above operation, 0 to 1x section and 1x section of all scanning lines of the original image
The ~ 1 m section is exchanged, that is, swapped and printed on transfer paper.

FIG. 27 shows the relationship between the original and the obtained copy at this time.

In the above embodiment, the case where the swap position does not change at the sub-scanning position has been described.

However, it is also possible to change the swap position according to the position in the sub-scanning direction.

<Mode setting> Mode setting related to this becomes complicated, so only the main points will be described.

In short, the operator simply makes the number n of swaps
Only n pairs of the position dimension value y in the sub-scanning direction and the desired swap position 1x in the main scanning direction corresponding to the position are input. That is, <Operation> First, the SCON700 is the RAM 224 in the IP 200 and the memory map shown in FIG. Except for the A9 to A5 signals, the SCON700 outputs commands and various signals to other units as before. In addition, SCON70
The software counter SYS-L-CTR in 0 is the IP2
00 is cleared before starting image processing.

Copy operation starts, and SYS-L-CT
R is incremented, but this SYS-L-
By appropriately switching A9 to A5 in accordance with the count value of the CTR, a plurality of copies at different swap positions can be obtained.

Then, in the previous example, the preset data of the RD-CTR 251 is the same, but in this embodiment, the values of A9 to A5 are switched according to the position in the sub-scanning direction, and the RA of the address is changed.
The data of M224 is different. Therefore, a different value is loaded as the preset value of the RS-CTR 251 each time.

As a result, the toggle buffer memory 263r, g, b or 266r,
In the g and b read operations, unlike the previous embodiment, the read start address, that is, the swap position is different for each position in the sub-scanning direction, and a copy having a plurality of swap positions is obtained.

Note that the value to be written to Dsf1 to Dsfn of the RAM 224 is arbitrary. For example, if 1 / 2,2376 of the number of effective pixels 4752 for main scanning is written, the comparator 254 immediately outputs the coincidence signal 1 and substantially No swap occurs. That is, it is possible to create a copy in which a specific section is swapped and the other specific sections are not performed.

Since A9 to A5 can be controlled freely, when the same main scanning swap position is scattered in different places in the sub-scanning direction, the respective values are not written in the RAM 224 but only in one place. However, the same data may be addressed at the time of reading.

FIG. 28 shows a copy example having a plurality of swap positions obtained in this manner.

〔effect〕

According to the present invention, it is possible to easily swap document images.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing the overall configuration of a digital color copying machine to which one embodiment of the present invention is applied, and FIGS. 2 (a-1) and 2 (a).
2) is a system block diagram of the copying machine shown in FIG. 1, FIG. 2 (b) is a drawing connection diagram, and FIGS. 2 (c), (d), (e),
(F) is a partial view, FIG. 2 (g) is an explanatory view showing how to call a gate, FIG. 3 is a circuit diagram of an image processor IP, FIG. FIGS. 4B and 4C are partial views, FIG. 4 is an explanatory diagram of address data of the RAM 224, and FIG.
FIG. 6 is a write cycle timing diagram of the RAM 224, FIG. 6 is an operation timing diagram of the image processor IP, FIG. 7 is a circuit diagram for explaining the circuit block 207c, and FIGS.
(A-2), (a-3), and (a-4) are memory units.
FIG. 8 (b) is a drawing connection diagram, FIGS. 8 (c), (d), (e) and (f) are partial views, and FIG.
The figure is a circuit diagram showing a RAM, FIG. 10, FIG. 11, FIG.
3 (a) is an operation timing diagram of the RAM of FIG. 9, FIG. 13 (b) is an explanatory diagram showing the meaning and time of symbols in FIGS. 10 to 13 (a), and FIG. 14 is a memory. FIG. 15 is an explanatory diagram of a pulse indicating an address clock, FIG. 16 is an explanatory diagram illustrating a relationship between an output of a comparator and a counter, FIG. 17 is a circuit diagram illustrating a configuration of a counter, FIG. 18 is a timing chart showing the addressing timing in the memory mode 2, FIG. 19 is a timing chart showing the addressing timing in the memory mode 3, FIG. 20 is a timing chart of the CMPSD data and the DSHIFT pulse, and FIG. FIG. 21 is a detailed view of the laser scanning system of the cyan recording apparatus, FIG. 22 is a timing diagram of a print cycle, and FIG.
FIG. 24 is a block diagram of the console unit, FIG. 24 is a layout diagram of operation display buttons and display means,
(B) and (c) are timing diagrams of the basic copy mode.
(A) is a drawing combination diagram, (b) and (c) are partial views, and FIG.
FIGS. (A), (b) and (c) are timing diagrams of the high-speed copy mode, (a) is a drawing combination diagram, (b) and (c) are partial views, and FIGS. 27 (a) and (b). ) Is an explanatory diagram showing the relationship between the original and the resulting copy when the document is swapped and printed on transfer paper. FIGS. 28 (a) and (b) are explanatory diagrams showing an example of a copy having a plurality of swap positions. . 263r, g, b, 266r, g, b ... memory means (toggle buffer memory), 251, 700 ... address sync changing means.

Claims (2)

(57) [Claims] An original is scanned and read by a scanner,
In an image forming apparatus for reproducing read image data on recording paper, storage means for storing the read image data for one line, and setting means for setting an initial value corresponding to a position to be swapped by setting from an operation unit A first address counter for giving a write address to the storage means by counting a clock synchronized with the image data from 0, and a clock synchronized with the image data from an initial value set in the setting means. A second address counter for giving a read address to the storage means by counting, and when a predetermined value which is the number of image data for one line matches a count value of the second address counter, Comparing means for setting the count value of the second address counter to 0; Image forming apparatus, characterized in that for a swap in the image data. 2. The apparatus according to claim 1, wherein said setting means is capable of setting an initial value for each line.
The image forming apparatus as described in the above.