JP2901064B2 - Image forming device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus in which an original image is color-separated and read two-dimensionally in pixel units, and image processing is performed digitally. The present invention relates to an image forming apparatus that enables editing and forms an image that has been subjected to image processing on a recording medium.

(Prior art)

An image forming apparatus in which a plurality of trimming areas can be set and a trimmed image can be moved, for example,
It is disclosed in JP-A-59-62885. In this image forming apparatus, the trimmed areas cannot be moved individually, and therefore, a plurality of trimmed areas are scattered here and there, making it difficult to read a print, and a plurality of trimmed areas cannot be read. There is a disadvantage that the recording paper cannot be made small because it is scattered everywhere, and the economy is lacking.

〔Purpose〕

The present invention has been made in view of the above-described inconveniences of the conventional apparatus, and an object thereof is to provide a plurality of trimming areas of a specific portion of an original image in the main scanning direction when there are a plurality of trimming areas. An object of the present invention is to provide an image forming apparatus capable of forming an image on a recording medium in which each trimming region is individually moved in the main scanning direction so that one end or the center position is set to a predetermined fixed position in the main scanning direction.

〔Constitution〕

In order to achieve the above object, the present invention provides an image forming apparatus that forms an image on a recording medium by passing the recording medium through the recording medium. A memory, a designating unit such as a digitizer tablet described later for designating a plurality of trimming regions for an image composed of image data input from the input unit, and Control means for performing trimming processing on the corresponding image data, and moving each of them so as to coincide with a predetermined position in a main scanning direction which is a direction perpendicular to the passing direction of the recording medium. Is what you do.

Hereinafter, a specific description will be given based on an embodiment of the present invention.

FIG. 1 is a block diagram of a digital color copying machine for explaining one embodiment of the present invention. 100 is a scanner unit (hereinafter referred to as SC), 200 is an image processor (hereinafter I)
P), 400 is a memory unit (hereinafter referred to as MU), 600 is a printer unit (hereinafter referred to as PU), 7
00 is a system controller (hereinafter referred to as SCON), 75
0 is a console unit (hereinafter referred to as CU), 900 is a digitizer tablet (hereinafter referred to as DG), 950 is a sorter unit (hereinafter referred to as ST), and 980 is an ADF unit (hereinafter referred to as AD).

2 (a), (b), (c), (d),
(E) is a system block diagram of the digital color copying machine shown in FIG. 1, and (a) is a combined diagram of the drawings.
(B)-(e) are each a partial view. The same reference numerals as those in FIG. 1 correspond to the same parts.

1 and 2, C indicates cyan, M indicates magenta, Y indicates yellow, R indicates red, G indicates green, B indicates blue, and BK indicates black.

In FIG. 2, the logic circuit is treated as positive logic, and a high voltage is High or 1 and a low voltage is Low or 0.
Described as As shown in FIG. 2 (f), A is a NAND gate, B is a NOR gate, C is an AND gate, D is an OR gate, E is a simple gate,
Then, F is the exclusive OR XOR.

First, among the configurations of the present invention, the SC100, IP200, MU400, PR600, SCON700, and CU750, which are the main parts,
The outline of those operations will be described.

(1) System Controller (SCON) 700 This is a computer that performs overall control of the digital color copying machine system of the present invention and is a stored program type computer.

 For example, each element can be configured as follows.

CPU704: Intel 8086 RAM712: Nidec Corporation µPD43256 x 4 (128KBYTE) ROM (PROM) 713: Intel 27512 x 10 (640KBYTE) Interrupt controller 710: Intel 8259 x 3 cascade connection (22 inputs) Timer / Counter 711 …… Intel8254 × 3 (9 timers /
Counter) Printer interface 703: Intel8255 (MODE2)
(Parallel type) Scanner interface 709: Same as above Console interface 708: Intel 8251 (serial communication type I / O) Image processor sign interface 701: Intel 8255
(MODE0) x 3 Memory unit interface 702 ... Intel8255 Digitizer tablet interface 707 ... Intel8251
(Serial communication type I / O) Sorter interface 706 ... Same as above ADF interface 705 ... Same as above Other components, such as a clock generator and a control signal decoder, are omitted.

(1-1) SC100 interface Physically, there are 8-bit bidirectional data lines and several control lines.

The instruction for SC is called SC command, At the time of data reception and data transmission completion, a signal is automatically input to the interrupt controller 710, and an interrupt service routine is automatically executed.

(1-2) PR600 interface Physically the same as SCI / F.

PR commands include: In addition, this signal pulse may not be generated by PR, but may be generated by, for example, SCON or IP, and supplied to another system.

This signal pulse is output from the interrupt controller 71.
It is input to 0 and is processed in real time.

(1-3) Interface to IP200 This interface is for output only.

γ _{0 to} γ ₂ … γ characteristics (density characteristics) of the copy for the original
(Group 8) MIRROR1 …… Instruction to make a mirror image copy in the main scanning direction SWAP1 …… Instruction to make a replacement copy of the image in the main scanning direction LEFT / ▲ ▼ …… Moving image copy in the main scanning direction instruction OUT / ▲ ▼ ...... region processing direction indicating INVERSE ...... concentration inverted copies creating a (blanking, partial color transform, partially quality processing selection) of inside or outside of the instruction a ₅ ~A ₉ ...... Upper 5bi addresses of RAM for area processing and image movement
t and address comparator data D _{0 to} D ₁₁ …… Area processing, image movement RAM data (12 bits) Clear the address counter of lower 6 bits of RAM for use and clear pulse of RAM address counter for scaling ▲ ▼ …… Write pulse for the above two types of RAM ALL …… Instruction not to perform area processing (when applied to the entire surface) CH _GCO ~ ₅ ...... Color conversion content instruction UCR ...... Instruction on whether to perform UCR (UNDER-COLOR-REMOVAL: under color removal) MAX ...... C, M, Y signals after complementary color generation and color correction Among them, the signal corresponding to the highest density is extracted, and the signal is sent to all the C, M, Y, and BK signal lines (for the next step of IP200, which will be described later). data of use RAM of Chitsupuserekuto (enable) ZD ₀ ~ ₁₁ ...... zooming RAM (12bit) CKIND ₀ ~ ₂ … Image quality processing, selection of 8 types OGATE …… Instruction whether to send cyan data MGATE …… Instruction whether to send magenta YGATE …… Instruction whether to send yellow BKGATE …… Sending or not sending black Instructions (1-4) vs. MU
400 interface An interface with output only.

SYMMETRY2: Used when making a target copy in the sub-scanning direction.

MIRROR2: Used to make a mirror image copy in the sub-scanning direction.

SWAP2: Used when making a replacement copy in the sub-scanning direction. COMPSD: Serial data of input data registers of three sets of 24-bit comparators inside the MU. DSHIFT: Shift pulse of the above register (shift register). Instruction to operate in FIFO (first-in, first-out) mode of MMODE2 …… Instruction to operate MU in write mode MMODE3 …… Instruction to operate MU in read mode MSTART …… Address counter of MU memory It is used for resetting.

VDENA …… Indicates whether or not the count-up of the address counter of the MU memory is possible (1-5) Interface to CU750 <Input> Imports key-in information of various keyboards, CU
When receiving data from the 750, the serial communication type I / O port
Since 708 generates an interrupt signal to 710, it is possible to quickly cope with a change in information of the CU 750.

<Output> Outputs data to be displayed on the console.

(1-6) Interface with DG900 <Input> Import XY coordinate data.

<Output> Sends buzzer and display lamp data.

I / O port 707 is an asynchronous serial communication system.
At the time of transmission, an interrupt signal is generated for 710.

(2) Scanner Unit (SC) 100 First, referring to FIG. 1, a document 1 is placed on a platen (contact glass) 2 and fluorescent lamps 3 ₁ , 3 ₂ for illuminating the document.
1st mirror which is illuminated by and whose reflected light can move
4 _1, is reflected by the second mirror 4, _second and third mirror 4 _3, through the imaging lens 5 enters the dichroic prism 6, wherein three wavelengths of light,-intensity (R), green (G) and It is split into blue (B). The split light enters the CCDs 7r, 7g, and 7b, which are solid-state imaging devices, respectively. That is, the red light is incident on the CCD 7r, the green light is incident on the CCD 7g, and the blue light is incident on the CCD 7b.

Fluorescent lamp 3 _1, 3 ₂ and the first mirror 4 ₁ is mounted on the first carriage 8, the second mirror 4 ₂ and the third mirror 4 ₃ is mounted on the second carriage 9, a second carriage 9 is first carriage 8 of
By moving at half speed, the optical path length from the document 1 to the CCD is kept constant, and the first and second carriages are scanned from right to left when reading the original image. Carriage drive pulley 11 fixed to the shaft of carriage drive motor 10
The first carriage 8 is connected to a carriage driving wire 12 wound around the vehicle, and the wire 12 is wound around a moving pulley (not shown) on the second carriage 9. Thus, the first carriage 8 and the second carriage move forward (original image reading scan) and return (return or forward direction original image reading scan) by forward and reverse rotation of the motor 10, and the second carriage 9 moves to the first carriage.
It moves at half the speed of the carriage 8.

When the first carriage 8 is at the home position shown in FIG. 1, the first carriage 8 is detected by a home position sensor 39 which is a reflection type photo sensor. When the first carriage 8 is driven to the right in the exposure scan and deviates from the home position, the sensor 39 does not receive light (carriage is not detected). When the first carriage 8 returns to the home position by return, the sensor 39 returns to the home position. Light reception (carriage detection) occurs, and the carriage 8 is stopped when the state changes from non-light reception to light reception.

Referring now to FIG. 2, the outputs of the CCDs 7r, 7g, and 7b are converted to 8-bit digital values by the A / D converters 102r, 102g, and 102b, that is, 256-level density signals.
It will be sent as a signal. Its value is 255 in white,
0 for black.

The control of the SC 100 is performed by the scanner controller 101.

The scanner controller 101 includes a CCD driver, a motor driver,
It is composed of those including various sensor input ports and SCON700I / F.

(3) Image processor (IP) 200 ・ Block 201 γ-correction processing (γ-Compensation) The gradation of the original and the copy is linear according to the characteristics of the read density gradation of SC and the print density gradation of PR. A correction process is performed so that

γ conversion processing (γ-Change) Processing for creating a copy having a γ characteristic different from that of the original, for example, a copy in which highlights are emphasized, a high contrast copy, or the like is performed.

Is one of the eight special γ characteristics, including the 3 bit signal from SCON, and the next block
R, G and B are output in 8 bits each.

Block 202 (see FIG. 3 for details) Mirroring 1 (MIRROR1) When the MIRROR1 signal from SCON is high, the arrangement of pixel data in the main scanning direction is inverted and output.

Swap 1 (SWAP1) The SWAP1 signal from SCON is high and the RAM shown in FIG.
224 loaded with appropriate data and LSY while scanning
When A ₆ to A ₁₁ in synchronization with the count value of the NC is given from SCON, replacement of the main scanning direction of the image.

Shift Part 1 RAM 224 to the appropriate data are loaded in advance, and when A ₆ to A ₁₁ in synchronization with the count value of LSYNC during scanning is given from the SCON, image positions of the same amount or a sub-scanning direction on the entire surface Are moved in different amounts. Movement direction is from SCON
Determined by LEFT / ▲ ▼ signal High / Low.

Appropriate data SWITCH output RAM224 are preloaded, and when A ₆ to A ₁₁ in synchronization with the count value of LSYNC during scanning is given from the SCON, block 202 High a SWITCH signal, Low
Output alternately.

This output is output to blocks 207C, M, Y, and BK for blanking part of the image (trimming processing), block 206 for partially changing the image quality processing, and partial color conversion. Is output to block 203.

Inverse (inversion) When the INVERSE signal from SCON is high, each bit of R, G, B 8 bits is inverted and output. The copy is therefore a negative image.

Next, a detailed description of the block 202 will be described with reference to FIGS.
This will be described with reference to FIGS. 5 and 6.

FIG. 3 is a circuit diagram of the image processor IP,
(A) is a drawing combination diagram, and (b) and (c) are partial views.

Two sets of RAM for each color (263r, g, b and 266r,
g, b). These RAMs are used as toggle buffer memories. When one set is taking in image data (writing to memory: memory write), one set is exposing data (reading memory: reading memory). . Switching between read and write is performed by JKFF every 1 LSYNC.
This is done by reversing 262.

FIG. 6 is an operation timing chart of the image processor IP. Assuming that the Q output of 262 goes high in the first LSYNC, one input of the OR gate 234 goes low, and VCLK (pulse generated by FIG. This pulse is also LSYN because there are 4752 pixels
4752 are generated between C and the next LSYNC. When the rising portion of the pulse (at the middle position of one pixel data) rises, a rising pulse is applied to the ▲ ▼ terminals of RAM 266r, RAM 266g and RAM 266, and the pixel data is written. The address at this time is the memory write counter (WR-
(CTR) 252.

Since the VCLK is also input to the CLK of the counter 252, the image data is sequentially written in the higher address direction.

On the other hand, in the RAMs 263r, 263g, and 263b, since one input of the OR gate 233 is High, the symbol ▼ is not active. Instead, if one of the three inputs of the NAND gate 264 connected to the output of the OR gate 259 is high, the input becomes low and the output is enabled, that is, the memory read is performed. Note that MM3 (248) is a retriggerable monomultivibrator whose output pulse width is set slightly longer than the cycle of VCLK. Therefore, as shown in FIG. 6, high output is continuously performed during generation of VCLK. .

Also, at this time, since the inputs of the bus drivers 268r, 268g, and 268b are high, the output is in a high impedance state,
The A input side is selected for the multiplexers 269r, g, and b.
The data is output to the next block 203 via R gates 230 ₀ r, g, b to 230 ₇ r, g, b.

The XOR gate is for inverting data when the INVERSE signal input is high, that is, for performing negative / positive inversion.

A memory read counter (RD-CTR) 251 is a presettable UP / DOWN counter, and can set the start of addressing and the addressing direction arbitrarily. Note that 250 and 261 are multiplexers for switching the address input of each RAM. A is output when the A / B input is high, and B when the A / B input is low. When the output of JKFF262 is inverted at the next LSYNC, RAM266r,
g and b operate in the read mode, and the RAMs 263r, g and b enter the write mode. Hereinafter, this repetition is performed.

 Next, the RAM 224 and its related configuration will be described.

RAM224 consists of 1024 words (WORD) x 12bit, 32W
One set that uses ORD as one set and 32 sets is composed of RD-CTR251 preset data (1 word) and “SWITCH” output switching comparison data of 31W.
ORD can be set.

FIG. 4 is an explanatory diagram of the address data of the RAM 224.
Here, DSFx is for the preset of RD-CTR251, and DSWx- ₁ to ₃₁
Is the data for SWITCH.

FIG. 5 is a write cycle timing chart of the RAM 224. Data write to the RAM 224 is performed as shown in FIG. Although higher address 5bit (A9～A5) is carried out at the input than SCON, lower 5bit counter 222 1 ▲ ▼ pulse is incremented (from the SCON) each, since the next 11111 _B becomes 00000 _B, Does not require input from SCON.

Also, when it is not necessary to write all data,
For example, Dsf ₁ , Dsw1-1, and Dsw1-2 are written, and Dsw1-3 to Dsw1 to Dsw1 are written.
When sw1-31 is not required, CLR prior to writing the next Dsf ₂
Is output from one pulse SCON, and the counter 222 needs to be cleared.

228,225 is a bus driver and 239 is a multiplexer. When ▲ ▼ = Low, 228,225 can be output, 239 has high impedance, and outputs A _{9 to} A ₅ and D _{11 to} D ₀ signals from SCON. It can be correctly given to the RAM 224.

The writing to the RAM 224 is performed before the copy operation.

 Next, reading of the RAM 224 will be described.

Reading of the RAM is performed when image data is sent from the SC 100. This is shown in FIG.

At this time, CS1 and ▲ ▼ are kept High, and CLR is kept Low.

A _{9 to} A ₅ are sent from SCON at appropriate timing as upper addresses during memory read.

D ₁₁ to D ₀ is not a memory, for the one comparison input of the comparator 254, sent from SCON.

Also, it is assumed that DSWx _{-1 to} DSWx _-31 in the RAM 224 are stored from the lowest address to the lowest value.

A ₉ to A ₅ is a is appropriately provided from the previous LSYNC which valid image data is started is sent from the SC100.

237 is a shift register of four stages, the A ₉ to A ₅ of RAM 224, S
It is provided to provide A _{9 to} A ₅ data given by CON with a delay of three LSYNC values. Also, data that is not delayed is used. This selection is made by the multiplexer 239.

Reference numeral 249 denotes a 13-bit counter, which is counted up by a continuous pulse CLK0 (having the same cycle as VCLK).

When b ₁₂ , b ₉ , and b _{8 of} this counter all become High, A
The output of the ND gate 244 becomes High, and the Q output of the RSFF242 becomes Hi.
gh, and the multiplexer 239 has an A input, that is, A ₉ before the delay.
Give ~A ₅ input to the RAM224.

Then, the output b ₂ of the counter 249 becomes High RSFF242 is reset, the multiplexer 239 B side, i.e. 3LSYNC
The address data delayed by a minute is supplied to the RAM 224 again.

 Note that RSFF242 is also reset by LSYNC.

_{That, b 12, b 9, b} 8 = become a High is CLK0 is 4864 th than _{LSYNC, b 12, b 9,} b 8 = High, become a b ₂ = High is
It is also the 4871st.

This value is set so as to be a value after the effective main traveling is completed.

Accordingly, in the valid image section, the RAM 224 is accessed with the address data delayed by 3 LSYNC, and the read data is input to the A input of the comparator 252. B input of the comparator is connected to the upper 12bit of _{RD-CTR251 (b 12 ~b 1} ). The comparator 252 outputs OUT = High only when the A and B inputs match.

Therefore, as long as the DSW data is not the same, the high output is performed only for 1 VCLK pulse. This output pulse is output to counter 22
It is also connected to the 2 CLK input, which is incremented.

The increment is also performed by LSYNC, and the clear is performed by Q = High of the RSFF242 described above.

Accordance connexion, A input of meaningful comparators lower address (A ₄ to A ₀₎ is not 0 in the RAM 224, is started from the first read data, every time the comparator 252 is a match output, increments the RAM addresses Will compare the new RAM data with the output of the WR-CTR 251.

The OUT terminal of the comparator 252 is also connected to the CLK input of the JKFF 253, and toggles the coincidence output every time it is output.

The output of this JKFF253 is sent to the SWITCH
The output is input to the OR gate 212 in FIG.

XOR gate 260 is simply for inverting the output of JKFF253.

Next, when the RSFF 242 outputs High, that is, when accessing the RAM 224 with the data before the delay of A _{9 to} A ₅ from SCON, the output of the AND gate 223 is High and the counter 222 is cleared, The lower 5 bits (A _{4 to} A ₀ ) are 0,
The head of each set in the figure, that is, the value of DSW _x is read.

During this output, next to LOAD input of the RD-CTR251 is High, the read data of the memory the upper 12bit of RD-CTR251 (i ₁₂ ~
i ₁ ).

In FIG. 6, the output of the counter 222 indicates the case where the comparator 252 outputs one signal four times.

Further, Dsf ₁ ~ ₆ phrase at the output of the counter 251, RAM 2
It indicates that the first address to the sixth set in 24 are preset to the counter 251.

Image Pro Seth in service IP image processing, D ₁₁ to D ₀ is RAM22
Although it does not act on 4, the comparator 254 is effective as an A input, and one B input is connected to the output of RD-CTR. The comparator 254 outputs High only when A and B match. At this time, RSFF256 is set (Q is set to High), and RD-CTR251 is cleared.

The Q output of RSFF256 is output from the XOR gate 257 and OR gate 259
And input to the NAND gates 264 and 265. Therefore, when SWAP1 = High, and Q and LEFT / ▲ of RSFF256
▼ When only one of the inputs is high, the output of the RAM to be read (either 268r, g, b or 266r, g, b) is enabled, that is, the image data is output to the next block 203. . Not enabled (▲ ▼ input = High)
At this time, since the output of this RAM is high impedance, and therefore is pulled up, it is all High (= 255) and equal to white data.

FIG. 6 shows these operations in various cases.

Incidentally, the read of the RAM 224, to use a A ₉ to A ₅ of A ₉ to A ₅ and 3LSYNC after delay before the delay, the image data processed by the RD-CTR is, block 207C which blanking processing is performed, M, Y, B
There is a delay of 3LSYNC before being processed by K, and the S
This is because the WITCH output is used here. That is, this is to synchronize the image processing in the sub-scanning direction.

-Block 203 Color change (Color Change) Converts any color signal of R, G, B to a specific level with a 6-bit signal of CCHG ₀ to ₅ from SCON700. That is, a print process of a color different from the original image is performed.

Block 204 Color correction processing Color reproduction of color copy is performed by reading the original with a scanner, separating the pixels with R (red), G (green), and B (blue), and compensating for the color signals of those signals, that is, R, Complementary color conversion to C (cyan), M (magenta), and Y (yellow) signals that independently absorbs G and B wavelengths, and adds BK (black) required for three colors or for undercolor removal described below This is achieved by printing with the four colors of toner and ink.

If dots of each color are printed in the same position and printed, each dot can be represented by subtractive color mixture, but it is also possible to print at different screen angles for each color to remove color moiré. Can be done. In this case, C, M, and Y, R, G, and B of the secondary color, and K in which three colors are overlapped in one pixel
It is well known that eight colors of paper W (White) appear at random, and the color reproduction in this case can be represented by a Neugebauer equation that predicts a mixed color state from a halftone dot area of each color.

By the way, C, M, and Y color materials do not have ideal spectral reflection characteristics, but have a component that absorbs unnecessary colors called sub-absorption. In this case, different color materials are used depending on how the color materials overlap. Will be reproduced.

Therefore, the toner and ink having this side absorption are simply referred to as R,
If it is used as it is as a complementary color of G and B, the color will be cloudy and the desired color will not be reproduced. So, in the color reproduction problem,
A so-called color correction process for removing the influence of the sub-absorption and performing color reproduction faithful to the original image is required.

The simplest color correction processing is linear masking using a 3 × 3 matrix. If Dr, Dg, and Db are R, G, and B densities, And the components of the coefficient matrix can be obtained from the spectral characteristics of the color material.

If this method does not provide sufficient correction, Dr ² , Dr, D
By performing non-linear masking in consideration of the secondary terms such as g, color reproduction with higher accuracy can be obtained. In this embodiment, non-linear masking is employed.

For the color correction in the block 204, in order to perform high-speed image signal processing, the correction calculation result is stored in advance as 8-bit data (each color) in the ROM, and the input data is connected to the address line (24 bits) of the ROM. There is a method of obtaining a result (reading a memory).

UCR (under color removal) BP (black printing) When black is reproduced with the three colors C, M, and Y, the lack of density occurs in high density areas mainly due to the effect of surface reflection.

In order to prevent this problem, reduce the consumption of ink and toner, and reduce the fixing energy,
Removal of the gray component, that is, the same amount of C, M, and Y components from a certain color, or under color removal (UCR), and printing with black toner or ink equivalent to the removed gray. Or called BP (Black Print).

The UCR ratio can be selected arbitrarily, and if it is 100%,
There are advantages such as minimum consumption of toner.

When the UCR signal from SCON700 is High, 100% UCR processing is performed, and C, M, Y, and BK are output in 6 bits each.

When the UCR signal is low, no UCR processing is performed, and the output of BK becomes 0.

max (maximum density extraction, output) When the MAX signal from the SCON700 is High, the minimum value of the input R, G, B signals from the block 203, that is, the signal corresponding to the maximum density in the original image is extracted, and the complement of that value is extracted. Are output to the next block 205 as 6-bit data of C, M, Y, and BK. At this time, the above-mentioned processes are stopped.

When the MAX signal is Low, the function stops, and
Works.

Block 205 scaling processing Before performing scaling processing (that is, before SC scanning), block 20
5 It is necessary to store the scaled data in the RAM for scaled data. This data is calculated by SCON700 according to the magnification (25% to 400%, 1% step).
With the ▼ = Low, “ZD ₀ to ₁₁ values are output and ▲ ▼
This is achieved by repeating the cycle of “generating one pulse”. The amount of data stored in this way is 1W
ORD (= 12bit) × 400, image data C, M, Y each 6bit
Is automatically scaled and output to the next block 206.

Block 206 Eight types of filter processing dither processing are selected with 3-bit data (CKIND ₀ to ₂ ) from SCON700.

For example, when CKIND ₀ to ₂ = 0, the whole surface smoothing filter processing +64
Level dither processing.

When CKIND ₀ to ₂ = 8, the halftone dot image portion is automatically separated from characters and line drawings, and the halftone dot image portion is subjected to smoothing filter processing + 64 level dither processing. For character and line drawing parts, sharpening filter processing +2
Perform level dither processing.

Filter processing Part 1: When sampling the original spatial frequency f ₀ of the moire removing processing halftone by dot document in a periodic pitch f _1, through Deizafuiruta frequency f _2, and outputs the printer of dots frequency f ₃ It will result in an _{f 0 -f 1, f 0 -f} 2 , etc. beats, i.e. moiré.

 A smoothing filter process for this is performed.

The filter of the embodiment is There is.

Part 2: Image sharpening (MTF correction) processing Laplacian ▽ ² f, which is the second derivative of the original image number f
It is well known that reducing the constant multiple of causes an overshoot on both shoulders of the eccentric edge and improves the sharpness, ie, the MTF.

Laplacian filters typically include In this case, the differential calculation is performed only in the X and Y directions.Bokeh occurs in the rotation target, so if the calculation is performed in the 45 ° direction or in a multi-direction with a larger matrix size, more ideal results will be obtained. In this embodiment, a matrix size of 5 × 5 is used.

Dither processing The density gradation required for color copying is 64 gradations. However, with current recording techniques, such as electrophotography, thermal transfer, ink jet, etc., it is almost impossible to express this gradation in one dot, and at most several levels of gradation can be expressed by dot size or dot density modulation. Not just.

Therefore, in general, an area gradation method such as a density pattern method or a dither method is often used. The density pattern method corresponds to a plurality of output dots for one input data, and the dither method corresponds to one output dot for one input data.
The dither method, in which the number of gradations is the same, naturally provides a higher resolution.

In this embodiment, the dither method is adopted, and
It is used together with the 8-level modulation in the dot.

 This method is generally called a multi-value dither method.

In the dither method, the configuration of a threshold matrix plays an important role in tone reproducibility and resolution, and can be generally classified into the following two types.

a. Dot concentration type (Typical example Fatting type) b. Dot distributed type (Typical example Bayer type) Also, all thresholds in the threshold matrix are set to be the same,
Substantial binarization is also possible.

In this embodiment, according to CKIND ₀ to ₂ signals from SCON700,
One of these various threshold matrices is selected, the input signals C, M, Y, and BK each having 6 bits are processed into C, M, Y, and BK each having 3 bits, and output to the next block.

Blocks 207C, 207M, 207Y, 207BK Whether to pass image data to the unit 400 (MU) by combining the CGATE, MGATE, YGATE, BKGATE signals from SCON700, the AREA signal of block 202, and the ALL signal from SCON , No (equivalent to passing white data).

 This detailed circuit is shown in FIG.

 The values of the three bits of each color from the block 206 are as follows: 7: 1 pixel is the lowest (blank), 6 to 1: 1 is the intermediate density, and 0: 1 is the maximum density.

(4) Memory unit (MU) 400 FIG. 8 is a block diagram of the MU 400, (a) is a drawing connection diagram, (b) to (e) are partial views, and this memory unit is as follows. Has the functions of the following three modes.

Memory mode 1: The memory mode operates as a delay circuit that outputs C, M, and Y image data with a predetermined delay, and can be said to be a FIFO (First-In, First-Out) memory.

The amount of delay is from the BK photoreceptor 44BK of PR600 (Fig. 1).
It is delayed by a pixel corresponding to the length up to the C, M, Y photoconductors 44C, 44M, 44Y. Specifically, 110mm, 44
M data is 220 mm, up to 44Y is 330 mm, pixel density is 16 dots / mm, and effective image width in the main scanning direction is 297 mm. C data: 16 × 110 × 16 × 297 = 8,363,520 pixels M data: 16 x 220 x 16 x 297 = 16,727,040 pixels Y data: 16 x 330 x 16 x 297 = 25,090,560 pixels Each data from IP200 is delayed and output to PR600.

This mode operates when the MMODE1 signal from SCON is high.

Memory mode 2: Write C, M, Y data from IP200 to memory. At this time, the data is not output to the PR600 (it may be output). This mode operates when the MMODE2 signal from SCON is high.

Memory card 3: Outputs data stored in memory mode 2 to PR600. The M and Y data are delayed with respect to the C data and output with M: 8,363,520 pixels and Y: 16,727,040 pixels, respectively.

This mode operates when the MMODE3 signal from SCON700 is High.

Reference numerals 401 ₀ to _{14 in} FIG. 8 denote memory blocks, which are shown in FIG.
1,048,576 words × 1 bit RAM combined 12 pieces, 1,048,57
Operate as a 6 word x 12 bit RAM.

The operation timing chart of the 1MDRAM in FIG. 9 is shown in FIGS.
3 The meaning and time of the symbols shown in FIG. 13A are as shown in FIG. 13B.

The memory blocks of the MU 400 correspond to the three modes of the MU and one of the following.

Memory mode 1 → memory read / write cycle Memory mode 2 → memory write cycle Memory mode 3 → memory read cycle Other → memory refresh cycle Automatically perform a memory flush cycle. The circuit for this refresh is omitted for the sake of simplicity. It is also omitted in the timing chart (FIG. 27).

These memory control signals are provided by the timing signal generator 40
6 (FIG. 8) or a combination of other signals. This is shown in FIG.

This figure explains the timing of the memory, and the mode is not switched at such a short interval when a copy is made.

CLK0 is a continuous pulse with a frequency equal to the input speed of one pixel, generated by the control signal generator 211 in IP200.
Supplied to MU400. The frequency is 7MHz.

Outputs of timing generator 406 ▲ ▼, ▲ ▼,
ROW / ▲ ▼, WR1, LOAD are continuous waves having a frequency of 1/4 of CLK0, and the duty and phase of High and Low are different from each other as shown in FIG. Address clock ACLK is also 1/4 of CLK0
Although it is a pulse with a period, it is 1/4 (1
A pulse of 6 x 297 mm = 4752 pixels / 4) is generated continuously.
It stays low until the next LSYNC is input.
The repetition of generating pulses is performed.

This is shown in FIG. FIG. 14 shows a state in which the ACLK is continuously generated.

Although the OE (output enable) of the decoders 1 to 3 (417 ₁ to ₃ ) is complicated in an actual circuit, one of MMODE1, MMODE2, and MMODE3 is set to High for the sake of simplicity. , It is assumed that the OE input becomes High.

<Refresh> When MMODE1 to MMODE3 are all Low, decoders 1 to 3
3 (417 ₁ to ₃ ) outputs ▲ ▼ to ▲ ▼ are all Hig
h. Accordingly, the outputs of the OR gates 408 ₀ to ₁₄ become High, and all the inputs of the memory blocks 401 ₀ to ₁₄ ▲ ▼ are High.
Since only ▲ ▼ is input, the refresh cycle shown in FIG. 13 is started.

<Read / Write> When MMODE1 input is High, decoder 1 (417 ₁ )
Any of ▼ to ▲ ▼ is Low output. In the decoder 2 (417 ₂ ), any one of ▼ to ▼ becomes Low output. Decoder 3 (417 ₃ ) is ▲ ▼ ~
One of ▲ ▼ becomes Low, ▲ ▼ ~ ▲
It is assumed that ▼ does not become Low (the reason will be described later). Then, one Lo of the decoder 3 (417 ₃ )
w One of OR gates 408 ₁₂ to ₁₄ corresponding to output ▲ ▼
One outputs Low when the ▲ ▼ output of the timing signal generator 406 outputs a Low, Memoriburotsuku MB ₁₂ ~ ₁₄
In any one of (401 ₁₂ to ₁₄ ), a low pulse is input as shown in FIG. Since the ▲ inputs of the remaining two blocks remain High, they remain in the refresh cycle. Similarly,
Low output ▲ ▼ of decoder 2 is MB _{7 to} MB ₁₁ (401 ₇ to ₁₁ )
Is activated, and the remaining 4 blocks are not activated.

The Low output CS of the decoder 1 (417 ₁ ) has one of the OR gates 408 ₀ to ₄ , 412, 413 as one Low input, and MB _{0 to} M when low input to the OR gates 408 ₀ to _4.
Either B ₄ is input High, the output Low of inverter 439 when entered into OR gate 412 or 413. Accordance connexion, the AND gate 410 or 411 outputs a Low, because eventually Low is input at one terminal of the OR gate 408 ₅ or 408 _6, MB ₅ or MB
₆ is active, that is, only one of MB _{0 to} MB ₆
▼ = Low, becomes active, and the remaining 6 blocks remain inactive.

Multiplexer 2 (MPX2: 409) has SEL input = Hig
When h, X _{0 to} X ₁₁ are output to Z _{0 to} Z ₁₁ , and when SEL input is Low, Y ₀ to Y
₁₁ is output. When MMODE1 = High, the X side is selected,
MB ₅ and MB ₆ are addressed to the output value of the address counter 1 (421 ₁ ).

On the other hand, the output of AND gate 408 is the same as WR1 output of 406, the output of NOR gate 407 becomes an inversion of this, a pulse of "memory ▲ ▼" in FIG. 10 is Memoriburotsuku MB ₀ to 14 ▲ ▼ terminal.

In addition, Low / ▲ of the timing signal generator 406
▼ output, MPX3 (418), MPX4 ( 419), becomes the SEL input of MPX5 (420), SEL = when the High X ₀ ~ ₉ side is output, Y ₀ ~ ₉ side when SEL = Low is outputted Will be.
Therefore, the lower 10b of the address counters ₁ to ₃ (421 ₁ to ₃ )
it is input as the low address of each memory block,
The upper 10 bits are input as a COLUMN address.

▲ ▼, ▲ ▼, ▲
The operation timings of ▼ and A _{0 to} A ₉ coincide with the “read / write cycle” shown in FIG. 10, and the data existing in the RAM until then is output to DO ₀ to ₁₁ and Di ₀ to ₁₁ Will be written (stored) with the new data.

When <write> MMODE2 is High, ▲ ▼ output of the decoder 1-3 (417 _1-3), ▲ ▼ ₀ ~ ▲ ▼ only any one Low next _4, 417 ₁ of CS5, CS6 is a Low (This situation will be described later).

The output of decoder 1 (417 ₁ ) activates one of MB _{0 to} MB ₄ , and the output of decoder 2 (417 ₂ ) outputs MB _{7 to} MB ₁₁
And one of the Akuteibu, the output of the decoder 3 (417 _3), the one of the _{MB 5, MB 6, MB 12} ~MB 14 to Akuteibu.

Also, one of the inputs of the NOR gate 407 is always High, that is,
Since the output is always Low, ▲ ▼ of MB _{0 to} MB ₁₄
The input is always Low.

Incidentally, MB _5, MB address inputs A ₀ to A ₉ in _6, PMX2 (409)
Is low, the address counter 3 (42
The value of the output of the 1 ₃₎ is input.

▲ ▼, ▲ ▼, ▲
▼, The operation timing of A _{0 to} A ₉ coincides with the “write cycle” in FIG. 11, and the data applied to the input terminals Di _{0 to} Di ₉ is output while the outputs DO _{0 to} DO ₁₁ remain high impedance. Will write.

<Read> When the MMODE3 input is High (MMODE1 and 2 are Low), the two inputs of the NOR gate 407 are both Low and the output is High. Therefore, the ▲ ▼ inputs of MB _{0 to} MB ₁₄ become High.

 Others are the same as the case of <lead>.

In this case, ▲ ▼, ▲ ▼, ▲
The timings of ▼ and A _{0 to} A ₉ coincide with the “read cycle” in FIG. 12, so that new data is not input (write), and the data stored so far is output to the output terminals DO _{0 to} DO 9.
₁₁ will be output.

The input of A ₀ to A ₉ in MB _5, MB ₆ is given by the output value of MMODE1 (read-write mode) the address counter 1 (421 _1), the MMODE2 (write mode) and MMODE3 (read mode) In the same manner as given by the output value of the address counter 3 (421 ₃ ), the input data Di ₀ to _{11 of} MB ₅ and MB ₆ ,
The output data DO ₀ to DO ₁₁ are also switched according to the mode. The input data is switched by the MPX1 (403) and the output is switched by the demultiplexer DMPX (404).

MPX1 (403) outputs an input on the X side when SEL = High. When SEL = Low, Y side input is output. DMPX
(404) is output to A side when SEL = High, and B side becomes high impedance. When SEL = Low, output to B side,
The A side becomes high impedance.

402 _{Y, M, C} are serial / parallel converters, 3 bit
× 4 data is converted to 12-bit data.

405 _{Y, M, C} are parallel / serial converters, 12 bit
The data is converted to 3 bits × 4 data. That is, these converters, which perform the exact opposite operation of 402 _{Y, M, C} , are only needed to lower the operating frequency of the memory or memory control circuit.

MPX1 (403), since each SEL input of DMPX (404) is are directly connected to MMODE1 line, after all, when the MMODE1 = High, the input data of MB _{5, 6} is Y (yellow) data, MB _{5 the} output of the ₆ also output as Y data, MMODE2 = when the High, CDi ₀ ~ ₃ input data is C (cyan) data MB _{5, 6}
Data is written, when the MMODE3 = High, is stored in the MB _5,6, CD ₀₀ ~ ₂ data as a C data
Will be output to

<Memory addressing in memory mode 1> At this time, SYMETRY2 = Low MIRROR2 = Low SWAP2 = Low MMODE1 = High MMODE2 = Low MMODE3 = Low VDENA = High is maintained during operation.

Then, the value of the data setting SW1 (416 ₁ ) = 16 × 330 × 16 × 297 × 1/4 =
6,272,640 Data setting SW2 (416 ₂ ) value = 16 x 220 x 16 x 297 x 1/4 =
4,181769 Data setting SW3 (416 ₃ ) value = 16 x 110 x 16 x 297 x 1/4 =
It is set to 2,090880.

One MSTART pulse is included, and all counters ₁ to ₃ (421 _1
3 ), all are cleared, and ACLK is supplied from the timing signal generator 406 to the CLK terminal by several gates (438, 441,...).
…)), The output is incremented by one each time ACLK is added.
Via 19,420, low and CO of each memory block
Join the LUMN address.

On the other hand, the output of the upper 4 bits of the counters 1 to 3 is
417 Input to ₁ to ₃ and decode signal also ▲ ▼ ₀ to ▲
▼ Output to ₆ . ▲ ▼ output switches at 2 ²⁰ =
10,48,576 units.

On the other hand, the output of the counter _1-3, comparators 415 _1-3
The output 0 outputs High when it matches with the data setting switches ₁ to ₃ respectively. This output is
AND gate 426 ₁ ~ _3, OR gate 428 ₁ ~ _3, AND gate 423 ₁ to _3,
OR gate 431 _1-3, a monostable multivibrator MM _1-3 (430
Via ₁ to ₃ ), set the CLR terminal of each counter ₁ to ₃ to High for a very short time to clear it. After that, the above is repeated. Since the left input of the time AND gate 423 _1-3 always is Low, the output of AND gate 427 _1-3 is always Low, the output of the comparator 425 _1-3 not at all contribute to the counter CLR. This is shown in FIG.

Here, t0 = t1 = t2 = t3 = t4 ≠ t5. That is, there are unused components in the memory block 6.

The memory block 7 need not be accessed because it is not accessed. However, the following problem, that is, "when the count error occurs in the counter in the middle, etc., the positional relationship of all the pixel data thereafter becomes out of order. In other words, the pixels of the image are out of order, and the copy cannot be made correctly. "

For this reason, even if the count value goes out of order, it is more desirable to limit the error to the main scanning line and not to continue the error in the next main scanning line. Therefore, the counter is configured, for example, as shown in FIG. That is, the counter may be divided into lower 11 bits and upper 13 bits, and the lower 10 bits may be cleared every LSYNC.

At this time, the number of pixels of one scanning line is 9572, and ACLK is 11
Since it is 88, the memory also has the disadvantage that considerable unused components occur per scan line.

Therefore, a memory address control circuit which has a narrow range in which image data is disturbed when an error occurs and has a high effective use rate of a memory is desirable, but details are omitted since it is not directly related to the present invention. Only this time, Memoriburotsuku is required one more will be MB ₆ also used.

From the above, reading and writing are performed simultaneously, and addressing occurs in the cycle set by SW ₁ to ₃ (416 ₁ to ₃ ). Therefore, the data to be read is always from the time when only the set number is written. You can see that it is late.

<Addressing in memory mode 2> Counters ₁ to ₃ (421 ₁ to ₃ ) as address counters
Is used in the same manner as in the memory mode 1, MMODE2 and VDENA are kept high in the memory mode 2 and low in the other modes. At this time, the output of the inverter 450 becomes Low and is input to the AND gates 432 ₁ to ₃ , so that 426 ₁ to _{3 become} H
igh will not be output. That is, the comparator 415
Be _1-3 match output, the counter so will not be cleared, each decoder will be sequentially addressed from CS ₀ to CS _4. In addition, although it is output sequentially after CS ₅ ,
It will not be accessed because the target RAM is gone.
The above timing is shown in FIG.

<Addressing for Memory Card 3> The counters ₁ to ₃ (421 ₁ to ₃ ) are used as the address counter in the same manner as in Modes 1 and 2 by using VDENA and MMODE3.
High, otherwise low. FIG. 19 is an addressing timing chart in the memory mode 3 (MMODE3). When one START pulse is input, each counter 1
３3 are cleared and increase with the input of ACLK. Since at this stage RSFF1 remains is reset by START pulse, Q output Low, the output of Yotsute AND gates 434 ₁ to ₃ is Low.

Further, since it is the other input is also Low of OR gates 433 _1-3, OE decoders _1-3 (Autopu bracts enable) is
It remains Low.

Therefore, the CS outputs of decoders ₁ to ₃ (417 ₁ to ₃ ) are all Hig.
h, that is, the memory is not activated and remains in the refresh cycle. Each memory keeps counting up, the counter 1 has 24 bits, and the address input value of the comparator 1 is the data setting SW1 (416 ₁ ) (set value is 6,272,640)
If there is a match with the, the comparator outputs a High to the Q terminal, via dei rate line 422 _1, excisional the RSFF1, AND
High output of gate 426 _1, OR gate 428 _1, the AND gate 43
2 _1, OR gate 431 _1, monostable multivibrator MM ₁ (430 ₁₎
, The CLR input of the counter 1 is set to High for a moment, so that it is cleared.

The Q output of RSFF1 is also connected to the AND gates 434 _1,
RSFF1 is excisional (Q = High) 434 ₁ output from the time H
igh, and the 433 _first output is High, slave connexion, the output of the decoder 417 ₁ from this time becomes enabled, ▲ ▼ any is to be output, memory access is initiated.

After excisional of RSFF1 is, comparator 425 ₁ of the output is 1 input of the AND gate 427 _1, the Q output of RSFF1 is summer and the other input, the clear after the counter 1, A-side setting of the comparator 425 ₁ It is performed any number of times when the value (parallel output value of S / P converter 440) and the output value of counter 1 match.

 The above operation is shown in FIG.

In addition, the serial / parallel converter 440
CMPSD, by sending in synchronization with DSHIFT pulses from the data D ₁ to D ₂₉ as the timing shown in FIG. 20 the DSMIFT data, the output value of 24bit is set.

The output terminals DO ₀ to DO ₁₁ of the memory are all pulled up to High. Therefore, the memory output is high impedance except when read is enabled.
The value output to PR400 is 111B (corresponding to a blank).

In the above description, the number of memories corresponding to the number one less than the recording color component is provided as the memory. However, the number of the memories may be equal to the number of all the recording color components. In such a case, the configuration is effective for matching the reading position of each color component (taking resist).

(5) Printer Unit 600 Next, the printer unit (PR) will be described.

Referring to FIG. 2, the outputs of the CCDs 7r, 7g, and 7b are subjected to analog / digital conversion and subjected to necessary processing to obtain recording color information of black (BK), yellow (Y), magenta (M), and cyan. (C) Each of the 3 bits is converted into an octalized signal for recording energization.

For each of the octalized signals, C, M, and Y are memory units 400
, BK is directly from IP200 Printer Unit PR600
Are input to the laser drivers 112bk, 112y, 112m, and 112c, and the respective laser drivers are connected to the semiconductor lasers 113bk, 113y, and 113m.
And 113c, a laser beam modulated with a recording color signal (binary signal) is emitted.

FIG. 1 is referred to again. The emitted laser beams are reflected by the rotating polygon mirrors 13bk, 13y, 13m and 13c, respectively, and f
Through the -θ lenses 14bk, 14y, 14m and 14c, to the fourth mirror 15b
k, 15y, 15m and 15c and the fifth mirrors 16bk, 16y, 16m and 16c are reflected by the polygon mirror, and the polygon mirror 17b is a cylindrical lens 17b.
After passing through k, 17y, 17m and 17c, the photosensitive drums 18bk, 18y, 18m and 18c are irradiated with an image.

The rotating polygon mirrors 13bk, 13y, 13m, and 13c are fixed to the rotating shafts of the polygon mirror driving motors 41bk, 41y, 41m, and 41c, and each motor rotates at a constant speed and drives the polygon mirror at a constant speed. . By the rotation of the polygon mirror, the laser light is scanned in a direction perpendicular to the rotation direction (clockwise) of the photosensitive drum, that is, in a direction along the drum axis (this is referred to as a main scanning direction).

FIG. 21 is a detailed view of a laser scanning system of the cyan color recording apparatus, where 43c is a semiconductor laser.

At one end of the laser scanning (two-dot chain line) in the direction along the axis of the photosensitive drum 18c, a sensor 44c, which is a photoelectric conversion element, is provided so as to receive the laser beam. The start point of one-line scanning is detected at the time when the detection is made and the detection is changed to the non-detection. That is, the laser light detection signal (pulse) of the sensor 44c is processed as a laser scanning line synchronization pulse. The configurations of the magenta recording device, the yellow recording device, and the black recording device are exactly the same as those of the cyan recording device shown in FIG.

Referring again to FIG. 1, the surface of the photosensitive drum is uniformly charged by charge scorotrons 19bk, 19y, 19m, and 19c connected to a negative charge high voltage generator (not shown). When the laser beam modulated by the recording signal is applied to the uniformly charged photoreceptor surface, charges on the photoreceptor surface flow to the equipment ground of the drum main body due to a photoconductive phenomenon and are reduced. Here, the laser is not turned on in a portion where the document density is high, and the laser is turned on in a portion where the document density is low. As a result, portions of the surface of the photosensitive drums 18bk, 18y, 18m, and 18c corresponding to portions where the document density is high have a potential of -800V, and portions corresponding to portions where the document density is low have a potential of about -100V. An electrostatic latent image is formed corresponding to the shading.
Each of the electrostatic latent images is referred to as a black developing unit 20bk,
Developed by the yellow developing unit 20y, the magenta developing unit 20m and the cyan developing unit 20c, and the black, black, and black are applied to the surfaces of the photosensitive drums 18bk, 18y, 18m and 18c, respectively.
A yellow, magenta and cyan toner image is formed.

The toner in the developing unit is positively charged by stirring, and the developing unit is biased to about -200 V by a developing bias generator (not shown). , A toner image is formed.

On the other hand, the recording paper 267 stored in the transfer paper cassette 22
The sheet is fed by the sheet feeding operation of the feed roller 23, and is sent to the transfer belt 25 at a predetermined timing by the registration roller 24. The recording paper placed on the transfer belt 25 is a transfer belt.
With the movement of 25, the photosensitive drums 18bk, 18y, 18m and 18c sequentially pass under the photosensitive drums 18kb, 18y, 18m and 18c.
, The black, yellow, magenta, and cyan toner images are sequentially transferred onto a recording sheet under the transfer belt by the action of a transfer corotron.

The transferred recording paper is then sent to the heat fixing unit 36, where the toner is fixed to the recording paper, and the recording paper is placed on a tray.
It is discharged to 37.

On the other hand, the residual toner on the photoreceptor surface after the transfer is removed by the cleaner units 21bk, 21y, 21m and 21c.

The recording devices for each color are arranged at a distance of 110 mm. The recording density is 16 dots / mm, the number of pixels in one main scanning line is 4752 dots, and the maximum number of pixels in the sub-scanning direction is 6720 dots.

Next, the printer controller 601 and its operation timing will be described. The printer controller includes a microcomputer unit including an output port with a driver for energizing each part of the printer, an input port for receiving an input from a sensor, an input / output interface with the SCON700, a CPU, a RAM, a ROM, an interrupt controller, and the like. It consists of a high-speed logic circuit for writing pixel data that is interfaced by the I / O section of the section.

First, turn on the system power switch 50.
When it is turned on, the PR600 unit is also energized. ・ The temperature of the fixing unit 36 rises. ・ The constant speed rotation of the polygon mirror starts up. ・ The home positioning of the carriage 8 ・ The clock for line synchronization (LSYNC) is generated (1.44KHz), Hz) ・ Clock for video synchronization (this is faster than CLK0: 7MHz)
Occurs (8.42M, initialization of various counters, etc.).

The line synchronous clock is a polygon mirror motor driver and IP20
0, SC100 and SCOM700. The former uses this signal as a reference signal of a phase lock loop (PLL) servo, and the beam sensors 44bk, 44y, 4
The beam detection signals of 4m and 44c are controlled so that they have the same frequency as the line synchronization clock and have a predetermined phase relationship.

As a signal for synchronizing the start of laser beam main scanning, detection signals (pulses) of the beam sensors 44bk, 44y, 44m, and 44c are used for each color (each sensor), and are used.
The frequency of the line synchronization signal and the detection signal of each beam sensor is
Since the signals are locked by the PLL and may cause the same but a slight phase difference, the scanning reference uses the detection signal of each beam sensor instead of the line synchronization signal. The video synchronization clock has a frequency of one dot (one pixel) for laser writing, and is supplied to the high-speed logic circuit for writing and the laser drivers 112bk, c, m, y.

The high-speed logic circuits for writing include (1) two sets of image memories for one main scan (used as input toggle buffers), and (2) BK, C, M, and Y writing dot counters.

FIG. 22 is a timing chart of a print cycle.
When the warm-up operation is completed, the printer is ready for printing, and the PR 600 sends a “ready” status to the SCON 700. SCON is PR400 when the status of all other units is all "operable" and the copy button on the CU750 is pressed.
Sends a “Print Start” command to

When the PR receives this signal, the valid image data is input to the laser drivers 112BK, C, M, and Y with a delay of one main scanning line from the next LSYNC (because of the toggle buffer). , m, y. The write dot counters (BK, Y, M, C) are cleared at the rise of the detection signal of each beam sensor, and the count-up is performed by the video synchronization signal.

If the dot counter is between 1 and 400, it is dummy data and 401
Up to 5153 (4752 pieces) are writable values. Here, the dummy data is for adjusting the physical distance between the photosensitive drums 18bk, 18y, 18m and 18c of the beam sensors 44bk, 44y, 44m and 44c. Also, write data (7-0)
Is captured at the falling point of the video sync signal.

In addition, the first, second,... In the timing chart (FIG. 22)
6720 is a scanning line number of one main scanning line transferred to the same position in the sub-scanning direction on the transfer paper.

Writing to the toggle buffer memory is performed at the frequency of CLKO (7 MHz) supplied from IP200, and reading of one toggle buffer memory is performed using the video synchronization signal (8.42
MHz) cycle.

The difference between the two frequencies is that the effective scanning range of the laser beam is about 70% of the rotation angle of the motor 41c because the polygon mirror 13c is used as shown in FIG.
It is necessary to be faster.

In the microcomputer also has two sets of main scanning counter (LSYNC-CTR _{1, 2),} (a CTR ₁ in this case) one counter "print start" command from the SCON is cleared, the LSYNC Increment by 1 each time it enters. The LSYNC-CTR ₁ outputs an instruction to the laser drive circuit 112 _{BK, C, M, Y according} to the value as follows.

112bk The laser 43 _BK drive when LSYNC-CRT = 1-6720, other non-driven, laser 43c driving time of the 112c LSYNC-CRT ₁ = 1760~8479, other non-driving, the 112m LSYNC-CTR _{When 1} = 3520 to 102390, laser 43 _M drive, otherwise non-drive, LSYNC-CTR for 112y ₁ = 5286 to 12005, laser 43 _Y drive, other non-drive, when printing multiple sheets continuously , SCON700 receives the next “start” command. At this time
If LSYNC-CTR ₁ is operating, clear LSYNC-CTR ₂ ,
Make a start.

The second image data controls the lasers 43 _{BK, C, M, and Y} as in the previous case. Further, when the third start signal is received, if LSYNC-CTR ₂ is operating, the first counter is cleared and the operation is started. Hereinafter, such a toggle operation is repeated to create a plurality of prints.
Therefore, even if random values for BK data from IP and C, M, Y data from MU are received outside the effective image section, the image is formed on the photoreceptor 18 _{BK, C, M, Y.} Never.

In fact, BK,
The output enable / disable flag for each color of C, M, and Y is set, and the logical AND of this flag and the above-mentioned LSYNC-CTR ₁ , ₂ is used to determine whether to output the laser 43 _{BK, C, M, and Y.} Do or not. This flag is set by a “color mode setting” command from SCON700.

(6) Console unit (CU) 750 Fig. 23 is a block diagram of the console unit.
FIG. 24 is a layout diagram of buttons and display means for operation display.

In FIG. 23, the console unit 750 comprises a console board 750 ', a CPU 754, a matrix or dynamic drive type I / O / decoder driver 756, an LCD controller 757, a video RAM (VIDEO RAM) 758, a RAM 759, a ROM 760,
Interrupt controller 761, serial I / O762, LCD driver
763.

The console board 750 'is a 512 × 256 dot L
It comprises a CD dot matrix display 751, an LED display group 752, and a switch matrix group 753. The switch matrix group 753 is composed of a group 1 and a group 2. The group 1 has 49 switches (normal push buttons) 765 to 813 in FIG. 24, and the group 2 has a transparent touch sensor button 753a-11 to 753. The touch sensor and the LCD dot matrix display 751 are provided at the same position in FIG. The touch sensor button is divided into eight in the horizontal direction and four in the vertical direction, and a total of 8 × 4 =
It comprises 32 matrix switches.

In FIG. 23, when the switch button of group 1 is pressed, the I / O / decoder driver 756 causes an interrupt signal 756a.
When the touch sensor switch of group 2 is pressed, the interrupt signal 756b is set high, and an interrupt subroutine is entered, and the ON / OFF status of all switches is checked by the CPU7.
54 can know. At this time, the information to be sent to SCON700 is sent to SCON7 via SCONI / F762 (serial I / O) immediately.
Sent to 00.

When some kind of display is required, the LED display group 752
Alternatively, it is displayed on the LCD dot matrix display 751.

The display can be changed by selecting one of the switch matrices 753.
One or more buttons are pressed, or a display command is received from SCON700.

 Next, a copy creation operation of the system will be described.

[1] Basic copy mode Scanner unit SC100 for making N copies
The image processor IP200 performs image processing on the data read by the SC100, and performs BK
The data is output directly to the printer unit PR600, and the C, M, Y data is output to the memory unit MU400. C,
The MU 400 that has received the M and Y data outputs the C data with a delay of C corresponding to a distance of 110 mm between the BK recording device and the C recording device in the PR 600. This 110mm is 110 × 16LSYNC = 176
0 main scanning lines, 1760 lines are 1760 x [297 mm (effective main scanning line length)
X 16 dots] = 8,363,520 pixels. This delay is generated and output to PR600. Similarly, M is 1,672,707 pixels,
Y is output to PR600 with a delay of 25,090,560 pixels. That is, the MU 400 is operated in the memory mode 1.

FIG. 25 is a timing diagram of the basic copy mode, in which (a) is a drawing combination diagram, (b) and (c) are partial views, and shows timings in the case of two-sheet repeat copy. In this case, set to 4-color full-color mode and use SCON70
0 is the BK, C, M, PR
Y, send all output enabled data. Various scan mode setting commands such as “A size reading” are sent to the SC 100. The UCR of IP200 is set to UCR execution. The 25th
In the figure, in the section “Output of SCON IP data”, b is the output of what IP sets before image processing, for example, RA
For example, writing of M224.

C. IP is always output during image processing, it is valid,
For example UCR, also be changed during the like D _O ~ _11.

After the above, first, a "scan start command" is sent to the SC 100, and at the same time, the LSYNC counter in SCON (this is referred to as SYS-L-CTR) is cleared and the count is enabled.

SYS for the number of main scanning lines (several to several tens) required for processing with IP200
When the count value of -L-CTR (hereinafter, this count value is referred to as NIP) reaches, a "print start" command is output to PR600 and one pulse is output to MSTART line to MU400.

Then, the BK of the image signal processed by the IP 200 is directly output to the PR, and the printing operation is performed immediately. C, M, and Y are input to the PR 600 with a delay of a predetermined number of pixels in the MU 400, and the printing operation of each color is performed. Here, the part (d) outputs the data stored in the MU (although there are others), but this value may be random.

However, in the PR600, as mentioned earlier, the LS in the PR600
Since the outputs of the lasers 43 _{BK, C, M, and Y} are controlled by the YNC-CTRs 1 and 2, this data is not printed.

When SYS-L-CTR in SCON reaches an appropriate value, it is cleared and a "start" command is sent to SC100 again.
Further, a “start” command is sent to the PR600. Note that no MSTART pulse is generated in the MU400.

By repeating the above, a repeat copy is created.

[2] High-speed copy mode To make N copies • One SC scan scan (at this time, IP processes the image and MU
Perform N times PR print operation (MU is MMODE3 at this time).

FIG. 26 is a timing chart of the high-speed copy mode,
(A) is a drawing combination diagram, and (b) and (c) are partial views showing timings when two copies are made.
When the High button (767) is pressed on the CU750 shown in Fig. 24, the CU
The display 767a is turned on by the 750 itself, and this information is immediately transmitted to the SCON 700. Then start button 8
When 13 is pressed, it is also sent to SCON700 immediately.

The SCON 700 sends a “scan mode setting” command to the SC 100 if necessary. If the IP needs to be set in advance, the SCON 700 sends the data of the above B.

Next, the data of (c) is output to the IP, and MMODE2 of the MU is set to Hi.
Set to gh and send the "scan start" command to the SC. SY
When the SL-CTR counts the number of processing delay LSYNCs (nips) of the IP 200, one MSTART signal is sent to the MU 400.

Thus, first, the image data is stored in the MU 400. The sub-scan length that can be stored is When converted into the addressing of the address counters 421 ₁ to ₃ , it corresponds to 0 to 5,242,879. To increase the storage length in the sub-scanning direction, the memory blocks MBA and MB shown in FIG.
B and MBC may be added, and a chip select circuit may be added.

If the High button 767 is pressed while the “4Color” display 769a is lit on the CU750, the 769a is turned off and “3
"Color" display 768a.

In the three-color mode, when the SCON 700 outputs the data of C to IP, the UCR signal outputs Low.

During the above, a “print mode setting” command is sent to PR600. This includes the information of "BK output not possible".

When all image data is stored in the MU, the SCON700
MMODE2 is set to Low, MMODE3 is set to High, an MSTART pulse is issued, and a “print start” command is sent to the PR600. Then, the counters 1 to 3 (421
₁ to ₃ ) start incrementing from 0, and from the counter that matches the value of the data setting switch 416 ₁ to ₃ , data is output from the memory addressed by the counter to the PR 600. The output is in the order of C, M, Y.

Each counter 421 ₁ to ₃ is an S / P converter for comparison from the following
The parallel output value becomes 440, and this is repeated.

In FIG. 26, each time is lengthened for easy viewing. Actually, send “Print Start” command, MSTA
The generation timing (t ₁ ) of the RT pulse is preferably generated immediately after the valid data of the SC 100 is processed by the IP 200.

It is preferable that the set value of the S / P converter is reduced to the limit of the valid data range [however, this set value is the address 1188 (= 4752 pixels × 1/1) used in one main scanning line.
4) must be an integer multiple of 4).

In this way, when making a large number of copies, it is not necessary to have the SC return time and print, so that the copy generation speed is greatly improved.

If an A4 size copy is made at 20 CPM when making a copy in the basic copy mode of [1] above, it will be about 26 CPM in this mode.

The 24-bit CMPSD data is sent to the MU 400 before the second MSTART pulse as shown in FIG.

Next, the trimming area set copy mode in the main scanning direction will be described.

This mode is used for trimming (in this case,
(It means that the inner image surrounded by a polygon such as a polygon, an octagon, ... is left and the outer is blanked.) When there are a plurality of areas, each of the plurality of trimming areas In this mode, each trimming region is individually moved in the main scanning direction as a print on transfer paper so that one end or the center position in the main scanning direction is adjusted to a predetermined fixed position in the main scanning direction.

The mode setting and operation will be described below. In addition, as an actual example, when three areas (one hexagon and two quadrilaterals) shown in FIG. 27 are designated as trimming areas, and are shifted in the main scanning direction to obtain a print of the same size. Is described.

First, the mode setting will be described with reference to FIG. When the operator presses the button 796, the display 796a turns on, and this mode can be set. It is also possible to move a plurality of trimming areas individually in the main scanning direction, regard the grouped images as one block, and designate which part of the transfer paper the block is to be arranged. is there. This designation can be made by pressing any of the buttons 779, 780, 781, 782, 783, 784, 785, 786, or 789.

If this designation is not made, the default value is "center left" and the display 782a is turned on.

The input of the trimming area is performed using the area buttons 790, 791 and 10 on the digitizer tablet (DG) 900 or CU750.
Input is performed using key buttons 816-0 to 816-9 and enter button 808.

In this example, the operator places a document on the DG900 and inputs a point of each region and a break of the region using a pen (not shown).

 That is, press P1, P2, P3, P4, P5 for the first area, and P7, P8 for the second area, and P11, P12, and the first area for the first area.

As described above, x (main scanning) and y (sub scanning) of each area
Coordinate values are input to SCON700.

Note that the inputs of P6, P9, P10, P13, and P14 are unnecessary because the SCON700 automatically calculates them.

Next, the operation will be described with reference to FIGS. 2 to 8 and FIG. This operation is roughly divided into two processes.

First, from the input coordinate values of the trimming area,
This is a process in which the SCON 700 calculates and calculates data necessary for control, sets the data in the RAM 713 that is its own data area, and transmits and sets data to other units.

Second, the original image data read by SC100 is transferred to IP200
According to the separation processing of blanking or passing the original image data as it is for a plurality of trimming areas, that is, performing a trimming process, and moving each of the trimmed plurality of trimming areas in a predetermined direction in the main scanning direction, This is a process of outputting image data to the PR 600 via the MU 400 and obtaining a print.

--- First process-- (1) First, SCON700 calculates the x and y of the input trimming area.
It is detected from the coordinate values whether the input is a polygonal shape and each side is not parallel or perpendicular to the main scanning line. If not parallel or perpendicular, the input coordinate values are corrected so as to be such.

(2) Next, a line segment in the y-direction (sub-scanning direction) is detected.

This line segment is a vector and the starting point is the one with the smaller value of y,
The larger one is called the end point, and the start point is to sort the end points in ascending order from the smaller one.

(3) Sorting x corresponding to the starting point in the sorted y in ascending order from the smallest, and 2 as shown below.
Create a dimensional array table.

Here, G = effective main scanning length × a value larger than 16 Y _X = original y dimension (mm) × 16 X _XX = original x dimension (mm) × 16/2 Y1, X11, X12, G Y2, X21, X22, G Y3, G Y4, X41, X42, G Y5, G Y6, X61, X62, G Y7, G (4) Next, on the memory map of the RAM 224 shown in FIG. Write data.

Note that this is a case where the transfer paper is set to the left in the main scanning direction, and the value of Xx2 is written in Dsfx when the transfer paper is set to the right. The procedure for writing to the RAM 224 is performed at the timing shown in FIG.

(5) On the other hand, the SCON 700 sorts and stores a predetermined address of the internal RAM 712 by multiplying the start and end points of the line segments in the sub-scanning direction of the entire trimming area by 16 in ascending order from the smaller value. .

--- Second Course-- The second course starts immediately after the operator presses the start button 813, and basically operates almost in the same manner as in the above-described basic copy mode. The only difference, however, is that the A9 to A5 signals for IP200 change during image processing.

The above change occurs in relation to the start or end position of the trimming area in the sub-scanning direction.

The original image scanning position in the sub-scanning direction is determined by SYS-SYS, a software counter in SCON700, which is cleared immediately before the start of scanning.
Since L-CTR is incremented every LSYNC pulse,
You can tell by monitoring this. The reason for changing the signals A9 to A5 is to control the read addressing of the RAM 224 set in the first process.

The timing of the above signal control will be described with reference to FIG.

From the start of image reading, the main scanning shift processing stage of the block 202 in the IP 200, that is, the toggle buffer memory 263r,
g, b or 266r, g, b
11, when the value of SYS-L-CTR-n11 reaches the sub-scanning start or end position of the trimming area, that is, in this case, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 At the time when the value matches the upper 5 bits of the address at which the corresponding trimming area data is stored in the RAM 224, that is, A9 to A5 are output so that the data can be accessed.

In particular, Is output in binary.

As described above, at least for the trimming area, the image data is passed to the next stage and the area outside the specified range is blanked, and the shift corresponding to each trimming area is performed with the value of Dsfx.

By executing the second process as described above, a desired print can be obtained.

 The above operation will be further supplementarily described.

When the reading operation of the SC 100 and the image processing operation by the IP 200 are started, when the number of VCLKs after the first LSYNC reaches 4871, as shown in FIG. 6, the lower order of the address of the RAM 224 is set as the preset value of the RD-CTR 251. Data with 5 bits equal to 0,
That is, Dsfx is loaded. This load operation is performed for each LSYNC pulse, but since the upper 5 bits of the addressing of the RAM 224 differ depending on the trimming area, the value loaded to the RD-CTR 251 also changes each time.

The value loaded to the RD-CTR 251 acts as a read start address of the toggle buffer memory 263r, g, b or 266r, g, b after the next LSYNC, that is, performs a shift operation. The shift to the left or right can be designated by controlling the LEFT / ▲ ▼ signals. In this example, 1 is set, that is, left shift is designated.

On the other hand, the lower 5 bits (A4 to A0) of the RAM 224 are not 0,
That is, data of 1 to 31H (H is a hexadecimal number) is used for the trimming operation in the main scanning direction. The same data is accessed only by the upper 5 bits of the address of the RAM 224 (A9 to A9).
The fact that A5) operates with a delay corresponding to 3 LSYNC after being supplied from the SCON 700 has been described in the description of FIG. These data are used as the A-side input of the comparator 252, and the B-side input of the comparator 252 is connected to the output of the RD-CTR 251.

Therefore, when the two inputs match, the JK-FF253 is inverted and output as a SWITCH signal via the gate 260, and an action is performed as to whether or not to output the image signal of each color to the next MU400.
C, M, Y, BK-transmitted to GATE207C, M, Y, BK.

Since the 5-bit counter 222 is incremented each time the comparator 252 outputs 1 from the coincidence output OUT terminal, the address of the RAM 224 is increased by one. That is, the comparator 252 outputs the trimming data Dswx−1, Dswx−
Each time they match, different data is sequentially compared with the RD-CTR 251 such as 2, Dswx-3,.... In this example, the coincidence signal 1 is output twice in a main scanning line including a portion where a trimmed image is to be left, and never output in a main scanning line to be blanked. Note that the in / out signal is kept at 0 during image processing.

FIG. 27 shows the relationship between the original and the copy in the case of this example.

In the above example, the example in which the main scanning direction is set to the left end of each trimming area on the left side of the transfer paper has been described.However, for each trimming area, the value of Dsfx can be set arbitrarily and LEFT / ▲ ▼ Since the signal can be changed freely, any direction and amount of movement can be freely selected. Therefore, it is possible to freely assemble to the center or right side.

[Effect] As described above, the present invention provides an image forming apparatus that forms an image by passing through a recording medium, an input unit that inputs image data, a memory that stores the image data, and an input unit that is input from the input unit. Designating means for designating a plurality of trimming areas for an image composed of image data, and performing a trimming process on the image data stored in the memory and corresponding to the plurality of designated areas, and the recording medium And control means for moving each of them so as to coincide with a predetermined position in the main scanning direction, which is a direction perpendicular to the passing direction of.

With such a configuration, when there are a plurality of trimming regions of a specific portion, each trimming region is adjusted so that one end or the center position of each of the plurality of trimming regions in the main scanning direction is set to a predetermined fixed position in the main scanning direction. It is possible to provide an image forming apparatus capable of forming images on a recording medium in which areas are individually moved in the main scanning direction.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing the overall configuration of a digital color copying machine to which one embodiment of the present invention is applied, and FIGS. 2 (a), (b),
2 (c), 2 (d) and 2 (e) show system block diagrams of the copying machine shown in FIG. 1, FIG. 2 (a) is a combined diagram of FIGS. 2 (b), 2 (c) and 2 (d). , (E) are partial views, FIG. 2 (f) is an explanatory diagram showing how to call a gate, FIG. 3 is a circuit diagram of an image processor IP, FIG. (B) and (c) are partial views, FIG. 4 is an explanatory diagram of address data of RAM 224, FIG. 5 is a write cycle timing diagram of RAM 224, FIG. 6 is an operation timing diagram of image processor IP, FIG. The figure is a circuit diagram for explaining the circuit block 207c, and FIGS. 8 (a), (b), (c), (d) and (e).
Is a block circuit diagram of the memory unit 400;
Figure (a) is a drawing combination diagram, and Figures (b), (c), (d),
(E) is a partial view, FIG. 9 is a circuit diagram showing a RAM, and FIG.
FIG. 11, FIG. 11, FIG. 12 and FIG. 13 are operation timing diagrams of the RAM of FIG. 9, FIG. 14 is a timing diagram showing the timing of the memory, FIG. FIG. 16 is an explanatory diagram for explaining the relationship between the output of the comparator and the counter, FIG. 17 is a circuit diagram showing the configuration of the counter,
FIG. 18 is a timing chart showing the addressing timing in the memory mode 2, FIG. 19 is a timing chart showing the addressing timing in the memory mode 3, FIG. 20 is a timing chart of the CMPSD data and the DSHIFT pulse, and FIG. FIG. 21 is a detailed view of a laser scanning system of the cyan color recording apparatus, FIG. 22 is a timing diagram of a print cycle, FIG. 23 is a block diagram of a console unit, FIG. FIG. 25 (a),
(B) and (c) are timing diagrams of the basic copy mode.
(A) is a drawing combination diagram, (b) and (c) are partial views, and FIG.
FIGS. (A), (b) and (c) are timing diagrams of the high-speed copy mode, (a) is a drawing combination diagram, (b) and (c) are partial views, and FIGS. 27 (a) and (b). () Is an explanatory diagram showing the relationship between a document and a copy. SC100: Original image reading means, IP200: Trimming means (shift means), RP600: Recording means.

Claims (2)

(57) [Claims] 1. An image forming apparatus for forming an image by passing through a recording medium, an input unit for inputting image data, a memory for storing the image data, and an image comprising image data input from the input unit. A designation unit for designating a plurality of trimming areas; and performing trimming processing on image data stored in the memory and corresponding to the plurality of designated areas, respectively, and perpendicular to a passing direction of the recording medium. An image forming apparatus comprising: a control unit configured to move each unit so as to match a predetermined position in a main scanning direction. 2. An image forming apparatus according to claim 1, further comprising setting means for changing said predetermined position.