JP2950829B2 - Digital color image forming device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus in which an original image is color-separated and read two-dimensionally in pixel units, and image processing is performed digitally. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus that enables editing and is applicable to a digital color copying machine that forms an image processed on a recording medium.

(Prior art)

To reproduce the same image repeatedly in the main scanning direction and the sub-scanning direction, a so-called dedicated frame memory is provided, and it is easy to analogize that it is sufficient to circulate two-dimensionally from this memory and output it to the image forming means. However, this method increases the cost. Further, in the color image forming apparatus, the original image is read after being decomposed into a plurality of color components, an image signal corresponding to the original image is stored in a memory, and the stored data is stored in, for example, cyan, magenta, yellow, and black. A color image is output from the memory with different delay times to the image forming station and overwritten on the recording paper to form a color image. As described above, the same desired color image is repeatedly formed on the recording paper. Therefore, if a dedicated frame memory is provided separately from the memory, a color shift occurs when a signal timing shift occurs between the memory and the dedicated frame memory, thereby deteriorating image quality.
Further, when the memory and the dedicated frame memory are separately provided, there is a drawback that signal processing takes a long time and a color image generation speed is reduced.

〔Purpose〕

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate such a conventional drawback, and an object of the present invention is to reduce the cost of at least a part of an original image without adding or expanding a memory device to an arbitrary magnification. Accordingly, it is an object of the present invention to provide an image forming apparatus capable of forming an image repeatedly arranged in a two-dimensional direction of a main scanning direction and a sub-scanning direction, that is, an image arranged in a matrix on a recording medium.

〔Constitution〕

The present invention achieves the above object by scanning an original image in a main scanning direction and a sub-scanning direction and reading the original image after being separated into a plurality of color components, for example, an original image reading means such as a scanner unit, and an image on a recording medium. A plurality of, for example, a photosensitive drum, a developing unit, a transfer belt, an image forming station comprising a pair of transfer corotrons and the like provided at predetermined intervals along the transport direction of the recording medium, An image signal corresponding to an original image read by the original image reading means, delayed by each image forming station except one of the image forming stations by a time corresponding to the interval between the image forming stations. In a digital color image forming apparatus having a delay memory and a memory control means for controlling the delay memory, the same image is repeated on the recording medium. A repeat mode designating means for designating a repeat mode to be output is provided, and when the repeat mode is designated by the repeat mode designating means, at least a part of the original image to be repeated in the delay memory is main-scanned. Direction and the sub-scanning direction, and changing the readout time of the storage data stored in the delay memory by the memory control means in accordance with the image formation station to which the storage data is output. And at least a part of the original image is repeatedly formed on the recording medium in at least one of the main scanning direction and the sub-scanning direction.

Hereinafter, a specific description will be given based on an embodiment of the present invention.

FIG. 1 is a block diagram of a digital color copying machine for explaining one embodiment of the present invention. 100 is a scanner unit (hereinafter referred to as SC), 200 is an image processor (hereinafter I)
P), 400 is a memory unit (hereinafter referred to as MU), 600 is a printer unit (hereinafter referred to as PU), 7
00 is a system controller (hereinafter referred to as SCON), 75
0 is a console unit (hereinafter referred to as CU), 900 is a digitizer tablet (hereinafter referred to as DG), 950 is a sorter unit (hereinafter referred to as ST), and 980 is an ADF unit (hereinafter referred to as AD).

2 (a) is a system block diagram of the digital color copying machine shown in FIG. 1, FIG. 2 (b) is a drawing connection diagram, and FIGS. 2 (c) to (f) are partial views. . The same reference numerals as those in FIG. 1 correspond to the same parts.

1 and 2, C indicates cyan, M indicates magenta, Y indicates yellow, R indicates red, G indicates green, B indicates blue, and BK indicates black.

In FIG. 2, the logic circuit is treated as positive logic, and a high voltage is High or 1 and a low voltage is Low or 0.
Described as As shown in FIG. 2 (g), A is a NAND gate, B is a NOR gate, C is an AND gate, D is an OR gate, E is a simple gate,
Then, F is the exclusive OR XOR.

First, among the configurations of the present invention, the SC100, IP200, MU400, PR600, SCON700, and CU750, which are the main parts,
The outline of those operations will be described.

(1) System Controller (SCON) 700 This is a computer that performs overall control of the digital color copying machine system of the present invention and is a stored program type computer.

 For example, each element can be configured as follows.

CPU704 Intel 8086 RAM712 Nidec Corporation µPD43256 × 4 (128KBYTE) ROM (PROM) 713 Intel27512 × 10 (640KBYTE) Interrupt controller 710 Intel8259 × 3 cascade connection (22 inputs) Timer / Counter 711 @ Intel8254 x 3 (9 timers /
Counter) Printer interface 703 ‥‥ Intel8255 (MODE2)
(Parallel type) Scanner interface 709 ‥‥ Same as above Console interface 708 ‥‥ Intel 8251 (serial communication type I / O) Image processing sign tough 701 ‥‥ Intel 8255
(MODE0) x 3 Memory unit interface 702 ‥ Intel 8255 Digitizer tablet interface 707 825 Intel 8251
(Serial communication type I / O) Sorter interface 706 (same as above) ADF interface 705 (same as above) There are clock generators, control signal decoders, etc., but they are omitted.

(1-1) SC100 interface Physically, there are 8-bit bidirectional data lines and several control lines.

The instruction for SC is called SC command, At the time of data reception and data transmission completion, a signal is automatically input to the interrupt controller 710, and an interrupt service routine is automatically executed.

(1-2) PR600 interface Physically the same as SCI / F.

PR commands include: (1-3) Interface to IP200 This interface is for output only.

γ _{0 to} γ ₂設定 Set the γ characteristics (density characteristics) of the copy for the original (group 8) MIRROR1 指示 Instruction to create a mirror image copy in the main scanning direction SWAP1 を Change the image in the main scanning direction Instructions to create LEFT / ▲ ▼ ‥‥ Direction of creation of moving image copy in main scanning direction INVERSE ‥‥ Instruction of creation of density inversion copy OUT / ▲ ▼ ‥‥ Area processing (blanking, partial color conversion, partial image quality process selection) for instruction a ₅ to a ₉ ‥‥ region processing inside or outside of the upper address of the image movement RAM 5bi
data D for t, and the address comparator ₀ to D ₁₁ ‥‥ region processing, data of the image movement RAM (12bit) ▲ ▼ ‥‥ region processing, Chitsupuserekuto (enable) CLR ‥‥ domain processing of image movement for RAM, image movement Clear the lower 6-bit address counter of RAM for use and clear pulse of RAM address counter for scaling ▲ ▼ ‥‥ Write pulse for the above two types of RAM ALL ‥‥ Instruction not to perform area processing (when applied to the entire surface) CH _{GCO 5}内容 Color conversion instruction UCR ‥‥ UCR (UNDER-COLOR-REMOVAL: under color removal) instruction MAX ‥‥ Complementary color generation, C, M, Y signal after color correction Among them, extract the signal corresponding to the one with the highest density and send the signal to all C, M, Y, BK signal lines (for the next step of IP200, which will be described later). data of use RAM of Chitsupuserekuto (enable) ZD ₀ ~ ₁₁ ‥‥ zooming RAM (12bit) CKIND ₀ ~ ‥‥ quality processing, send instruction whether BKGATE ‥‥ stroll Send whether instruction YGATE ‥‥ yellow or send an indication of whether MGATE ‥‥ magenta send Eight selected CGATE ‥‥ cyan data (1-4) Interface to MU400 This interface is for output only.

SYMMETRY2 ‥‥ Used when making a target copy in the sub-scanning direction.

MIRROR2 ‥‥ Used when making a mirror image copy in the sub-scanning direction.

SWAP2 ‥‥ Used when making a replacement copy in the sub-scanning direction.

COMPSD ‥‥ Serial data of the input data registers of the three sets of 24-bit comparators inside the MU DSHIFT ‥‥ Shift pulse of the above register (shift register) MMODE1 ‥‥ To operate the MU in normal FIFO (first in, first out) mode Instruction for operating MMODE2 @ MU in write mode Instruction for operating MMODE3 @ MU in read mode Used to reset the address counter of the memory of MSTART @ MU.

Instruction to enable / disable counting up of address counter of VDENA @ MU memory (1-5) Interface to CU750 <Input> Imports key-in information of various keyboards, CU
When receiving data from the 750, the serial communication type I / O port
Since 708 generates an interrupt signal to 710, it is possible to quickly cope with a change in information of the CU 750.

<Output> Outputs data to be displayed on the console.

(1-6) Interface with DG900 <Input> Import XY coordinate data.

<Output> Sends buzzer and display lamp data.

I / O port 707 is an asynchronous serial communication system.
At the time of transmission, an interrupt signal is generated for 710.

(2) Referring to Sukiyanayunitsuto (SC) 100 First Figure 1, the document 1 is a platen placed on the (contact glass) 2, a document illumination fluorescent lamp 3 _1, 3 ₂
1st mirror which is illuminated by and whose reflected light can move
4 _1, is reflected by the second mirror 4, _second and third mirror 4 _3, through the imaging lens 5 enters the dichroic prism 6, wherein three wavelengths of light,-intensity (R), green (G) and It is split into blue (B). The split light enters the CCDs 7r, 7g, and 7b, which are solid-state imaging devices, respectively. That is, the red light is incident on the CCD 7r, the green light is incident on the CCD 7g, and the blue light is incident on the CCD 7b.

Fluorescent lamp 3 _1, 3 ₂ and the first mirror 4 ₁ is mounted on the first carriage 8, the second mirror 4 ₂ and the third mirror 4 ₃ is mounted on the second carriage 9, a second carriage 9 is first carriage 8 of
By moving at half speed, the optical path length from the document 1 to the CCD is kept constant, and the first and second carriages are scanned from right to left when reading the original image. Carriage drive pulley 11 fixed to the shaft of carriage drive motor 10
The first carriage 8 is connected to a carriage driving wire 12 wound around the vehicle, and the wire 12 is wound around a moving pulley (not shown) on the second carriage 9. Thus, the first carriage 8 and the second carriage move forward (original image reading scan) and return (return or forward direction original image reading scan) by forward and reverse rotation of the motor 10, and the second carriage 9 moves to the first carriage.
It moves at half the speed of the carriage 8.

When the first carriage 8 is at the home position shown in FIG. 1, the first carriage 8 is detected by a home position sensor 39 which is a reflection type photo sensor. When the first carriage 8 is driven to the right in the exposure scan and deviates from the home position, the sensor 39 does not receive light (carriage is not detected). When the first carriage 8 returns to the home position by return, the sensor 39 returns to the home position. Light reception (carriage detection) occurs, and the carriage 8 is stopped when the state changes from non-light reception to light reception.

Referring now to FIG. 2, the outputs of the CCDs 7r, 7g, and 7b are converted to 8-bit digital values by the A / D converters 102r, 102g, and 102b, that is, 256-level density signals.
It will be sent as a signal. Its value is 255 in white,
0 for black.

The control of the SC 100 is performed by the scanner controller 101.

The scanner controller 101 includes a CCD driver, a motor driver,
It is composed of those including various sensor input ports and SCON700 I / F.

(3) Image processor (IP) 200 ・ Block 201 γ-correction processing (γ-Compensation) The gradation of the original and the copy is linear according to the characteristics of the read density gradation of SC and the print density gradation of PR. A correction process is performed so that

γ conversion processing (γ-Change) Processing for creating a copy having a γ characteristic different from that of the original, for example, a copy in which highlights are emphasized, a high contrast copy, or the like is performed.

Is one of the eight special γ characteristics, including the 3 bit signal from SCON, and the next block
R, G and B are output in 8 bits each.

Block 202 (see FIG. 3 for details) Mirroring 1 (MIRROR1) When the MIRROR1 signal from SCON is high, the arrangement of pixel data in the main scanning direction is inverted and output.

Swap 1 (SWAP1) The SWAP1 signal from SCON is high and the RAM shown in FIG.
224 loaded with appropriate data and LSY while scanning
When A ₆ to A ₁₁ in accordance with the count value of the NC is given from SCON, replacement of the main scanning direction of the image.

Shift Part 1 RAM 224 to the appropriate data are loaded in advance, and when A ₆ to A ₁₁ in synchronization with the count value of LSYNC during scanning is given from the SCON, image positions of the same amount or a sub-scanning direction on the entire surface Are moved in different amounts. Movement direction is from SCON
Determined by LEFT / ▲ ▼ signal High / Low.

Appropriate data SWITCH output RAM224 are preloaded, and when A ₆ to A ₁₁ in synchronization with the count value of LSYNC during scanning is given from the SCON, block 202 High a SWITCH signal, Low
Output alternately.

This output is output to blocks 207C, M, Y, and BK for blanking part of the image (trimming processing), block 206 for partially changing the image quality processing, and partial color conversion. Is output to block 203.

Inverse (inversion) When the INVERSE signal from SCON is high, each bit of R, G, B 8 bits is inverted and output. The copy is therefore a negative image.

Next, a detailed description of the block 202 will be described with reference to FIGS.
This will be described with reference to FIGS. 5 and 6.

FIG. 3 is a circuit diagram of the image processor IP,
(A) is a drawing combination diagram, and (b) and (c) are partial views.

Two sets of RAM for each color (263r, g, b and 266r,
g, b). These RAMs are used as toggle buffer memories. When one set is taking in image data (writing to memory: memory write), one set is exposing data (reading memory: reading memory). . Switching between read and write is performed by JKFF every 1 LSYNC.
This is done by reversing 262.

FIG. 6 is an operation timing chart of the image processor IP. Assuming that the Q output of 262 goes high at the first LSYNC, one input of the OR gate 234 goes low, and VCLK (pulse generated by FIG. This pulse is also LSYN because there are 4752 pixels
4752 are generated between C and the next LSYNC. When the rising portion of the pulse (at the middle position of one pixel data) rises, a rising pulse is applied to the ▲ ▼ terminals of RAM 266r, RAM 266g and RAM 266, and the pixel data is written. The address at this time is the memory write counter (WR-
(CTR) 252.

Since the VCLK is also input to the CLK of the counter 252, the image data is sequentially written in the higher address direction.

On the other hand, in the RAMs 263r, 263g, and 263b, since one input of the OR gate 233 is High, the symbol ▼ is not active. Instead, if one of the three inputs of the NAND gate 264 connected to the output of the OR gate 259 is high, the input becomes low and the output is enabled, that is, the memory read is performed. Note that MM3 (248) is a retriggerable monomultivibrator whose output pulse width is set slightly longer than the cycle of VCLK. Therefore, as shown in FIG. 6, high output is continuously performed during generation of VCLK. .

Also, at this time, since the inputs of the bus drivers 268r, 268g, and 268b are high, the output is in a high impedance state,
The A input side is selected for the multiplexers 269r, g, and b.
The data is output to the next block 203 via R gates 230 ₀ r, g, b to 230 ₇ r, g, b.

The XOR gate is for inverting data when the INVERSE signal input is high, that is, for performing negative / positive inversion.

A memory read counter (RD-CTR) 251 is a presettable UP / DOWN counter, and can set the start of addressing and the addressing direction arbitrarily. Note that 250 and 261 are multiplexers for switching the address input of each RAM. A is output when the A / B input is high, and B when the A / B input is low. When the output of JKFF262 is inverted at the next LSYNC, RAM262r,
g and b operate in the read mode, and the RAMs 263r, g and b enter the write mode. Hereinafter, this repetition is performed.

 Next, the RAM 224 and its related configuration will be described.

RAM224 consists of 1024 words (WORD) x 12bit, 32W
One set that uses ORD as one set and 32 sets is composed of RD-CTR251 preset data (1 word) and “SWITCH” output switching comparison data of 31W.
ORD can be set.

FIG. 4 is an explanatory diagram of the address data of the RAM 224.
Here, DSFx is for the preset of RD-CTR251, and DSWx- ₁ to ₃₁
Is the data for SWITCH.

FIG. 5 is a write cycle timing chart of the RAM 224. Data write to the RAM 224 is performed as shown in FIG. Although higher address 5bit (A9～A5) is carried out at the input than SCON, lower 5bit counter 222 1 ▲ ▼ pulse is incremented (from the SCON) each, since the next 11111 _B becomes 00000 _B, Does not require input from SCON.

Also, when it is not necessary to write all data,
For example Dsf _{1, Dsw-1,} write the Dsw1-2, Dsw1-3~Ds
When w1-31 is not required, CLR prior to writing the next Dsf ₂
Is output from one pulse SCON, and the counter 222 needs to be cleared.

Note that 228,225 is a bus driver, 239 is a multiplexer, and when ▲ ▼ = Low, 228,225 can be output, 239 has high impedance, and outputs A _{9 to} A ₅ and D _{11 to} D ₀ signals from SCON. It can be correctly given to the RAM 224.

The writing to the RAM 224 is performed before the copy operation.

 Next, reading of the RAM 224 will be described.

Reading of the RAM is performed when image data is sent from the SC 100. This is shown in FIG.

At this time, CS1 and ▲ ▼ are kept High, and CLR is kept Low.

A _{9 to} A ₅ are sent from SCON at appropriate timing as upper addresses during memory read.

D ₁₁ to D ₀ is not a memory, for the one comparison input of the comparator 254, sent from SCON.

Also, it is assumed that DSWx _{-1 to} DSWx _-31 in the RAM 224 are stored from the lowest address to the lowest value.

A ₉ to A ₅ is a is appropriately provided from the previous LSYNC which valid image data is started is sent from the SC100.

237 is a shift register of four stages, the A ₉ to A ₅ of RAM 224, S
It is provided to provide A _{9 to} A ₅ data given by CON with a delay of three LSYNC values. Also, data that is not delayed is used. This selection is made by the multiplexer 239.

Reference numeral 249 denotes a 13-bit counter, which is counted up by a continuous pulse CLK0 (having the same cycle as VCLK).

When b ₁₂ , b ₉ , b _{8 of} this counter are all High, AND
The output of the gate 244 becomes High, and the Q output of the RSFF242 becomes High.
The multiplexer 239 has an A input, that is, A ₉ to A ₉ before delay.
₅ inputs are given to RAM224.

Then, the output b ₂ of the counter 249 becomes High RSFF242 is reset, the multiplexer 239 B side, i.e. 3LSYNC
The address data delayed by a minute is supplied to the RAM 224 again.

 Note that RSFF242 is also reset by LSYNC.

That is, it becomes a _{b 12, b 9, b 8} = High is, CLK0 is from LSYNC
4864 _{th, b 12, b 9, b} 8 = High, become a b ₂ = High is likewise 4871 th.

This value is set so as to be a value after the effective main traveling is completed.

Accordingly, in the valid image section, the RAM 224 is accessed with the address data delayed by 3 LSYNC, and the read data is input to the A input of the comparator 252. B input of the comparator is connected to the upper 12bit of _{RD-CTR251 (b 12 ~b 1} ). The comparator 252 outputs OUT = High only when the A and B inputs match.

Therefore, as long as the DSW data is not the same, the high output is performed only for 1 VCLK pulse. This output pulse is output to counter 22
It is also connected to the 2 CLK input, which is incremented.

The increment is also performed by LSYNC, and the clear is performed by Q = High of the RSFF242 described above.

Accordance connexion, A input of meaningful comparators lower address (A ₄ to A ₀₎ is not 0 in the RAM 224, is started from the first read data, every time the comparator 252 is a match output, increments the RAM addresses Will compare the new RAM data with the output of the WR-CTR 251.

The OUT terminal of the comparator 252 is also connected to the CLK input of the JKFF 253, and toggles the coincidence output every time it is output.

The output of this JKFF253 is sent to the SWITCH
The output is input to the OR gate 212 in FIG.

XOR gate 260 is simply for inverting the output of JKFF253.

Next, when the RSFF 242 outputs High, that is, when accessing the RAM 224 with the data before the delay of A _{9 to} A ₅ from SCON, the output of the AND gate 223 is High and the counter 222 is cleared, The lower 5 bits (A _{4 to} A ₀ ) are 0,
The head of each set in the figure, that is, the value of DSW _x is read.

During this output, next to LOAD input of the RD-CTR251 is High, the read data of the memory the upper 12bit of RD-CTR251 (i ₁₂ ~
i ₁ ).

In FIG. 6, the output of the counter 222 indicates the case where the comparator 252 outputs the coincidence signal four times.

Also, the output of the counter 251 with Dsf ₁ to ₆ is the RAM
The start address of the first to sixth sets in 224 is
This indicates that the counter 251 has been preset.

Image Pro Seth in service IP image processing, D ₁₁ to D ₀ is RAM22
Although it does not act on 4, the comparator 254 is effective as an A input, and one B input is connected to the output of RD-CTR. The comparator 254 outputs High only when A and B match. At this time, RSFF256 is set (Q is set to High), and RD-CTR251 is cleared.

The Q output of RSFF256 is output from the XOR gate 257 and OR gate 259
And input to the NAND gates 264 and 265. Therefore, when SWAP1 = High, and Q and LEFT / ▲ of RSFF256
▼ When only one of the inputs is high, the output of the RAM to be read (either 268r, g, b or 266r, g, b) is enabled, that is, the image data is output to the next block 203. . Not enabled (▲ ▼ input = High)
At this time, since the output of this RAM is high impedance, and therefore is pulled up, it is all High (= 255) and equal to white data.

FIG. 6 shows these operations in various cases.

Incidentally, the read of the RAM 224, to use a A ₉ to A ₅ of A ₉ to A ₅ and 3LSYNC after delay before the delay, the image data processed by the RD-CTR is, block 207C which blanking processing is performed, M, Y, B
There is a delay of 3LSYNC before being processed by K, and the S
This is because the WITCH output is used here. That is, this is to synchronize the image processing in the sub-scanning direction.

Block 203: Color change (Color Change) Converts any color signal of R, G, B to a specific level with a 6-bit signal of CCHG ₀ to ₅ from SCON700. That is, a print creation process of a color different from the original image is performed.

Block 204 Color correction processing Color reproduction of color copy is performed by reading the original with a scanner, separating the pixels with R (red), G (green), and B (blue), and compensating for the color signals of those signals, that is, R, Complementary color conversion to C (cyan), M (magenta), and Y (yellow) signals that independently absorbs G and B wavelengths, and adds BK (black) required for three colors or for undercolor removal described below This is achieved by printing with the four colors of toner and ink.

If dots of each color are printed in the same position and printed, each dot can be represented by subtractive color mixture, but it is also possible to print at different screen angles for each color to remove color moiré. Can be done. In this case, C, M, and Y, R, G, and B of the secondary color, and K in which three colors are overlapped in one pixel
It is well known that eight colors of paper W (White) appear at random, and the color reproduction in this case can be represented by a Neugebauer equation that predicts a mixed color state from a halftone dot area of each color.

However, the C, M, and Y color materials do not have ideal spectral reflection characteristics, and have components that absorb unnecessary colors called sub-absorptions. In this case, the color materials differ depending on how they overlap. The color will be reproduced.

Therefore, the toner and ink having this side absorption are simply referred to as R,
If it is used as it is as a complementary color of G and B, the color will be cloudy and the desired color will not be reproduced. So, in the color reproduction problem,
A so-called color correction process for removing the influence of the sub-absorption and performing color reproduction faithful to the original image is required.

The simplest color correction processing is linear masking using a 3 × 3 matrix. If Dr, Dg, and Db are R, G, and B densities, And the components of the coefficient matrix can be obtained from the spectral characteristics of the color material.

If this method does not provide sufficient correction, use Dr ² , Dr D
By performing non-linear masking in consideration of the secondary terms such as g, color reproduction with higher accuracy can be obtained. In this embodiment, non-linear masking is employed.

For the color correction in the block 204, in order to perform high-speed image signal processing, the correction calculation result is stored in advance as 8-bit data (each color) in the ROM, and the input data is connected to the address line (24 bits) of the ROM. There is a method of obtaining a result (reading a memory).

UCR (Under color removal) (Black printing) When black is reproduced with three colors of C, M, and Y, the lack of density occurs in high-density areas mainly due to surface reflection.

In order to prevent this problem, reduce the consumption of ink and toner, and reduce the fixing energy,
Removal of the gray component, that is, the same amount of C, M, and Y components from a certain color, or under color removal (UCR), and printing with black toner or ink equivalent to the removed gray. Or called BP (Black Print).

The UCR ratio can be selected arbitrarily, and if it is 100%,
There are advantages such as minimum consumption of toner.

When the UCR signal from SCON700 is High, 100% UCR processing is performed, and C, M, Y, and BK are output in 6 bits each.

When the UCR signal is low, no UCR processing is performed, and the output of BK becomes 0.

max (maximum density extraction, output) When the MAX signal from the SCON700 is High, the minimum value of the input R, G, B signals from the block 203, that is, the signal corresponding to the maximum density in the original image is extracted, and the complement of that value is extracted. 6 bits of C, M, Y, and BK are completely equal, and the next block 205
Output to At this time, the above-mentioned processes are stopped.

When the MAX signal is Low, the function stops, and
Works.

Block 205 scaling processing Before performing scaling processing (that is, before SC scanning), block 20
5 It is necessary to store the scaled data in the RAM for scaled data. This data is calculated by SCON700 according to the magnification (25% to 400%, 1% step), and the data is
With ▼ = Low, “ZD ₀ to ₁₁ values are output and ▲▲
This is achieved by repeating the cycle of “generating one pulse”. The amount of data stored in this way is 1W
ORD (= 12bit) × 400, image data C, M, Y each 6bit
Is automatically scaled and output to the next block 206.

Block 206 Eight kinds of filter processing dither processing are selected with 3-bit data (CKIND ₀ to ₂ ) from SCON700.

For example, when CKIND ₀ to ₂ = 0, the whole surface smoothing filter processing +64
Level dither processing.

CKIND ₀ when the ~ 2 _{= 8,} the halftone image portion and a character, a line drawing automatically separated halftone image portion smoothing filter processing +64 Reberudeiza process. For character and line drawing parts, sharpening filter processing +2
Perform level dither processing.

Filter processing Part 1: When sampling the original spatial frequency f ₀ of the moire removing processing halftone by dot document in a periodic pitch f _1, through Deizafuiruta frequency f _2, and outputs the printer of dots frequency f ₃ It will result in an _{f 0 -f 1, f 0 -f} 2 , etc. beats, i.e. moiré.

 A smoothing filter process for this is performed.

The filter of the embodiment is There is.

Part 2: Image sharpening (MTF correction) processing By subtracting a constant multiple of Laplacian ▽ ² f, which is the second derivative, from the number of original images f, an overshoot occurs on both shoulders of the eccentric edge, and sharpness, ie, MTF It is well known that is improved.

Laplacian filters typically include In this case, the differential operation is performed only in the X and Y directions, but blurring occurs in the rotation target, so if the calculation is performed in multiple directions by increasing the matrix size in 45 ° or even more, the more ideal result In this embodiment, a matrix size of 5 × 5 is used.

Dither processing The density gradation required for color copying is 64 gradations. However, with current recording techniques, such as electrophotography, thermal transfer, ink jet, etc., it is almost impossible to express this gradation in one dot, and at most several levels of gradation can be expressed by dot size or dot density modulation. Not just.

Therefore, in general, an area gradation method such as a density pattern method or a dither method is often used. The density pattern method corresponds to a plurality of output dots for one input data, and the dither method corresponds to one output dot for one input data.
The dither method, in which the number of gradations is the same, naturally provides a higher resolution.

In this embodiment, the dither method is adopted, and
It is used together with the 8-level modulation in the dot.

 This method is generally called a multi-value dither method.

In the dither method, the configuration of a threshold matrix plays an important role in tone reproducibility and resolution, and can be generally classified into the following two types.

a. Dot concentration type (Typical example Fatting type) b. Dot distributed type (Typical example Bayer type) Also, all thresholds in the threshold matrix are set to be the same,
Substantial binarization is also possible.

In the present embodiment, one of these various threshold matrices is selected in accordance with the CKIND ₀ to ₂ signals from the SCON700, and the input signals C, M, Y, and BK are each input to 6 bits, and the C, M, Y, and BK signals are input to 3 bits each. And output to the next block.

Blocks 207C, 207M, 207Y, 207BK Whether to pass image data to the unit 400 (MU) by combining the CGATE, MGATE, YGATE, BKGATE signals from SCON700, the AREA signal of block 202, and the ALL signal from SCON , No (equivalent to passing white data).

 This detailed circuit is shown in FIG.

 The values of the three bits of each color from the block 206 are as follows: 7: 1 pixel is the lowest (blank), 6 to 1: 1 is the intermediate density, and 0: 1 is the maximum density.

(4) Memory unit (MU) 400 FIG. 8 is a block diagram of the MU 400, (a) is a drawing connection diagram, (b) to (e) are partial views, and this memory unit is as follows. Has the functions of the following three modes.

Memory mode 1: The memory mode operates as a delay circuit that outputs C, M, and Y image data with a predetermined delay, and can be said to be a FIFO (First-In, First-Out) memory.

The amount of delay is from the BK photoreceptor 44BK of PR600 (Fig. 1).
It is delayed by a pixel corresponding to the length up to the C, M, Y photoconductors 44C, 44M, 44Y. Specifically, 110mm, 44
M data is 220 mm, up to 44Y is 330 mm, pixel density is 16 dots / mm, and effective image width in the main scanning direction is 297 mm. C data: 16 × 110 × 16 × 297 = 8,363,520 pixels M data: 16 x 220 x 16 x 297 = 16,727,040 pixels Y data: 16 x 330 x 16 x 297 = 25,090,560 pixels Each data from IP200 is delayed and output to PR600.

This mode operates when the MMODE1 signal from SCON is high.

Memory mode 2: Write C, M, Y data from IP200 to memory. At this time, data is not output to PR600 (it may be output). This mode operates when the MMODE2 signal from SCON is high.

Memory mode 3: Data stored in memory mode 2 is output to PR600. The M and Y data are delayed with respect to the C data and output with M: 8,363,520 pixels and Y: 16,727,040 pixels, respectively.

This mode operates when the MMODE3 signal from SCON700 is High.

Reference numerals 401 ₀ to _{14 in} FIG. 8 denote memory blocks, which are shown in FIG.
1,048,576 words × 1 bit RAM combined 12 pieces, 1,048,57
Operate as a 6 word x 12 bit RAM.

The operation timing chart of the 1MDRAM in FIG. 9 is shown in FIGS.
3 The meaning and time of the symbols shown in FIG. 13A are as shown in FIG. 13B.

The memory blocks of the MU 400 correspond to the three modes of the MU and one of the following.

Memory mode 1 → memory read / write cycle Memory mode 2 → memory write cycle Memory mode 3 → memory read cycle Other → memory refresh cycle Note that in memory mode → 1 to 3, memory blocks with ▲ ▼ input high Automatically perform a memory refresh cycle. The circuit for this refresh is omitted for the sake of simplicity. It is also omitted in the timing chart (FIG. 27).

These memory control signals are provided by the timing signal generator 40
6 (FIG. 8) or a combination of other signals. This is shown in FIG.

This figure explains the timing of the memory, and the mode is not switched at such a short interval when a copy is made.

CLK0 is a continuous pulse with a frequency equal to the input speed of one pixel, generated by the control signal generator 211 in IP200.
Supplied to MU400. The frequency is 7MHz.

Outputs of timing generator 406 ▲ ▼, ▲ ▼,
ROM / ▲ ▼, WR1 and LOAD are continuous waves having a frequency of 1/4 of CLK0, and the duty and phase of High and Low are different from each other as shown in FIG. Address clock ACLK is also 1/4 of CLK0
Although it is a pulse with a period, it is 1/4 (1
A pulse of 6 x 297 mm = 4752 pixels / 4) is generated continuously.
It stays low until the next LSYNC is input.
The repetition of generating pulses is performed.

This is shown in FIG. FIG. 14 shows a state in which the ACLK is continuously generated.

Although the OE (output enable) of the decoders 1 to 3 (417 ₁ to ₃ ) is complicated in an actual circuit, any one of MMODE1, MMODE2, and MMODE3 is set to High in order to simplify the description. , It is assumed that the OE input becomes High.

<Refresh> When MMODE1 to MMODE3 are all Low, decoders 1 to 3
Outputs ▲ ▼ to ▲ ▼ of 3 (417 ₁ to ₃ ) are all Hi
gh. Accordingly, the outputs of the OR gates 408 ₀ to ₁₄ become High, and all the inputs of the memory blocks 401 ₀ to ₁₄ ▲ ▼ are High.
Since only ▲ ▼ is input, the refresh cycle shown in FIG. 13 is started.

<Read / Write> When MMODE1 input is High, decoder 1 (417 ₁ )
Any of ▼ to ▲ ▼ is Low output. In the decoder 2 (417 ₂ ), any one of ▼ to ▼ becomes Low output. Decoder 3 (417 ₃ ) is ▲ ▼ ~
One of ▲ ▼ becomes Low, ▲ ▼, ▲
It is assumed that ▼ does not become Low (the reason will be described later). Then, one Lo of the decoder 3 (417 ₃ )
w One of OR gates 408 ₁₂ to ₁₄ corresponding to output ▲ ▼
One outputs Low when the ▲ ▼ output of the timing signal generator 406 outputs a Low, Memoriburotsuku MB ₁₂ ~ ₁₄
In any one of (401 ₁₂ to ₁₄ ), a low pulse is input as shown in FIG. Since the ▲ inputs of the remaining two blocks remain High, they remain in the refresh cycle. Similarly,
Low output ▲ ▼ of decoder 2 is MB _{7 to} MB ₁₁ (401 ₇ to ₁₁ )
Is activated, and the remaining 4 blocks are not activated.

The low output CS of the decoder 1 (417 ₁ ) is connected to the OR gates 408 ₀ to ₄ , 4
One of the terminals 12,413 is set to Low input and OR gate 4
08 When Low is input to ₀ to ₄ , one of MB _{0 to} MB ₄ is ORed
When input to gate 412 or 413, inverter 439
Input High, Output Low. Therefore, AND gate 410 or 411
Output and Low, because eventually the Low at one terminal of the OR gate 408 ₅ or 408 ₆ is input, MB ₅ or MB ₆ is Akuteibu,
That is, only one of MB _{0 to} MB ₆ becomes ▲ = Low, becomes active, and the remaining six blocks remain inactive.

Multiplexer 2 (MPX2: 409) has SEL input = Hig
When h, X _{0 to} X ₁₁ are output to Z _{0 to} Z ₁₁ , and when SEL input is Low, Y ₀ to Y
₁₁ is output. When MMODE1 = High, the X side is selected,
MB ₅ and MB ₆ are addressed to the output value of the address counter 1 (421 ₁ ).

On the other hand, the output of AND gate 408 is the same as WR1 output of 406, the output of NOR gate 407 becomes an inversion of this, a pulse of "memory ▲ ▼" in FIG. 10 is Memoriburotsuku MB ₀ to 14 ▲ ▼ terminal.

In addition, Low / ▲ of the timing signal generator 406
▼ output, MPX3 (418), MPX4 ( 419), becomes the SEL input of MPX5 (420), SEL = when the High X ₀ ~ ₉ side is output, Y ₀ ~ ₉ side when SEL = Low is outputted Will be.
Accordingly, the lower 10 address counters ₁ to ₃ (421 ₁ to ₃ )
bit is input as the low address of each memory block,
The upper 10 bits are input as a COLUMN address.

▲ ▼, ▲ ▼, ▲
The operation timing of ▼, A _{0 to} A ₉ coincides with the “read / write cycle” shown in FIG. 10, and the data existing in the RAM up to that time is output to DO ₀ to ₁₁ and Di ₀ to ₁₁ Will be written (stored) with the new data.

When <write> MMODE2 is High, ▲ ▼ output of the decoder 1-3 (417 _1-3), ▲ ▼ _{0 ~} ▲ ▼ only any one Low next _4, 417 ₁ of CS5, CS6 is a Low (This situation will be described later).

The output of decoder 1 (417 ₁ ) activates one of MB _{0 to} MB ₄ , and the output of decoder 2 (417 ₂ ) outputs MB _{7 to} MB ₁₁
And one of the Akuteibu, the output of the decoder 3 (417 _3), the one of the _{MB 5, MB 6, MB 12} ~MB 14 to Akuteibu.

Also, one of the inputs of the NOR gate 407 is always High, that is,
Since the output is always Low, ▲ ▼ of MB _{0 to} MB ₁₄
The input is always Low.

Incidentally, MB _5, MB address inputs A ₀ to A ₉ in _6, PMX2 of (409)
Since the SEL input is low, address counter 3 (421 ₃ )
The value of the output of is input.

▲ ▼, ▲ ▼, ▲
▼, operation timing of the A ₀ to A ₉ are consistent with the "write cycle" in FIG. 11, the output DO ₀ to DO ₁₁ remains in a high impedance, the data applied to the input terminal Di ₀ -DI ₉ Will write.

<Read> When the MMODE3 input is High (MMODE1 and 2 are Low), the two inputs of the NOR gate 407 are both Low and the output is High. Therefore, the ▲ ▼ inputs of MB _{0 to} MB ₁₄ become High.

 Others are the same as the case of <lead>.

In this case, ▲ ▼, ▲ ▼, ▲
The timings of ▼, A _{0 to} A ₉ coincide with the “read cycle” in FIG. 12, so that new data is not input (written) and the data stored so far is output to the output terminals DO _{0 to} DO 9.
₁₁ will be output.

The inputs of A _{0 to} A ₉ of MB ₅ and MB ₆ are given by the output value of address counter 1 (421 ₁ ) in MMODE1 (read / write mode), and in MMODE2 (write mode) and MMODE3 (read mode). In the same manner as given by the output value of the address counter 3 (421 ₃ ), the input data Di ₀ to ₁₁ and the output data DO ₀ to _{11 of} MB ₅ and MB ₆ are also switched in the mode. Input data switching is MPX1 (403), output is demultiplexer D
Can be switched with MPX (404).

MPX1 (403) outputs an input on the X side when SEL = High. When SEL = Low, Y side input is output. DMPX
(404) is output to A side when SEL = High, and B side becomes high impedance. When SEL = Low, output to B side,
The A side becomes high impedance.

Also, 402 _Y , _M , _C are serial / parallel converters, 3 bit
× 4 data is converted to 12-bit data.

405 _Y , _M , _C are parallel / serial converters, 12 bit
The data is converted to 3 bits × 4 data. That is, these converters, which perform the exact opposite operation of 402 _Y , _M , _C , are only needed to lower the operating frequency of memories and memory control circuits.

MPX1 (403), since each SEL input of DMPX (404) is are directly connected to MMODE1 line, after all, when the MMODE1 = High, the input data of MB _{5, 6} is Y (yellow) data, MB ₅ , ₆ are also output as Y data, and when MMODE2 = High, the input data of MBs ₅ , ₆ is CDi ₀ which is C (cyan) data.
₃ are written and when MMODE3 = High, the data is stored in MBs ₅ and ₆ and the data is stored as C data in CD ₀₀
~ ₂ .

<Memory addressing in memory mode 1> At this time, SYMETRY2 = Low MIRROR2 = Low SWAP2 = Low MMODE1 = High MMODE2 = Low MMODE3 = Low VDENA = High is maintained during operation.

Then, the value of the data setting SW1 (416 ₁ ) = 16 × 330 × 16 × 297 × 1/4 = 6,272,640 The value of the data setting SW2 (416 ₂ ) = 16 × 220 × 16 × 297 × 1/4 = 4,181769 The value of the data setting SW3 (416 ₃ ) is set to 16 × 110 × 16 × 297 × 1/4 = 2,090880.

One MSTART pulse is included and all counters ₁ to ₃ (42
1 ₁ to ₃ ) are all cleared, and ACLK is supplied from the timing signal generator 406 to the CLK terminal at some gates (438,44).
1), after ACLK is added, it is incremented one by one.
Via 18,419,420, the Lo of each memory block
Join the w, COLUMN address.

On the other hand, the output of the upper 4 bits of the counters 1 to 3 is
417 Input to ₁ to ₃ and decode signal also ▲ ▼ ₀ to ▲
▼ Output to ₆ . ▲ ▼ output switches 2
²⁰ = 10,48,576 units.

On the other hand, the output of the counter _1-3, comparators 415 ₁ -
₃ is connected to the A input side and respectively match the data setting SW ₁ ~ _3, it outputs 0 outputs High. This output AND gates 426 ₁ ~ _3, OR gates 428 ₁ ~ _3, AND gates 423 ₁
To _3, OR gates 431 _1-3, a monostable multivibrator MM _1-3
Via (430 ₁ to ₃ ), set the CLR terminal of each counter ₁ to ₃ to High for a very short time and clear it. After that, the above is repeated. At this time, AND gate 423
_Since the left inputs of _1-3 are always low, the AND gate 427
Output _1-3 is always Low, the output of the comparator 425 _1-3 does not contribute at all to counter CLR. This is shown in FIG.

Here, t0 = t1 = t2 = t3 = t4 ≠ t5. That is, there are unused components in the memory block 6.

The memory block 7 need not be accessed because it is not accessed. However, the following problem, that is, "when the count error occurs in the counter in the middle, etc., the positional relationship of all the pixel data thereafter becomes out of order. In other words, the pixels of the image are out of order, and the copy cannot be made correctly. "

For this reason, even if the count value goes out of order, it is more desirable to limit the error to the main scanning line and not to continue the error in the next main scanning line. Therefore, the counter is configured, for example, as shown in FIG. That is, the counter may be divided into lower 11 bits and upper 13 bits, and the lower 10 bits may be cleared every LSYNC.

At this time, the number of pixels of one scanning line is 9572, and ACLK is 11
Since it is 88, the memory also has the disadvantage that considerable unused components occur per scan line.

Therefore, it is desirable to use a memory address control circuit which has a narrow range in which the deviation of image data when an error occurs and has a high effective use rate of the memory. However, since it is not directly related to the present invention, the details are omitted. Only this time, Memoriburotsuku is required one more will be MB ₆ also used.

From the above, reading and writing are performed simultaneously, and addressing occurs in the cycle set by SW ₁ to SW ₃ (416 ₁ to SW ₃ ). Therefore, the data to be read always starts when only the set number is written. You can see that it is late.

<Addressing in Memory Mode 2> Counters ₁ to ₃ (421
₁ ) to ₃ ) are the same as in the case of memory mode 1,
When in memory mode 2, keep MMODE2 and VDENA high,
Others shall be Low. At this time, the output of the inverter 450 becomes Low and is input to the AND gates 432 ₁ to ₃ .
426 ₁ to ₃ will not output High. That is, even if the controller 415 _1-3 match output, the counter so will not be cleared, each decoder will be sequentially addressed from CS ₀ to CS _4. It should be noted that although the data is output sequentially after CS ₅ , it is not accessed because the target RAM is gone. The above timing is shown in FIG.

Counter ₁ to ₃ as the address counter <addressing when the memory mode 3> (421 _1-3)
Use VDENA and MMODE3 as in modes 1 and 2.
Is kept at High, and the rest is kept at Low. FIG. 19 is an addressing timing diagram in the memory mode 3 (MMODE3). When one START pulse is input, each of the counters 1 to 3 is cleared and increases with the input of ACLK. Since at this stage RSFF1 remains is reset by START pulse, Q output Low, the output of Yotsute AND gates 434 ₁ to ₃ is Low.

Further, since the other input of OR gate 433 _1-3 also is Low, the OE (Autopu bracts enable) decoders _1-3 remains Low.

Therefore, the CS outputs of decoders ₁ to ₃ (417 ₁ to ₃ ) are all
High, that is, the memory is not activated and remains in the refresh cycle. Each memory keeps counting up, the counter 1 has 24 bits, and the address input value of the comparator 1 is the data setting SW1 (416 ₁ ) (set value is 6,272,640)
When consistent with, the comparator outputs a High to Q terminals, via dei rate line 422 _1, and excisional the RSFF1, A
High output of ND gate 426 _1, OR gate 428 _1, the AND gate 42
3 ₁ , OR gate 431 ₁ , mono multivibrator MM ₁ (430 ₁ )
, The CLR input of the counter 1 is set to High for a moment, so that it is cleared.

The Q output of RSFF1 is also connected to the AND gates 434 _1,
RSFF1 is excisional (Q = High) 434 ₁ output from the time H
igh, and the 433 _first output is High, slave connexion, the output of the decoder 417 ₁ from this time becomes enabled, ▲ ▼ any is to be output, memory access is initiated.

After excisional of RSFF1 is, comparator 425 ₁ of the output is 1 input of the AND gate 427 _1, the Q output of RSFF1 is summer and the other input, the clear after the counter 1, A-side setting of the comparator 425 ₁ It is performed any number of times when the value (parallel output value of S / P converter 440) and the output value of counter 1 match.

 The above operation is shown in FIG.

In addition, the serial / parallel converter 440
CMPSD, by sending in synchronization with DSHIFT pulses from the data D ₁ to D ₂₉ as the timing shown in FIG. 20 the DSMIFT data, the output value of 24bit is set.

The output terminals DO ₀ to DO ₁₁ of the memory are all pulled up to High. Therefore, since the memory output is high impedance after read enable,
The value output to PR400 is 111B (corresponding to a blank).

In the above description, the number of memories corresponding to the number one less than the recording color component is provided as the memory. However, the number of the memories may be equal to the number of all the recording color components. In such a case, the configuration is effective for matching the reading position of each color component (taking resist).

(5) Printer Unit 600 Next, the printer unit (PR) will be described.

Referring to FIG. 2, the outputs of the CCDs 7r, 7g, and 7b are subjected to analog / digital conversion and subjected to necessary processing to obtain recording color information of black (BK), yellow (Y), magenta (M), and cyan. (C) Each of the 3 bits is converted into an octalized signal for recording energization.

For each of the octalized signals, C, M, and Y are memory units 400
, BK is directly from IP200 Printer Unit PR600
Are input to the laser drivers 112bk, 112y, 112m, and 112c, and the respective laser drivers are connected to the semiconductor lasers 113bk, 113y, and 113m.
And 113c, a laser beam modulated with a recording color signal (binary signal) is emitted.

FIG. 1 is referred to again. The emitted laser beams are reflected by the rotating polygon mirrors 13bk, 13y, 13m and 13c, respectively, and f
Through the -θ lenses 14bk, 14y, 14m and 14c, to the fourth mirror 15b
k, 15y, 15m and 15c and the fifth mirrors 16bk, 16y, 16m and 16c are reflected by the polygon mirror, and the polygon mirror 17b is a cylindrical lens 17b.
After passing through k, 17y, 17m and 17c, the photosensitive drums 18bk, 18y, 18m and 18c are irradiated with an image.

The rotating polygon mirrors 13bk, 13y, 13m, and 13c are fixed to the rotating shafts of the polygon mirror driving motors 41bk, 41y, 41m, and 41c, and each motor rotates at a constant speed and drives the polygon mirror at a constant speed. . By the rotation of the polygon mirror, the laser light is scanned in a direction perpendicular to the rotation direction (clockwise) of the photosensitive drum, that is, in a direction along the drum axis (this is referred to as a main scanning direction).

FIG. 21 is a detailed view of a laser scanning system of the cyan color recording apparatus, where 43c is a semiconductor laser.

At one end of the laser scanning (two-dot chain line) in the direction along the axis of the photosensitive drum 18c, a sensor 44c, which is a photoelectric conversion element, is provided so as to receive the laser beam. The start point of one-line scanning is detected at the time when the detection is made and the detection is changed to the non-detection. That is, the laser light detection signal (pulse) of the sensor 44c is processed as a laser scanning line synchronization pulse. The configurations of the magenta recording device, the yellow recording device, and the black recording device are exactly the same as those of the cyan recording device shown in FIG.

Referring again to FIG. 1, the surface of the photosensitive drum is uniformly charged by charge scorotrons 19bk, 19y, 19m, and 19c connected to a negative charge high voltage generator (not shown). When the laser beam modulated by the recording signal is applied to the uniformly charged photoreceptor surface, charges on the photoreceptor surface flow to the equipment ground of the drum main body due to a photoconductive phenomenon and are reduced. Here, the laser is not turned on in a portion where the document density is high, and the laser is turned on in a portion where the document density is low. As a result, portions of the surface of the photosensitive drums 18bk, 18y, 18m, and 18c corresponding to portions where the document density is high have a potential of -800V, and portions corresponding to portions where the document density is low have a potential of about -100V. An electrostatic latent image is formed corresponding to the shading.
Each of the electrostatic latent images is referred to as a black developing unit 20bk,
Developed by the yellow developing unit 20y, the magenta developing unit 20m and the cyan developing unit 20c, and the black, black, and black are applied to the surfaces of the photosensitive drums 18bk, 18y, 18m and 18c, respectively.
A yellow, magenta and cyan toner image is formed.

The toner in the developing unit is positively charged by agitation, and the developing unit is biased to about -200 V by a developing bias generator (not shown). Correspondingly, a toner image is formed.

On the other hand, the recording paper 267 stored in the transfer paper cassette 22
The sheet is fed by the sheet feeding operation of the feed roller 23, and is sent to the transfer belt 25 at a predetermined timing by the registration roller 24. The recording paper placed on the transfer belt 25 is a transfer belt.
By the movement of 25, the photosensitive drums 18bk, 18y, 18m and 18c sequentially pass under the photosensitive drums 18bk, 18y, 18m and 18c.
, The black, yellow, magenta, and cyan toner images are sequentially transferred onto a recording sheet under the transfer belt by the action of a transfer corotron.

The transferred recording paper is then sent to the heat fixing unit 36, where the toner is fixed to the recording paper, and the recording paper is placed on a tray.
It is discharged to 37.

On the other hand, the residual toner on the photoreceptor surface after the transfer is removed by the cleaner units 21bk, 21y, 21m and 21c.

The recording devices for each color are arranged at a distance of 110 mm. The recording density is 16 dots / mm, the number of pixels in one main scanning line is 4752 dots, and the maximum number of pixels in the sub-scanning direction is 6720 dots.

Next, the printer controller 601 and its operation timing will be described. The printer controller includes a microcomputer unit including an output port with a driver for energizing each part of the printer, an input port for receiving an input from a sensor, an input / output interface with the SCON700, a CPU, a RAM, a ROM, an interrupt controller, and the like. It consists of a high-speed logic circuit for writing pixel data that is interfaced by the I / O section of the section.

First, turn on the system power switch 50.
When it is turned on, the PR600 section is also energized. ・ The temperature of the fixing unit 36 rises. ・ The constant speed rotation of the polygon mirror starts up. ・ The home positioning of the carriage 8 ・ The line synchronization clock (LSYNC) is generated (1.44KHz) ・ Clock for video synchronization (this is faster than CLK0: 7MHz)
(8.42MHz), ・ Initialize various counters, etc.

The line synchronous clock is a polygon mirror motor driver and IP20
0, SC100 and SCON700. The former uses this signal as a reference signal of a phase lock loop (PLL) servo, and the beam sensors 44bk, 44y, 4 which are feedback signals.
The beam detection signals of 4m and 44c are controlled so that they have the same frequency as the line synchronization clock and have a predetermined phase relationship.

As a signal for synchronizing the start of laser beam main scanning, detection signals (pulses) of the beam sensors 44bk, 44y, 44m, and 44c are used for each color (each sensor), and are used.
The frequency of the line synchronization signal and the detection signal of each beam sensor is
Since the signals are locked by the PLL and may cause the same but a slight phase difference, the scanning reference uses the detection signal of each beam sensor instead of the line synchronization signal. The video synchronization clock has a frequency of one dot (one pixel) for laser writing, and is supplied to the high-speed logic circuit for writing and the laser drivers 112bk, c, m, y.

The high-speed logic circuits for writing include (1) two sets of image memories for one main scan (used as input toggle buffers), and (2) BK, C, M, and Y writing dot counters.

FIG. 22 is a timing chart of a print cycle.
When the warm-up operation is completed, the printer is ready for printing, and the PR 600 sends a “ready” status to the SCON 700. SCON is PR400 when the status of all other units is all "operable" and the copy button on the CU750 is pressed.
Sends a “Print Start” command to

When the PR receives this signal, the valid image data is input to the laser drivers 112BK, C, M, and Y with a delay of one main scanning line from the next LSYNC (because of the toggle buffer). , m, y. The write dot counters (BK, Y, M, C) are cleared at the rise of the detection signal of each beam sensor, and the count-up is performed by the video synchronization signal.

If the dot counter is between 1 and 400, it is dummy data and 401
Up to 5153 (4752 pieces) are writable values. Here, the dummy data is for adjusting the physical distance between the photosensitive drums 18bk, 18y, 18m and 18c of the beam sensors 44bk, 44y, 44m and 44c. Also, write data (7-0)
Is captured at the falling point of the video sync signal.

In addition, the first, second,... In the timing chart (FIG. 22)
6720 is a scanning line number of one main scanning line transferred to the same position in the sub-scanning direction on the transfer paper.

Writing to the toggle buffer memory is performed at the frequency of CLKO (7 MHz) supplied from IP200, and reading of one toggle buffer memory is performed using the video synchronization signal (8.42
MHz) cycle.

The difference between the two frequencies is that the effective scanning range of the laser beam is about 70% of the rotation angle of the motor 41c because the polygon mirror 13c is used as shown in FIG.
It is necessary to be faster.

In the microcomputer also two sets of main scanning counter (LSYNC-CTR _{1, 2)} there is, (a CTR ₁ in this case) one counter "print start" command from the SCON is cleared, the LSYNC Increment by 1 each time it enters. The LSYNC-CTR ₁ outputs an instruction to the laser drive circuit 112 _BK , _C , _M , _{Y according} to the value as follows.

112bk The laser 43 _BK drive when LSYNC-CRT = 1-6720, other non-driven, laser 43c driving time of the 112c LSYNC-CRT ₁ = 1760~8479, other non-driving, the 112m LSYNC-CTR ₁ = 3520 to 102390, laser 43 _M
Drive, the other non-driven, the laser 43 _Y when the 112y LSYNC-CTR ₁ = 5286~12005
In the case of driving, other non-driving, and when making multiple prints continuously, the next “start” command is received from SCON700. At this time
If LSYNC-CTR ₁ is operating, clear LSYNC-CTR ₂ ,
Make a start.

The second image data controls the lasers 43 _BK , _C , _M , and _{Y in} the same manner as in the previous case. Further, when the third start signal is received, if LSYNC-CTR ₂ is operating, the first counter is cleared and the operation is started. Hereinafter, such a toggle operation is repeated to create a plurality of prints.
Therefore, even if random values are received for the BK data from the IP and C, M, and Y data from the MU outside the valid image section, the image is formed on the photoreceptor 18 _BK , _C , _M , and _Y. Never.

In fact, BK,
The output enable / disable flag of each color of C, M, and Y is set, and the logical AND of this flag and the above-mentioned LSYNC-CTR ₁ , ₂ is used to determine whether to output the laser 43 _BK , _C , _M , _Y. Do or not. This flag is set by a “color mode setting” command from SCON700.

(6) Console unit (CU) 750 Fig. 23 is a block diagram of the console unit.
FIG. 24 is a layout diagram of buttons and display means for operation display.

In FIG. 23, a console unit 750 includes a console board 750 ', a CPU 754, a matrix type or dynamic drive type I / O / decoder driver 756, an LCD controller 757, a video RAM (VIDEO RAM) 758, a RAM 759, a ROM 760,
It comprises an interrupt controller 761, a serial I / O 762, and an LCD driver 763.

The console board 750 'is a 512 × 256 dot L
It comprises a CD dot matrix display 751, an LED display group 752, and a switch matrix group 753. The switch matrix group 753 is composed of a group 1 and a group 2. The group 1 has 49 switches (normal push buttons) 765 to 813 in FIG. 24, and the group 2 has a transparent touch sensor button 753a-11 to 753. The touch sensor and the LCD dot matrix display 751 are provided at the same position in FIG. This touch sensor button is divided into eight small in the horizontal direction and four in the vertical direction, and a total of 8 × 4 =
It comprises 32 matrix switches.

In FIG. 23, when the switch button of group 1 is pressed, the I / O / decoder driver 756 causes an interrupt signal 756a.
When the touch sensor switch of group 2 is pressed, the interrupt signal 756b is set high, and an interrupt subroutine is entered, and the ON / OFF status of all switches is checked by the CPU7.
54 can know. At this time, the information to be sent to SCON700 is sent to SCON I / F762 (serial I / O) immediately.
Sent to 700.

When some kind of display is required, the LED display group 752
Alternatively, it is displayed on the LCD dot matrix display 751.

The display can be changed by selecting one of the switch matrices 753.
One or more buttons are pressed, or a display command is received from SCON700.

 Next, a copy creation operation of the system will be described.

[1] Basic copy mode Scanner unit SC100 for making N copies
The image processor IP200 performs image processing on the data read by the SC100, and performs BK
The data is output directly to the printer unit PR600, and the C, M, Y data is output to the memory unit MU400. C,
The MU 400 that has received the M and Y data outputs the C data with a delay corresponding to the distance 110 mm between the BK recording device and the C recording device in the PR 600 for C. This 110mm is 110 × 16LSYNC = 176
0 main scanning lines, 1760 lines are 1760 x [297 mm (effective main scanning line length)
X 16 dots] = 8,363,520 pixels. This delay is generated and output to PR600. Similarly, M is 1,672,707 pixels,
Y is output to PR600 with a delay of 25,090,560 pixels. That is, the MU 400 is operated in the memory mode 1.

FIG. 25 is a timing diagram of the basic copy mode, in which (a) is a drawing combination diagram, (b) and (c) are partial views, and shows timings in the case of two-sheet repeat copy. In this case, set to 4-color full-color mode and use SCON70
0 is the BK, C, M, PR
Y, send all output enabled data. Various scan mode setting commands such as “A size reading” are sent to the SC 100. The UCR of IP200 is set to UCR execution. The 25th
In the figure, in the section of “SCON IP data output”, b is the output of what IP sets before image processing, for example, RA
For example, writing of M224.

B) IP is always output during image processing, it is valid,
For example, it may change on the way at UCR, D ₀ to ₁₁ or the like.

After the above, when the "scan start command" is sent to the SC 100, the LSYNC counter in SCON (this is referred to as SYS-L-CTR) is cleared and the count is enabled.

SYS for the number of main scanning lines (several to several tens) required for processing with IP200
When the count value of -L-CTR (hereinafter, this count value is referred to as NIP) reaches, a "print start" command is output to PR600 and one pulse is output to MSTART line to MU400.

Then, the BK of the image signal processed by the IP 200 is directly output to the PR, and the printing operation is performed immediately. C, M, and Y are input to the PR 600 with a delay of a predetermined number of pixels in the MU 400, and the printing operation of each color is performed. Here, the portion C outputs data stored in the MU (although there are others), but this value may be random.

However, in the PR600, as mentioned earlier, the LS in the PR600
Since the outputs of the lasers 43 _BK , _C , _M , and _Y are controlled by the YNC-CTRs 1 and 2, this data is not printed.

When SYS-L-CTR in SCON reaches an appropriate value, it is cleared and a "start" command is sent to SC100 again.
Further, a “start” command is sent to the PR600. Note that no MSTART pulse is generated in the MU400.

By repeating the above, a repeat copy is created.

[2] High-speed copy mode To make N copies • One SC scan scan (at this time, IP processes the image and MU
Perform N times PR print operation (MU is MMODE3 at this time).

FIG. 26 is a timing chart of the high-speed copy mode,
(A) is a drawing combination diagram, and (b) and (c) are partial views showing timings when two copies are made.
When the High button (767) is pressed on the CU750 shown in Fig. 24, the CU
The display 767a is turned on by the 750 itself, and this information is immediately transmitted to the SCON 700. Then start button 8
When 13 is pressed, it is also sent to SCON700 immediately.

The SCON 700 sends a “scan mode setting” command to the SC 100 if necessary. If the IP needs to be set in advance, the SCON 700 sends the above data.

Next, the data of the above B is output to the IP, and MMODE2 of the MU is set to Hi.
Set to gh and send the "scan start" command to the SC. SY
When the SL-CTR counts the number of processing delay LSYNCs (nips) of the IP 200, one MSTART signal is sent to the MU 400.

Thus, first, the image data is stored in the MU 400. The sub-scan length that can be stored is When converted to the addressing of the address counters 421 ₁ to ₃ , it corresponds to 0 to 5,242,879. To increase the storage length in the sub-scanning direction, the memory blocks MBA and MB shown in FIG.
B and MBC may be added, and a chip select circuit may be added.

If the High button 767 is pressed while the “4Color” display 769a is lit on the CU750, the 769a is turned off and “3
"Color" display 768a.

In the three-color mode, when the SCON 700 outputs low data to IP, the UCR signal outputs low.

During the above, a “print mode setting” command is sent to PR600. This includes the information of "BK output not possible".

When all image data is stored in the MU, the SCON700
MMODE2 is set to Low, MMODE3 is set to High, an MSTART pulse is issued, and a “print start” command is sent to the PR600. Then, counters 1-3 (421 _1-
3) start the increment from 0, the counter matches the value of the data setting switches 416 _1-3, and outputs the data to the PR600 from the memory to which the counter is addressing. The output is in the order of C, M, Y.

Each counter 421 _1-3, a comparison of the following becomes parallel output value of the S / P converter 440, which is repeated.

In FIG. 26, each time is lengthened for easy viewing. Actually, send “Print Start” command, MSTA
The generation timing (t ₁ ) of the RT pulse is preferably generated immediately after the valid data of the SC 100 is processed by the IP 200.

It is preferable that the set value of the S / P converter is reduced to the limit of the valid data range [however, this set value is the address 1188 (= 4752 pixels × 1/1) used in one main scanning line.
4) must be an integer multiple of 4).

In this way, when making a large number of copies, it is not necessary to have the SC return time and print, so that the copy generation speed is greatly improved.

If an A4 size copy is made at 20 CPM when making a copy in the basic copy mode of [1] above, it will be about 26 CPM in this mode.

Note that the 24-bit CMPSD data stored in the MU 400 is transmitted before the second MSTART pulse as shown in FIG.

[3] Multi image copy mode No. 27 in both main and sub scanning directions
Referring to the drawing, this mode is arranged such that when the length of a specific section in the main scanning direction of the document is 1 m, images of a plurality of specific sections 1 m are not overlapped in the main scanning direction of the transfer paper, and In this mode, when the length of a specific section in the sub-scanning direction of the document is 1 s, the images of the specific section 1 s are arranged in the sub-scanning direction of the transfer paper so as not to overlap.

It is also possible to combine main / sub bidirectional or either main / sub magnification, for example, reducing the entire A3 size image to 25% for both main and sub, and reducing this reduced image to 16 on A3 transfer paper. It is also possible to print in a matrix (two-dimensionally).

FIG. 27 illustrates a case where only two multi-copy is made three times in the sub-scanning direction.

 The setting and operation of this mode are performed as follows.

<Settings related to the main scanning direction> a. When the operator presses the main scanning direction multiplexer button 777 once, the displays 777a and 777c on the CU750 are turned on and "Please enter the dimensions" is displayed on the display 751. The message is displayed, and the operator inputs the size 1 m of the repetition section using the buttons 816_0 to 816-9 and the Enter button 808 in response to the message (see FIG. 24).

Or b. When the operator presses the main scanning direction multiplexer button 777 twice, the displays 777a and 777d on the CU750 are turned on, and "Please enter the number of divisions" is displayed on the display 751. This is performed by the operator inputting the number Nm of the repetition sections with the buttons 816_0 to 816_9 and the Enter button 808 according to the message.

Further, the dimension 1m at this time is the same as
In the case of, the division number is temporarily converted into a value obtained by dividing the main scanning length of the transfer paper by Nm, and is displayed on the display 777b.

In the case of b, the value of Nm is displayed for a while after the Enter button 808 is pressed, and then the display is switched to 1 m after a suitable time. Also, display 777d at the same time
Is switched off and the display 777c is switched on.

<Settings related to the sub-scanning direction> a. When the operator presses the sub-scanning direction multi-image button 780 once, the displays 780a and 780c on the CU 750 light up, and "Please enter the dimensions." Is displayed, and the operator inputs the size 1s of the repetition section using the buttons 816_0 to 816_9 and the Enter button 808 in response to this message.

Or b. When the operator presses the main scanning direction multi-image button 780 twice, the displays 780a and 780 on the CU 750 are turned on, and "Enter the number of divisions" is displayed on the display 751. the Metsuseji is performed by inputting the number N _s of operator repeated sections button 816_0～9 and enter button 808 in response to.

Further, the dimension 1s at this time is the same as
In this case, the division number is temporarily converted to a value obtained by dividing the sub-scanning length of the transfer paper by Ns, and is displayed on the display 780b.

In the case of b, the value of Ns is displayed for a while after the Enter button 808 is pressed, and then the display is switched to 1s after an appropriate time. At the same time, the display 780d is switched off and the display 780c is switched on.

<Copy Operation> The copy operation is a first process including reading of an original by the SC 100, formation of a plurality of sets of the same image data in the main scanning direction by the IP 200, memory operation of the same image data to the MU 400, and storage in the MU 400. A second process of cyclically outputting the image data that has been output to the PR 600 a plurality of times and continuously forming a plurality of identical image data on transfer paper in the sub-scanning direction (FIGS. 2, 3, (See FIG. 4, FIG. 5, FIG. 6, FIG. 8, and FIG. 27).

--- First course --- CU750 sends various setting information to SCON700, and then SCON70
In the case of 0, data is written to address 0 of RAM 224 of IP 200 by setting the value of Dsf ₁ to 0 for preset data of RD-CTR 251, according to the procedure described in FIG. Here, the value of Dsf ₁ is set to 0 in order to match the start point of the main scanning line repetition with the edge of the document, and if the start point is set at another position, the value is set to a value corresponding thereto.

Further, data relating to scaling in the main scanning direction is given to the block 205 in the IP 200 through the ZD ₀ to ₁₁ signal lines.

Subsequently, when the operator presses the start button 813, in the main scanning direction, the SCON 700 continues to output a value of 1 m × 16 ÷ 2 to D ₀ to D ₁₁ while the IP 200 is processing the input image data.
With respect to the sub-scanning direction, as shown in FIG.
0 is 297 × 16 × 1s × 16 ÷ for MU400 through CMPSD signal line
4 and then output MSTART = 1, MMODE1,2,3 = 0.

Scanner scan mode is set for SC100. In this case, "scan in 0-1s section", "magnification of sub-scan"
And so on, and then a "scan start" command.

When SYS-L-CTR of the initial value 0 is incremented by LSYNC and eventually reaches nip corresponding to the processing delay of IP200, MMODE2 = 1 is output, and SYS-L-CTR is nip + 1s
Return to MMODE2 = 0 when x16 is reached.

At this stage, the MU 400 has stored a plurality of image data in the main scanning direction and one image data in the sub scanning direction.

When scaling is set, the data stored in the MU 400 is image data that has already been scaled for both the main and sub units.

--- Second process-- Next, MMODE2 = 0 and MMODE3 = 1, and a "print start" command is sent to PR600 for the required number of copies. However, the interval at which this command is sent is when the SYS-L-CTR matches a predetermined image data output interval.

By operating in this manner, the image data already stored in the MU 400 is the 24-bit data of the S / P converter 4 (440), that is, the value sent through the CMPSD and the count value of the memory address counters 421-1 to 423-1. The counter is cleared and is output repeatedly in the sub-scanning direction each time. Since this output data is already stored in the multi-scanning direction in the main scanning direction, a plurality of copy images in both main and sub-directions, that is, multi-image copying in both the main and sub-scanning directions are obtained. become.

While the IP200 is processing the input image, A5 to IP200
All A9 inputs are kept at 0, and ALL inputs are kept at 1.

<Example> Here, 1 / of the main scanning length from the edge of the document (main scanning start point)
4, that is, the width of 279mm / 4 = 74.25mm is the main scanning length of A3 paper 297mm
In the sub-scanning direction, a width of 400 mm / 4 = 100 mm from the sub-scanning start point of the original in the sub-scanning direction, ie, 400 mm / 4 = 100 mm, is added to the sub-scanning length of 400 mm. An example in which a single copy is made by repeatedly forming images of a total of 16 surfaces at the same magnification will be further described.

Before the SC100 read operation starts, the SCON700 must read the IP200 RAM
Write 0 to the start address of 224 (corresponding to Dsf ₁ ). After that, A5 to A9 before IP200 starts image processing.
The signals are all 0, and D _{0 to} D ₁₁ are 74.25 × 16252, that is, 594
Is converted to binary and its signal level is output, and these signal levels are continuously maintained during image processing.

SCON700 sends 297 x 16 to MU400 via CMPSD signal line.
Send a value of × 100 × 168004 = 1900800 (this data transmission does not need to be completed immediately, but may be completed immediately before the MU400 starts sending image data to the PR600). MSTART = 1, MMODE1,2,3 = 0 are output.

To the SC 100, a setting command such as a scan mode of the scanner, in this case, "scan in the range of 0 to 100 mm" is sent, and then a "scan start" command is sent. Thereafter, when the reading operation of the SC 100 and the image processing operation of the IP 200 are started, when the value of VCLK after the first LSYNC is counted to 4871, the preset value is stored in the RD-CTR 251 in the RAM 224.
More loaded. This load operation is performed every time LSYNC is received, but since the values of A5 to A9 are always the same, the data to be loaded is always the same. Original image data valid from the second or later LSYNC is transmitted from the SC 100. The data at this time is stored in the toggle buffer memory 263r, g, b or 26.
6r, g, or b will be written. The data stored in the toggle buffer memory is the next LSYN
The image is read from C, and a multi-image is formed at this reading stage and transmitted to the next stage.

This read operation is started from the address 0 of the toggle buffer memory because the initial value of the RD-CTR 251 is a preset value, that is, 0. RD-CTR2
Numeral 51 is incremented each time one pulse of VCLK. This output value is used not only for addressing the toggle buffer memory but also as the B-side input signal of the 13-bit comparator 254.

On the other hand, the upper 12 bits of the A side input of the comparator are
Is connected to the D ₀ ~ ₁₁ signals from SCON700, least significant bit is fixed to 0.

Therefore, when the value of RD-CTR 251 matches twice the value of D ₀ to D ₁₁ , the comparator 254 outputs 1 as a match signal from the OUT terminal to clear RD-CTR 251. Since VCLK continues to come after this clearing, the reading of the toggle buffer memory can be started again from address 0.
In this way, data in the same section is read four times for convenience and output to the next circuit.

On the other hand, the software counter SYS-
Since the L-CTR is cleared immediately after the "start" command is issued to the SC 100, and the LSYNC signal is output as one pulse for each main scan, the SYS-L-CTR is incremented. Eventually, MMODE2 = 1 is output when it reaches nip corresponding to the processing delay of IP200. That is, four identical images are formed side by side in the main scanning direction, and the arranged image data is stored in the MU 400 through other image processing.

Incidentally, to obtain a multi-image copy of scaling to the original, 1m × 16 ÷ 2 ÷ The D ₀ ~ ₁₁ when the magnification is m
m is given.

This is because the scaling means is located at a stage subsequent to the present circuit.

Next, MMODE2 = 0 and MMODE3 = 1, one pulse is issued on the MSTART signal line, and then a “print start” command is sent to the PR600. Then, an address counter 421-3 for each color memory in the MU 400 is temporarily generated by the MSTART pulse.
１1 is cleared and incremented by the LSYNC pulse. Eventually, the 24-bit comparators 3-1 (415-3-1) become O each time they sequentially match the value of the data setting SW 3-1.
1 is output from the terminal, the plurality of address counters are cleared again through some gates, and the increment is started again. At the same time, the OE terminals of the decoders 417-3 to 417-1 are set to 1 and the C in the image memory is reset. , M, Y data starts to be output to PR600. Address counter that started incrementing again
421-3 to 4-1 have 24-bit comparators 4 to
6 (425-1 to 3) are also connected to the B side input, and are compared with the previously set 24-bit output of the S / P converter 440.

Therefore, from the next time, the coincidence outputs of these comparators effectively act on the CLR terminals of the plurality of address counters, and the data in the image memory is output again from address 0. By repeating the above, the same data is transmitted to the PR 600 a plurality of times (in this case, four times) in the sub-scanning direction, and a multi-image is formed in the sub-scanning direction. Here, one set of the data passed to the PR 600 is already multi image data in the main scanning direction. Thus, a total of 16 multi-images are formed in both the main and sub directions.

FIG. 28 shows the relationship between the original and the obtained copy at this time.

FIG. 29 shows the relationship between the original and the copy in an example in which the A3 original is reduced to 50% for both the main and sub sides and a multi-image of two main and sub sides each is formed on A3 transfer paper.

In the above embodiment, the case where the main scanning repetition section 1m does not change at the sub-scanning position has been described.

However, 1m can be changed at an arbitrary position yn (0 <yn <1s) within a range smaller than the repetition section 1s in the sub-scanning direction. One set of images with different numbers of multi-screens in the main scanning direction
As a set, a plurality of sets of images can be obtained on a transfer sheet by arranging them in the sub-scanning direction every 1 second.

<Mode setting> Mode setting related to this becomes complicated, so only the main points will be described.

The item of <setting regarding the main scanning direction> is slightly changed while <setting regarding the sub-scanning direction> of the previous embodiment remains unchanged. In short, in short, the operator sets the position dimension value y in the sub-scanning direction and the position corresponding to the position in the sub-scanning direction for n sets in which the number of multi-screens in the main scanning direction is different corresponding to the sub-scanning position within a range smaller than 1 s. A desired repetition position 1m in the main scanning direction is input as a pair and n sets are input. That is, <Operation> --First process-- As in the previous embodiment, the SCON 700 outputs commands and various signals to other units.

The software counter SYS-L in SCON700
-CTR is cleared before the IP 200 enters image processing.

Copy operation starts, and SYS-L-CT
R is incremented, but this SYS-L-
The D ₁₁ to D ₀ in accordance with the count value of the CTR by appropriately switching a plurality of main scanning multi-image is obtained on the MU400.

Then, those A-side input of the comparator 254 in the previous embodiment has been made always the same is, the value of D ₁₁ to D ₀ at the position of the sub-scanning direction in this embodiment is switched, is compared in each case different values Will be.

Therefore, a different number of sets of main scan repetitive images at different y positions are obtained in the MU 400.

--- Second process-- Same as the previous embodiment.

As an example of the above, FIG. 30 shows an example in which the image is repeated twice in the main scanning direction at y1, four times in the main scanning direction at y2, and this is set as one set, and further two sets of images are repeated in the sub-scanning direction. .

〔effect〕

The present invention is configured as described above, and stores image signals corresponding to the read original image, and uses a memory unit that outputs the stored data to each image forming station with a different delay time. Is repeatedly formed a desired number of times.

Therefore, it is not necessary to provide a dedicated frame memory separately as in the related art, cost can be reduced, and there is no color shift due to a timing shift of a signal between the memory means and the dedicated frame memory. While maintaining the color image generation speed,
A highly reliable digital color image forming apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing the overall configuration of a digital color copying machine to which one embodiment of the present invention is applied, and FIGS. 2 (a-1) and 2 (a).
2) is a system block diagram of the copying machine shown in FIG. 1, FIG. 2 (b) is a drawing connection diagram, and FIGS. 2 (c), (d), (e),
(F) is a partial view, FIG. 2 (g) is an explanatory view showing how to call a gate, FIG. 3 is a circuit diagram of an image processor IP, FIG. FIGS. 4B and 4C are partial views, FIG. 4 is an explanatory diagram of address data of the RAM 224, and FIG.
FIG. 6 is a write cycle timing diagram of the RAM 224, FIG. 6 is an operation timing diagram of the image processor IP, FIG. 7 is a circuit diagram for explaining the circuit block 207c, and FIGS.
(A-2), (a-3), and (a-4) are memory units.
FIG. 8 (b) is a drawing connection diagram, FIGS. 8 (c), (d), (e) and (f) are partial views, and FIG.
The figure is a circuit diagram showing a RAM, FIG. 10, FIG. 11, FIG.
3 (a) is an operation timing diagram of the RAM of FIG. 9, FIG. 13 (b) is an explanatory diagram showing the meaning and time of symbols in FIGS. 10 to 13 (a), and FIG. 14 is a memory. FIG. 15 is an explanatory diagram of a pulse indicating an address clock, FIG. 16 is an explanatory diagram illustrating a relationship between an output of a comparator and a counter, FIG. 17 is a circuit diagram illustrating a configuration of a counter, 18 is a timing chart showing the addressing timing in the memory mode 2, FIG. 19 is a timing chart showing the addressing timing in the memory mode 3, FIG. 20 is a timing chart of the CMPSD data and the DSHIFT pulse, and FIG. FIG. 21 is a detailed view of the laser scanning system of the cyan recording apparatus, FIG. 22 is a timing diagram of a print cycle, and FIG.
FIG. 24 is a block diagram of the console unit, FIG. 24 is a layout diagram of operation display buttons and display means,
(B) and (c) are timing diagrams of the basic copy mode.
(A) is a drawing combination diagram, (b) and (c) are partial views, and FIG.
(A), (b), and (c) are timing diagrams of the high-speed copy mode, (a) is a drawing combined diagram, (b) and (c) are partial views, and FIG. 27 is both main and sub scanning directions. FIGS. 28 (a) and (b) are timing diagrams of the multi-image copy mode. Vice each 2
FIGS. 30 (a) and 30 (b) are explanatory diagrams showing an example of image formation in which two sets are repeated in the sub-scanning direction, showing the relationship between a manuscript and a copy for forming a multi-image of four surfaces in total. 18 photosensitive drum, 20 developing unit, 25 transfer belt, 29 corotron for transfer, 267 recording paper, 100
Scanner unit (SC), 200 Image processor (IP), 400 Memory unit (MU), 600 Printer unit (PU), 700 System controller (SCON)

Claims (1)

(57) [Claims] 1. An original image reading means for scanning an original image in a main scanning direction and a sub-scanning direction to separate the image into a plurality of color components and reading the image, and in a transport direction of the recording medium for forming an image on the recording medium. A plurality of image forming stations provided at a predetermined interval along, and each image forming station except one of the image forming stations is delayed by a time corresponding to the interval between the image forming stations. In a digital color image forming apparatus having a delay memory for outputting an image signal corresponding to an original image read by an original image reading unit and a memory control unit for controlling the delay memory, the same image is stored on the same recording medium. A repeat mode designating means for designating a repeat mode for repeatedly outputting is provided, and the repeat mode is designated by the repeat mode designating means. In this case, at least a part of the original image to be repeated in the delay memory is stored in the main scanning direction and the sub-scanning direction, and the read time of the storage data stored in the delay memory by the memory control unit is set to the time. While changing according to the image forming station that is the output destination of the storage data, the data is repeatedly output to the image forming station, and at least a part of the original image is recorded on the recording medium in at least one of the main scanning direction and the sub scanning direction. A digital color image forming apparatus, which is formed repeatedly in one direction.