JPS6094537A - 並列直列変換回路 - Google Patents

並列直列変換回路

Info

Publication number
JPS6094537A
JPS6094537A JP58202353A JP20235383A JPS6094537A JP S6094537 A JPS6094537 A JP S6094537A JP 58202353 A JP58202353 A JP 58202353A JP 20235383 A JP20235383 A JP 20235383A JP S6094537 A JPS6094537 A JP S6094537A
Authority
JP
Japan
Prior art keywords
signal
data
bit
flip
shift register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58202353A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0233212B2 (enrdf_load_stackoverflow
Inventor
Shinichi Isobe
磯部　信一
Minoru Kataoka
稔 片岡
Mikio Yonekura
米倉　幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP58202353A priority Critical patent/JPS6094537A/ja
Publication of JPS6094537A publication Critical patent/JPS6094537A/ja
Publication of JPH0233212B2 publication Critical patent/JPH0233212B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
JP58202353A 1983-10-28 1983-10-28 並列直列変換回路 Granted JPS6094537A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58202353A JPS6094537A (ja) 1983-10-28 1983-10-28 並列直列変換回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58202353A JPS6094537A (ja) 1983-10-28 1983-10-28 並列直列変換回路

Publications (2)

Publication Number Publication Date
JPS6094537A true JPS6094537A (ja) 1985-05-27
JPH0233212B2 JPH0233212B2 (enrdf_load_stackoverflow) 1990-07-26

Family

ID=16456110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58202353A Granted JPS6094537A (ja) 1983-10-28 1983-10-28 並列直列変換回路

Country Status (1)

Country Link
JP (1) JPS6094537A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04185021A (ja) * 1990-11-20 1992-07-01 Fujitsu Ltd 論理素子による信号の逓倍化方式
JPH08116272A (ja) * 1991-07-12 1996-05-07 Mitsubishi Electric Corp 並直列／直並列変換回路
EP1079300A1 (en) * 1999-08-09 2001-02-28 ATI International SRL Method and apparatus for serially transmitting graphics data
KR100309618B1 (ko) * 1996-12-13 2001-11-15 칼 하인쯔 호르닝어 병렬/직렬 변환기

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58146129A (ja) * 1982-02-24 1983-08-31 Usac Electronics Ind Co Ltd 並列・直列変換回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58146129A (ja) * 1982-02-24 1983-08-31 Usac Electronics Ind Co Ltd 並列・直列変換回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04185021A (ja) * 1990-11-20 1992-07-01 Fujitsu Ltd 論理素子による信号の逓倍化方式
JPH08116272A (ja) * 1991-07-12 1996-05-07 Mitsubishi Electric Corp 並直列／直並列変換回路
KR100309618B1 (ko) * 1996-12-13 2001-11-15 칼 하인쯔 호르닝어 병렬/직렬 변환기
EP1079300A1 (en) * 1999-08-09 2001-02-28 ATI International SRL Method and apparatus for serially transmitting graphics data

Also Published As

Publication number Publication date
JPH0233212B2 (enrdf_load_stackoverflow) 1990-07-26

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