JPS609343B2 - Electronic component manufacturing method - Google Patents

Electronic component manufacturing method

Info

Publication number
JPS609343B2
JPS609343B2 JP49120505A JP12050574A JPS609343B2 JP S609343 B2 JPS609343 B2 JP S609343B2 JP 49120505 A JP49120505 A JP 49120505A JP 12050574 A JP12050574 A JP 12050574A JP S609343 B2 JPS609343 B2 JP S609343B2
Authority
JP
Japan
Prior art keywords
temperature
bonded
molten metal
electronic component
electronic components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP49120505A
Other languages
Japanese (ja)
Other versions
JPS5146072A (en
Inventor
学 盆子原
好雄 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP49120505A priority Critical patent/JPS609343B2/en
Publication of JPS5146072A publication Critical patent/JPS5146072A/en
Publication of JPS609343B2 publication Critical patent/JPS609343B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は、熔融金属を媒介とする接続により構成する電
子部品製造法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing electronic components using connections mediated by molten metal.

これまでの電子部品の接続には、接着電子部品及び被接
着電子部品をあらかじめ常温で適正な位置に配置した後
荷重をかけて、圧接したり、熔接したりしていた。
Conventionally, electronic components have been connected by placing the bonded electronic component and the electronic component to be bonded in appropriate positions at room temperature in advance, and then applying a load to press or weld them.

あるいは荷重をかけたままで、接着金属が熔融する迄高
温に保管し、その後、常温にする方法で電子部品の接続
を得ていた。これらの方法では、圧鞍、熔接部に、過大
の負荷がかかり、接続部に割れが入ったり、歪が残った
りする欠点や、高温保管状態が長すぎることや、接続部
以外が高温状態が長い為に、劣化したり、長時間、高温
状態に保管できない場合などには使用できない欠点を有
していた。本発明の目的は、かかる従来の欠点のない電
子部品の製造方法を提供することにある。
Alternatively, electronic components were connected by storing the device under a load at a high temperature until the adhesive metal melted, and then returning it to room temperature. These methods have disadvantages such as excessive loads being applied to the pressure saddle and welded parts, resulting in cracks or distortions in the joints, as well as problems such as being stored at high temperatures for too long, and high temperatures in areas other than the joints. Because they are long, they have the disadvantage that they deteriorate and cannot be used in cases where they cannot be stored at high temperatures for long periods of time. An object of the present invention is to provide a method for manufacturing electronic components that does not have these conventional drawbacks.

本発明の特徴は、熔融金属を媒介とする接続を行なう電
子部品の製造方法において、この熔融金属を熔融温度以
下でかつ常温以上の温度で予熱し、しかる後にこの熔融
金属及び被接着電子部品を熔融金属の熔融温度以上の高
温にして被接着電子部品を加圧接着し、しかる後に加圧
状態のままで一定時間この熔融金属及び被接着電子部品
を熔融金属の熔融温度以下でかつ熔融温度に近い温度に
保持し、しかる後に加圧状態を解除して常温にする電子
部品の製造方法にある。
A feature of the present invention is that, in a method for manufacturing electronic components in which connections are made using molten metal, the molten metal is preheated to a temperature below the melting temperature and above room temperature, and then the molten metal and the electronic components to be bonded are bonded together. The electronic components to be bonded are bonded under pressure at a high temperature higher than the melting temperature of the molten metal, and then the molten metal and the electronic components to be bonded are bonded under pressure for a certain period of time at a temperature lower than the melting temperature of the molten metal and at the melting temperature. The electronic component is manufactured by maintaining the temperature at a temperature close to that of the conventional one, and then releasing the pressurized state to bring the temperature to room temperature.

本発明によれば、熔融金属が予熱されているので接着時
間が短かくて済む。
According to the present invention, since the molten metal is preheated, the bonding time can be shortened.

さらに接着後も一定時間加圧状態が維持されこの時温度
も熔融温度に近い状態にされるので、接着部が急冷され
ることがなく割れが入らないので十分安定な接着状態と
することが出来る。以下t図面を参照して実施例を説明
する。
Furthermore, since the pressurized state is maintained for a certain period of time even after bonding, and the temperature is kept close to the melting temperature, the bonded part is not rapidly cooled and cracks do not occur, making it possible to maintain a sufficiently stable bonded state. . Embodiments will be described below with reference to the drawings.

実施例 1 第1図は、支持台2上に配置されたAu突起電極6を有
する半導体素子3と、その電極6に相対する如く、配置
された表面(Sn)メッキ5されたりードフレーム4と
それらのものを加熱圧薮する加圧部1の相対配置断面図
である。
Embodiment 1 FIG. 1 shows a semiconductor element 3 having an Au protruding electrode 6 placed on a support base 2, a surface (Sn) plated frame 4 placed opposite to the electrode 6, and a board frame 4 thereon. FIG. 2 is a sectional view of the relative arrangement of a pressurizing section 1 that heats and presses objects.

この状態で、少くとも加圧部1のみを、又は、加圧部I
と、リードフレーム4を、又は、加圧部1と、銅リード
フレーム4と、半導体素子3を、Au−Sn共晶合金が
熔融しない温度の200午0に1秒間保持し、次いで加
圧部1を押し下げ、第2図の状態に保持し、これと同時
に、加圧部1の温度を、電流を流すことにより、金一錫
合金が完全に熔融する温度300qCに0.9秒保持す
ると、リードフレーム4上の錫メッキ5と、半導体素子
3の金突起電極6とで金一錫合金7が出来る。次いで、
加圧部の温度を200C0まで1.9砂かかって下げる
ことにより、金一錫合金7は、完全に凝固し、半導体素
子3とりードフレーム4との接続が得られ、次いで常温
まで冷却する。なお、この200qCまでの冷却は最初
の0.9砂でほぼ200午○近くまで冷却し、この20
0℃近くの状態を1秒間維持する。第3図には、この工
程の温度と時間の関係が示してある。
In this state, at least pressurizing part 1 or pressurizing part I
Then, the lead frame 4, or the pressurizing part 1, the copper lead frame 4, and the semiconductor element 3 are held at 200:00 for 1 second at a temperature at which the Au-Sn eutectic alloy does not melt, and then the pressurizing part 1 is pressed down and held in the state shown in Fig. 2, and at the same time, the temperature of the pressurizing part 1 is held for 0.9 seconds at 300 qC, the temperature at which the gold-tin alloy completely melts, by flowing an electric current. A gold-tin alloy 7 is formed by the tin plating 5 on the lead frame 4 and the gold protruding electrodes 6 of the semiconductor element 3. Then,
The gold-tin alloy 7 is completely solidified by lowering the temperature of the pressurized part to 200 C0 by applying 1.9 kg of sand, and the connection between the semiconductor element 3 and the lead frame 4 is obtained, and then it is cooled to room temperature. . In addition, this cooling to 200qC was done with the initial 0.9 sand to almost 200 qC, and this 20
Maintain the temperature near 0°C for 1 second. FIG. 3 shows the relationship between temperature and time in this process.

第4図には、この工程で接続を完了した半導体装置の断
面図が示してある。
FIG. 4 shows a cross-sectional view of the semiconductor device whose connections have been completed in this step.

実施例 2 本実施例は、半導体装置の封入ケースの封止方法を示し
たもので、第5図、第6図に示してある。
Example 2 This example shows a method for sealing an enclosure case for a semiconductor device, and is shown in FIGS. 5 and 6.

第5図には、加圧部11、セラミックケースベース12
、そのケースの内部メタライズ配線18、ボンディング
線16によりメタライズ配線18と接続されている半導
体素子17、外部リード19、ケースベース12の封止
部に設けられたAu層1 5、ケースの封止ふた1 3
及び封止金属層14の相対位置が示してある。本実施例
も、実施例1と、同一の工程を経れば、第6図に示した
如く、容易に封止済みの半導体装置が出来る。第6図の
封止部10は、第5図、金属層14,15の金一錫合金
である。尚、同一番号は同一のものを示す。以上、実施
例に示した如く、本発明で短時間に、容易に且つ、安定
した接続部が得られる。
FIG. 5 shows a pressurizing part 11, a ceramic case base 12
, the internal metallized wiring 18 of the case, the semiconductor element 17 connected to the metallized wiring 18 by the bonding wire 16, the external lead 19, the Au layer 15 provided in the sealing part of the case base 12, and the sealing lid of the case. 1 3
and the relative positions of the sealing metal layer 14 are shown. In this example, if the same steps as in Example 1 are followed, a sealed semiconductor device as shown in FIG. 6 can be easily obtained. The sealing part 10 in FIG. 6 is made of a gold-tin alloy of the metal layers 14 and 15 in FIG. In addition, the same number indicates the same thing. As shown in the embodiments above, the present invention allows a simple and stable connection to be obtained in a short time.

本発明は、実施例に示した丈でなく、他の電子部品の製
造にも適用できることは明らかである。
It is clear that the present invention can be applied to the manufacture of other electronic components other than those shown in the examples.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、加圧部、リードフレーム、半導体素子、支持
台の相対位置を示したそれぞれの断面図である。 第2図は、リードフレームと半導体素子を接続中の断面
図である。第3図は、加圧部の温度上昇と時間の関係図
である。第4図は、接続の終了した半導体装置の断面図
である。第5図は、半導体封入ケースの封入時のケース
ふたと、ケースベースと加圧部の相対位置の断面図であ
る。第6図は、封入の終了した半導体装置の断面図であ
る。1,11・・・加圧部、2・・・支持台、3,17
・・・半導体素子、4…リードフレーム、5…Snメッ
キ、6・・・Au突起電極、7,1 0・・・Au−S
n合金、12・・・セラミックケース、13・・・ケー
ス封止蓋、1 4・・・封止金属層、1 5・・・Au
層、1 6・・・ボンディング線、18・・・メタライ
ズ配線、19・・・外部リード。 第1図 第2図 第3図 第4図 多5図 第5図
FIG. 1 is a sectional view showing the relative positions of a pressurizing part, a lead frame, a semiconductor element, and a support base. FIG. 2 is a cross-sectional view of the lead frame and the semiconductor element being connected. FIG. 3 is a diagram showing the relationship between temperature rise of the pressurizing section and time. FIG. 4 is a cross-sectional view of the semiconductor device after the connection is completed. FIG. 5 is a cross-sectional view of the relative positions of the case lid, the case base, and the pressurizing part when the semiconductor enclosure case is sealed. FIG. 6 is a cross-sectional view of the semiconductor device after encapsulation. 1, 11... Pressure part, 2... Support stand, 3, 17
... Semiconductor element, 4... Lead frame, 5... Sn plating, 6... Au protruding electrode, 7,1 0... Au-S
n alloy, 12... Ceramic case, 13... Case sealing lid, 1 4... Sealing metal layer, 1 5... Au
Layer, 1 6... Bonding line, 18... Metallized wiring, 19... External lead. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 1 熔融金属を媒介とする接続を行なう電子部品の製造
方法において、前記熔融金属を熔融温度以下でかつ常温
以上の温度で予熱し、しかる後に前記熔融金属及び被接
着電子部品を前記熔融金属の熔融温度以上の高温にして
前記被接着電子部品を加圧接着し、しかる後に加圧状態
のままで一定時間前記熔融金属及び前記被接着電子部品
を前記熔融金属の熔融温度以下でかつ熔融温度に近い温
度に保持し、しかる後に加圧状態を解除して常温にする
ことを特徴とする電子部品製造方法。
1. In a method of manufacturing an electronic component in which connection is made using molten metal, the molten metal is preheated to a temperature below the melting temperature and above room temperature, and then the molten metal and the electronic component to be bonded are bonded to the molten metal. The electronic components to be bonded are bonded under pressure at a high temperature higher than the temperature, and then the molten metal and the electronic components to be bonded are bonded under pressure for a certain period of time at a temperature below the melting temperature of the molten metal and close to the melting temperature. A method for manufacturing an electronic component, characterized by maintaining the temperature at a certain temperature, and then releasing the pressurized state and bringing the temperature to room temperature.
JP49120505A 1974-10-18 1974-10-18 Electronic component manufacturing method Expired JPS609343B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP49120505A JPS609343B2 (en) 1974-10-18 1974-10-18 Electronic component manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49120505A JPS609343B2 (en) 1974-10-18 1974-10-18 Electronic component manufacturing method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP60263373A Division JPS61190954A (en) 1985-11-22 1985-11-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5146072A JPS5146072A (en) 1976-04-20
JPS609343B2 true JPS609343B2 (en) 1985-03-09

Family

ID=14787845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP49120505A Expired JPS609343B2 (en) 1974-10-18 1974-10-18 Electronic component manufacturing method

Country Status (1)

Country Link
JP (1) JPS609343B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2356140A1 (en) * 1972-11-09 1974-05-22 Cii Honeywell Bull DEVICE FOR SOLDERING INTEGRATED CIRCUIT PLATES TO A SUBSTRATE
JPS49133867A (en) * 1972-11-09 1974-12-23

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2356140A1 (en) * 1972-11-09 1974-05-22 Cii Honeywell Bull DEVICE FOR SOLDERING INTEGRATED CIRCUIT PLATES TO A SUBSTRATE
JPS49133867A (en) * 1972-11-09 1974-12-23

Also Published As

Publication number Publication date
JPS5146072A (en) 1976-04-20

Similar Documents

Publication Publication Date Title
JP3381601B2 (en) How to mount electronic components with bumps
JPS59500394A (en) Cast solder leads for semiconductor circuits without lead wires
JPS61154764A (en) Method of combining metal with structural member and combining material
US5011067A (en) Method for attaching a fuse wire to a lead frame
KR100343150B1 (en) Power semiconductor module with metal terminal, metal terminal manufacturing method of power semiconductor module, and power semiconductor module manufacturing method
JPS609343B2 (en) Electronic component manufacturing method
JPS6389313A (en) Molding of resin in mold for electronic component
JPS62169433A (en) Manufacture of semiconductor device
JP2966079B2 (en) Lead frame, semiconductor device using the same, and method of mounting semiconductor device
JPS6356705B2 (en)
JPH02177463A (en) Manufacture of ceramic-metal composite board
JP3827442B2 (en) Manufacturing method of semiconductor package
JP2716355B2 (en) Method for manufacturing semiconductor device
US5537739A (en) Method for electoconductively connecting contacts
JPS59993A (en) Method of bonding metal plate electrode
JP3279158B2 (en) Surface acoustic wave device
JP2986661B2 (en) Method for manufacturing semiconductor device
JP2870506B2 (en) Soldering method of work with bump
JP3705779B2 (en) Power device, manufacturing method thereof, and tin-based solder material
JPH05145004A (en) Manufacture of semiconductor device
JP2522738B2 (en) Ceramic package for semiconductor device and semiconductor device
JP2007142054A (en) Seal cover and its manufacturing method
JPH05144989A (en) Production of lead frame and method for bonding semiconductor element using the frame
JPH03296237A (en) Rear surface joining method of semiconductor chip for thermal conduction and semiconductor device using it
JPH01179346A (en) Manufacture of semiconductor device