JPS61190954A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61190954A JPS61190954A JP60263373A JP26337385A JPS61190954A JP S61190954 A JPS61190954 A JP S61190954A JP 60263373 A JP60263373 A JP 60263373A JP 26337385 A JP26337385 A JP 26337385A JP S61190954 A JPS61190954 A JP S61190954A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- semiconductor element
- section
- pressing
- pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、とくに半導体
素子の突起電極とリードフレームのリードとを加圧部（
ボンディングツール）で熔融合金金属を媒介として接続
する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and in particular, to connect protruding electrodes of a semiconductor element and leads of a lead frame to a pressurizing portion (
This invention relates to a method of connecting using a molten alloy metal as an intermediary using a bonding tool.
これまでの電子部品の接続には、接着電子部品及び被接
着電子部品をあらかじめ常温で適正な位置に配置した後
荷重をかけて、圧接したり、爆接したりしていた。ある
いは荷重をか砂たままで、接着金属が熔融する迄高温に
保管し、その後、常温にする方法で電子部品の接続を得
ていた。これらの方法では、圧接、溶接部に、過大の負
荷がかかり、接続部に割れが入ったり、歪が残ったりす
る欠点や、高温保管状態が長すぎることや、接続部以外
が高温状態が長い為Ｋ。Conventionally, electronic components have been connected by placing the bonded electronic components and the electronic components to be bonded in appropriate positions at room temperature in advance, applying a load, and pressing or explosively welding them. Alternatively, electronic components were connected by leaving the load as sand and storing it at a high temperature until the adhesive metal melted, and then bringing it to room temperature. These methods have disadvantages such as excessive loads being applied to the pressure welding and welding parts, resulting in cracks or distortions in the joints, high temperature storage for too long, and high temperatures in areas other than the joints for a long time. Tame K.
劣化したり、長時間、高温状態に保管できない場合など
Ｋは使用できない欠点を有していた。K has disadvantages that make it unusable, such as when it deteriorates or cannot be stored at high temperatures for long periods of time.
本願発明は上記欠点を考えてこれを除去した方法を提供
することを目的とする。The present invention aims to provide a method that eliminates the above drawbacks.
本発明は半導体素子に設けられた突起電極とる半導体装
置の製造方法において、前記加圧部により加圧する前に
、前記リードと前記突起電極のそれぞれの表面金属によ
り成る接続部金属の熔融温度より低い温度でかつ常温よ
シ高い温度で該リード、該突起電極を、予熱しておき、
次に該加圧部処より該リードと該突起電極とを加圧し、
かつ一定時間該熔融温度以上とし、次に加圧を維持した
まま一定時間該熔融温度以下でかつ常温よりも高い温度
に維持し、しかる後に除圧して該接続部を常温まで下げ
ることを特徴とする半導体装置の製造方法である。The present invention provides a method for manufacturing a semiconductor device using a protruding electrode provided on a semiconductor element, in which the melting temperature of the connecting portion metal formed by the surface metal of each of the lead and the protruding electrode is lower than the melting temperature of the surface metal of each of the lead and the protruding electrode before applying pressure by the pressure applying section. Preheating the lead and the protruding electrode at a temperature higher than room temperature,
Next, pressurize the lead and the protruding electrode from the pressurizing part,
and above the melting temperature for a certain period of time, then maintain the temperature below the melting temperature and higher than room temperature for a certain period of time while maintaining pressure, and then remove the pressure and lower the connection part to room temperature. This is a method for manufacturing a semiconductor device.
以下に図面を参照して災施例を説明する。A disaster example will be described below with reference to the drawings.
実施例
第１図は、支持台２上に配置されたＡｕ突起電極６を有
する半導体素子３と、その電極６に相対する如く、配置
された表面錫（Ｓｎ）メッキ５されたリードフレームの
リード４とそれらのものを加熱圧接する加圧部（ボンデ
ィングツール）１の相対配置断面図である。この状態で
、加圧部１と、銅リードフレーム４と、半導体素子３を
、Ａｕ−Ｓｎ共晶合金が熔融しない温度の２００℃に１
秒間保持し、次いで加圧部１を押し下げ゛、第２図の状
態に保持し、これと同時に加圧部ｌの温度を、この加圧
部に電流を流すことにより、金−錫合金が完全く熔融す
る温度３００℃に０．５秒保持すると、リードフレーム
４上の錫メッキ５と、半導体素子３の全突起電極６とで
金−錫合金７が出来る。Embodiment FIG. 1 shows a semiconductor element 3 having an Au protruding electrode 6 placed on a support base 2, and a lead of a lead frame whose surface is plated with tin (Sn) 5 placed so as to face the electrode 6. FIG. 4 is a sectional view of the relative arrangement of a pressurizing part (bonding tool) 1 that heats and presses these parts together. In this state, the pressurizing part 1, the copper lead frame 4, and the semiconductor element 3 are heated to 200°C, a temperature at which the Au-Sn eutectic alloy does not melt.
2 seconds, then press down the pressure part 1 and hold it in the state shown in Fig. 2. At the same time, the temperature of the pressure part 1 is changed by passing a current through this pressure part until the gold-tin alloy is completely heated. When held at a melting temperature of 300° C. for 0.5 seconds, a gold-tin alloy 7 is formed by the tin plating 5 on the lead frame 4 and all the protruding electrodes 6 of the semiconductor element 3.
次いで、加圧部の温度を２００℃まで１．５秒かかりて
下げることＫより、加圧したまま金−錫合金７は、完全
く凝固し、半導体素子３とリードフレーム４との接続が
得られ、次いで加圧部を上げることＫより除圧して常！
まで冷却する。Next, by lowering the temperature of the pressurized part to 200°C in 1.5 seconds, the gold-tin alloy 7 completely solidifies while being pressurized, and the connection between the semiconductor element 3 and the lead frame 4 is established. Then, raise the pressurized part and release the pressure!
Cool until cool.
第３図には、この工程の温度と時間の関係が示しである
。この冷却は同図に示すように最初の０．５秒でほぼ２
００℃近くまで冷却し、この２００℃近くの状態を１秒
間維持する。FIG. 3 shows the relationship between temperature and time in this process. As shown in the figure, this cooling takes place approximately 2 times in the first 0.5 seconds.
Cool to near 00°C and maintain this state near 200°C for 1 second.
以上、実施例に示した如く、本発明で短時間に１容易に
且つ、安定した接続部が得られる。As shown in the examples above, the present invention allows a simple and stable connection to be obtained in a short time.
第１図は、加圧部、リードフレーム、半導体素子、支持
台の相対位置を示したそれぞれの断面図である。
第２図は、リードフレームと半導体素子を接続中の断面
図である。
第３図は、加圧部の温度上昇と時間の関係図である。
第４図は、接続の終了した半導体装置の断面図である。
ｌは加圧部、２は支持台、３は半導体素子、４はリード
フレーム、５はＳｎメ、キ、６は人Ｕ突起電極、７はＡ
ｕ−Ｓｎ合金である。
２Ｊ＋ 巳
第 ２ 図FIG. 1 is a sectional view showing the relative positions of a pressurizing part, a lead frame, a semiconductor element, and a support base. FIG. 2 is a cross-sectional view of the lead frame and the semiconductor element being connected. FIG. 3 is a diagram showing the relationship between the temperature rise of the pressurizing section and time. FIG. 4 is a cross-sectional view of the semiconductor device after the connection is completed. 1 is a pressurizing part, 2 is a support base, 3 is a semiconductor element, 4 is a lead frame, 5 is Sn metal, 6 is a human U protrusion electrode, 7 is A
It is a u-Sn alloy. 2J+ Snake 2nd figure
Claims (1)
ードとをブロック状の加圧部により加圧しかつ加熱する
ことにより接着する半導体装置の製造方法において、前
記加圧部により加圧する前に、前記リードと前記突起電
極のそれぞれの表面金属により成る接続部金属の熔融温
度より低い温度でかつ常温より高い温度で該リード、該
突起電極を予熱しておき、次に該加圧部により該リード
と該突起電極とを加圧し、かつ一定時間該熔融温度以上
とし、次に加圧を維持したまま一定時間該熔融温度以下
でかつ常温よりも高い温度に維持し、しかる後に除圧し
て該接続部を常温まで下げることを特徴とする半導体装
置の製造方法。In a method for manufacturing a semiconductor device in which a protruding electrode provided on a semiconductor element and a lead of a lead frame are bonded together by applying pressure and heating using a block-shaped pressure section, the leads are The lead and the protruding electrode are preheated at a temperature lower than the melting temperature of the connecting portion metal and higher than room temperature, and then the pressure section is used to heat the lead and the protruding electrode. Pressure is applied to the protruding electrode, and the temperature is kept at or above the melting temperature for a certain period of time, and then the pressure is maintained at a temperature below the melting temperature and higher than room temperature for a certain period of time, and then the pressure is removed to close the connection part. A method for manufacturing a semiconductor device characterized by lowering the temperature to room temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60263373A JPS61190954A (en) | 1985-11-22 | 1985-11-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60263373A JPS61190954A (en) | 1985-11-22 | 1985-11-22 | Manufacture of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49120505A Division JPS609343B2 (en) | 1974-10-18 | 1974-10-18 | Electronic component manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61190954A true JPS61190954A (en) | 1986-08-25 |
| JPS6356705B2 JPS6356705B2 (en) | 1988-11-09 |
Family
ID=17388587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60263373A Granted JPS61190954A (en) | 1985-11-22 | 1985-11-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61190954A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
-
1985
- 1985-11-22 JP JP60263373A patent/JPS61190954A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6356705B2 (en) | 1988-11-09 |
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