JPS6092832U - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS6092832U
JPS6092832U JP1983186277U JP18627783U JPS6092832U JP S6092832 U JPS6092832 U JP S6092832U JP 1983186277 U JP1983186277 U JP 1983186277U JP 18627783 U JP18627783 U JP 18627783U JP S6092832 U JPS6092832 U JP S6092832U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
lead
hybrid integrated
semiconductor pellets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983186277U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0142344Y2 (enrdf_load_stackoverflow
Inventor
成田 万紀
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP1983186277U priority Critical patent/JPS6092832U/ja
Publication of JPS6092832U publication Critical patent/JPS6092832U/ja
Application granted granted Critical
Publication of JPH0142344Y2 publication Critical patent/JPH0142344Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
JP1983186277U 1983-11-30 1983-11-30 混成集積回路装置 Granted JPS6092832U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983186277U JPS6092832U (ja) 1983-11-30 1983-11-30 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983186277U JPS6092832U (ja) 1983-11-30 1983-11-30 混成集積回路装置

Publications (2)

Publication Number Publication Date
JPS6092832U true JPS6092832U (ja) 1985-06-25
JPH0142344Y2 JPH0142344Y2 (enrdf_load_stackoverflow) 1989-12-12

Family

ID=30402394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983186277U Granted JPS6092832U (ja) 1983-11-30 1983-11-30 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS6092832U (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216167A (ja) * 1993-01-20 1994-08-05 Hitachi Ltd 半導体装置及びその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245056A (en) * 1976-09-27 1977-04-08 Gen Corp Integrated circuit and method of producing same
JPS58122763A (ja) * 1982-01-14 1983-07-21 Toshiba Corp 樹脂封止型半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245056A (en) * 1976-09-27 1977-04-08 Gen Corp Integrated circuit and method of producing same
JPS58122763A (ja) * 1982-01-14 1983-07-21 Toshiba Corp 樹脂封止型半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216167A (ja) * 1993-01-20 1994-08-05 Hitachi Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JPH0142344Y2 (enrdf_load_stackoverflow) 1989-12-12

Similar Documents

Publication Publication Date Title
JPS6092832U (ja) 混成集積回路装置
JPS6025159U (ja) リ−ドフレ−ム
JPS5878666U (ja) 混成集積回路装置
JPS6096846U (ja) 半導体集積回路装置
JPS6115746U (ja) 集積回路用パツケ−ジ
JPS6013737U (ja) 半導体集積回路装置
JPS5844871U (ja) 配線基板
JPS6059541U (ja) 集積回路用リ−ドフレ−ム
JPS5918430U (ja) クロスオ−バ配線を施した半導体チツプの実装構造
JPS60133668U (ja) プリント回路基板
JPS5991751U (ja) 樹脂封入型半導体集積回路装置
JPS5920643U (ja) 半導体装置
JPS60111064U (ja) ハイブリツドic用回路基板
JPS58187151U (ja) 高密度パツケ−ジ
JPS58166048U (ja) Icパツケ−ジ
JPS6054331U (ja) 半導体装置の実装基板
JPS587341U (ja) 半導体集積回路のパツケ−ジ
JPS5965563U (ja) プリント配線基板
JPS59106671U (ja) ハンダごてチツプ
JPS5952659U (ja) 混成集積回路
JPS58182458U (ja) 回路ユニツト
JPS58138344U (ja) チツプキヤリア
JPS58120647U (ja) 混成集積回路
JPS60137447U (ja) 半導体装置
JPS60149166U (ja) 混成集積回路装置