JPS6072281A - 発光ダイオ−ド基板 - Google Patents

発光ダイオ−ド基板

Info

Publication number
JPS6072281A
JPS6072281A JP58181303A JP18130383A JPS6072281A JP S6072281 A JPS6072281 A JP S6072281A JP 58181303 A JP58181303 A JP 58181303A JP 18130383 A JP18130383 A JP 18130383A JP S6072281 A JPS6072281 A JP S6072281A
Authority
JP
Japan
Prior art keywords
pattern
base
light emitting
emitting diode
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58181303A
Other languages
English (en)
Other versions
JPH0416027B2 (ja
Inventor
Toshihiko Ishii
俊彦 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP58181303A priority Critical patent/JPS6072281A/ja
Publication of JPS6072281A publication Critical patent/JPS6072281A/ja
Publication of JPH0416027B2 publication Critical patent/JPH0416027B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements
    • H01L33/642Heat extraction or cooling elements characterized by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 イ)産業上の利用分野 本発明はプリンタ用ヘッドに好適な発光ダイオード基板
に関する。
口)従来技術 従来比較的多数の発光ダイオードを基板に載置する時は
第1図に示すように基台(ハ)上の載置パターンに)上
に発光ダイオード(2)を載置していたが。
発光ダイオードに)は発光に伴って発熱するので、多く
の発光部な点灯させると過熱状態となり、輝度低下1発
光波長ずれ及び短寿命化を生じ好ましくない。中でもプ
リンタ用ヘッドとしての発光アレイに於いては発光部が
線分となるよう発光ダイオードに)を1〜4行の線状C
二装置する。従って中央部はど蓄熱し、部分的に上記欠
点を呈しや丁い。
しかもこのような場合、配線qIi度が高いので、載置
パターン2広げる争が出来ないし、ヒートパイプ等の放
熱手段は極端に高価で好ましくない。
ハ)発明の目的 本発明は発光ダイオードに対し場所による蓄熱量の均一
化(即ち発光輝度の場所に対する均一化)が行なえ、か
つ放熱特性も優Am発光ダイオード基板を提供するもの
である。
二)発明の構成 本発明は発光ダイオードが載置パターンに電気的にも熱
的にも低抵抗で接続されている躯に着目してなさTL7
Hもので、載置パターンに電気的にも熱的にも接続され
に下地パターンを設けるものである。以下本発明Y実施
例に基づいて詳細に説明する。
ホ)実施例 第2図は本発明実施例の発光ダ1オード基板の断面図で
ある。il+はセラミック等の基台で、 +21+31
(3)はメタライズさn定装置パターンと配線パターン
である。(4)は載置パターン(2)と電気的かつ熱的
に接続さTLに下地パターンで、基台(1)に埋め込ま
tl、rrものである。この下地パターン(4)は例え
ば基一台111Y製造する時Iニゲリーンシートに設け
らルた空隙部にはめ込まル、焼結後にスルホール等の手
法で載置パターン(2)と接続されるが、下地パターン
+41そのものは特にメタライズされていなくてもよい
。(5)は載置パターン(21上に導電性接着剤等で載
置固着され配線が施こさ几たGa入eP等の発光ダイオ
ードである。
第3図は同様に本発明の他の実施例2示す断面図である
が、基台(111として金属板又は耐熱樹脂板ン用いて
いる。下地パターンIのテぐ上に載置パターン任zン積
層して設けているが、下地パターン圓と配線パターンt
131 tl3)は絶縁層t161tlli)により設
けである0そしてこれらの載置パターンuz、配線パタ
ーン13 [31−下地パターン圓及び絶縁JvI圓四
は印刷法等により設けてもよい。
上述の例において下地パターン(4)圓は載置パターン
+21(121より光分大きい面積となって放熱効果ン
高めている。そしてプリンタ用ヘッド等においては載置
パターン[2+(13は帯状となるが、下地パターン(
4)圓は均熱部としても作用テるため、光分厚いか又は
広いことが望ましいが凸レンズ状の如く中央が周辺より
中広の形状となっていればより好ましい。
へ)発明の効果 以上の如く本発明は、基台上に設けらTLり載置パター
ンと、載置パターン上に載置同右さルz発光ダイオード
と、載置パターンの下方に載置パターンと電気的かつ熱
的に接続さTした載置パターンより面積の広い下地パタ
ーンとを具備した発光ダイオード基板であるから、放熱
性にflln、ているのみでなく均熱性も具備し1表面
の配線密度も高くできるので特に直線的に発光ダイオー
トン多く配置する場合等に好適である。
【図面の簡単な説明】
第1図は発光ダイオード基板の斜視図、第2図および第
6図は本発明実施例の発光ダイオード基板の断面図であ
る・ 111(Lll ・・・基台、 +2](121−・・
載置パターン、f3)+31(131u31.、。 配線パターン、 +41(141・・・下地パターン、
(51u51・・・R1ダイオード、 (1,6)(l
fil・・・絶縁層。

Claims (1)

  1. 【特許請求の範囲】 1)基台上に設けられ定装置パターンと、載置パターン
    上に載置固着されに発光ダイオードと。 載置パターンの下方に載置パターンと電気的かつ熱的に
    接続された載置パターンより面積の広い下地パターンと
    t具備したφを特徴とする発光ダイオード基板。 2)前記載置パターンは帯状乞なしており、前記発光ダ
    イオードは線状に配置さ几ている争’Y4?徴とする前
    記特許請求の範囲′5111項記載の発光ダイオード基
    板。
JP58181303A 1983-09-28 1983-09-28 発光ダイオ−ド基板 Granted JPS6072281A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58181303A JPS6072281A (ja) 1983-09-28 1983-09-28 発光ダイオ−ド基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58181303A JPS6072281A (ja) 1983-09-28 1983-09-28 発光ダイオ−ド基板

Publications (2)

Publication Number Publication Date
JPS6072281A true JPS6072281A (ja) 1985-04-24
JPH0416027B2 JPH0416027B2 (ja) 1992-03-19

Family

ID=16098315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58181303A Granted JPS6072281A (ja) 1983-09-28 1983-09-28 発光ダイオ−ド基板

Country Status (1)

Country Link
JP (1) JPS6072281A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62142665A (ja) * 1985-12-18 1987-06-26 Sanyo Electric Co Ltd 光プリンタヘツド
JP2003124528A (ja) * 2001-08-09 2003-04-25 Matsushita Electric Ind Co Ltd Led照明装置およびカード型led照明光源
WO2005008790A2 (de) * 2003-07-11 2005-01-27 Leising Guenther Leuchtdiode sowie led-lichtquelle
JP2014093463A (ja) * 2012-11-06 2014-05-19 Fuji Xerox Co Ltd 面発光型半導体レーザアレイ装置、光源および光源モジュール

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005158957A (ja) * 2003-11-25 2005-06-16 Matsushita Electric Works Ltd 発光装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62142665A (ja) * 1985-12-18 1987-06-26 Sanyo Electric Co Ltd 光プリンタヘツド
JP2003124528A (ja) * 2001-08-09 2003-04-25 Matsushita Electric Ind Co Ltd Led照明装置およびカード型led照明光源
WO2005008790A2 (de) * 2003-07-11 2005-01-27 Leising Guenther Leuchtdiode sowie led-lichtquelle
US8614456B2 (en) 2003-07-11 2013-12-24 Tridonic Optoelectronics Gmbh LED and LED light source
EP2398080A3 (de) * 2003-07-11 2014-04-23 Tridonic Jennersdorf GmbH Leuchtdiode sowie Leuchtdiode-Lichtquelle
JP2014093463A (ja) * 2012-11-06 2014-05-19 Fuji Xerox Co Ltd 面発光型半導体レーザアレイ装置、光源および光源モジュール

Also Published As

Publication number Publication date
JPH0416027B2 (ja) 1992-03-19

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