JPS6069766A - Interprocessor communication system - Google Patents

Interprocessor communication system

Info

Publication number
JPS6069766A
JPS6069766A JP17632583A JP17632583A JPS6069766A JP S6069766 A JPS6069766 A JP S6069766A JP 17632583 A JP17632583 A JP 17632583A JP 17632583 A JP17632583 A JP 17632583A JP S6069766 A JPS6069766 A JP S6069766A
Authority
JP
Japan
Prior art keywords
tcp
order
arf
control device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17632583A
Other languages
Japanese (ja)
Other versions
JPH0113140B2 (en
Inventor
Koichi Munakata
棟方　康一
Norio Sakai
堺　紀雄
Ryuzo Shimakage
島影　隆造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP17632583A priority Critical patent/JPS6069766A/en
Publication of JPS6069766A publication Critical patent/JPS6069766A/en
Publication of JPH0113140B2 publication Critical patent/JPH0113140B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To improve the flexibility to an increase in the number of commands by providing an anser request flag flip-flop (ARF) to a terminal controller. CONSTITUTION:When a central controller CC sends out an order to the terminal controller TCP, the CPU of the TCP returns an answer indicating the reception of the order to the CC. Once confirming that said order is received by the TCP, the CC scans the ARF of the TCP at a constant period. The TCP, on the other hand, executes the job specified by the order and starts an input/output device I/O according to the job. The CPU reads how many bytes are given to the command of said order and information for the result of the job or the extent of information, and adds byte length definition information to the data to generate answer data. This answer data is stored in a buffer register BUF to set ARF=1, and to shift to a standby state to read the data from the CC. The CC scans the ARF at a constant period and reads the answer data stored in the BUF when reading ARF=1.

Description

【発明の詳細な説明】 （技術分野） 本発明はプロセ、す間を低速パスで接続したゾロセッサ
間通信方式に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an inter-processor communication system in which processors are connected by a low-speed path.

（従来技術） 従来のゾロセッサ間通信方式は第１図に示す如く中央制
御装置ＣＣと複数の端末制御装置ＴＣＰとが低速パス５
ＰＢＵＳで接続され、前記端末制御装置ＴＣＰはプロセ
ッサＣＰＵと入出力装置Ｉ１０及びアンサデータを蓄積
するバッファレジスタＢＵＦで’Ｒ１）成される。中央
制御装置ＣＣと端末制御装置ｉＪ’ｒｃｐのゾロセッサ
間通信動作シーケンスを第２図に示す。(Prior art) In the conventional inter-sessor communication system, as shown in FIG.
Connected via PBUS, the terminal control device TCP is composed of a processor CPU, an input/output device I10, and a buffer register BUF for storing answer data. The communication operation sequence between the central controller CC and the terminal controller iJ'rcp is shown in FIG.

以下第１図と第２図を用いて動作を説明する。中央制御
装置ＣＣと端末制御装置ＴＣＰ間は前記中央制御装置Ｃ
Ｃが送出するオーダによりバイト数が定められておシ、
中央制御装置ＣＣから送出された所定のオーダを端末制
御装置ＴＣＰが受信すると、該端末制御装置ＴＣＰのプ
ロセッサＣＰＵは前記オーダを受信したことを中央制御
装置ＣＣに返送する。中央制御装置ＣＣは前記端末制御
装置ＴＣＰの応答で、送出したオーダが正しく受信され
たことを確認すると端末制御装置ＴＣＰ側のジョブ（Ｊ
ｏｂ）の大きさを認識し、該ジョブ実行に必要な時間の
計数を行う。The operation will be explained below using FIGS. 1 and 2. The central controller C is connected between the central controller CC and the terminal controller TCP.
The number of bytes is determined by the order sent by C.
When the terminal control device TCP receives a predetermined order sent from the central control device CC, the processor CPU of the terminal control device TCP returns a notification that the order has been received to the central control device CC. When the central controller CC confirms that the sent order has been correctly received in response to the terminal controller TCP, the central controller CC sends the job (J) on the terminal controller TCP side.
ob) and counts the time required to execute the job.

−実端末制御装置ＴＣＰは前記オーダに従ってジョブを
選択、実行し、該ジョブの結果又は情報をアンサデータ
としてバッファレジスタＢＵＦに記憶する。該アンサデ
ータの記憶を完了したバッファレジスタＢＵＦは中央制
御装置ＣＣ側からのアンザデータ読取シ待状態に移行す
る。中央制御装置ＣＣは送出したオーダで予め規定され
ている一定時間経過後、端末制御装置ＴＣＰに対してア
ンサデータの読取りを開始する。中央制御装置ＣＣはオ
ーダを送出する時にアンサデータのバイト数を予め認識
しているため必要量のアンザデータ読取シ動作を繰返す
ことになる。前述のような方式では中央制御装置ＣＣは
送出オーダに対するアンサデータのバイト数及び前記オ
ーダに対する端末制御装置ＴＣＰ側のジョブ実行時間を
総て認識しておかねばならない。これは新しいサービス
によるコマンド増への対応が難かしいという点と、端末
制御装置ＴＣＰから中央制御装置ＣＣに対して処理要求
ができないため中央制御装置ＣＣと端末制御装置ＴＣＰ
との機能分担が限定されてしまうという欠点があった。- The real terminal control device TCP selects and executes a job according to the order, and stores the result or information of the job as answer data in the buffer register BUF. The buffer register BUF, which has completed storing the answer data, shifts to a state in which it waits for the answer data to be read from the central control unit CC side. The central controller CC starts reading answer data from the terminal controller TCP after a certain period of time predefined in the sent order has elapsed. Since the central control unit CC recognizes the number of bytes of answer data in advance when sending out an order, it repeats the operation of reading the required amount of answer data. In the method described above, the central control unit CC must be aware of the number of bytes of answer data for a sending order and the job execution time on the terminal control unit TCP side for the order. This is because it is difficult to respond to the increase in commands due to new services, and because the terminal control device TCP cannot make processing requests to the central control device CC, the central control device CC and the terminal control device TCP
The disadvantage was that the division of functions between the two was limited.

（発明の目的） 本発明はかかる欠点に鑑みなされたもので、端末制御装
置にアンサリクエストフラグ・フリップフロップ（以下
ＡＲＰ回路という。）を設け、端末制御装置から中央制
御装置に対して処理要求を可能とし、才だアンサデータ
の中にコマンド及びバイト長定義情報を割付けることに
よりデータを可変長にし、更にクロスコマンド処理も可
能とするものである。以下図面を用いて発明の内容を詳
細に説明する。(Object of the Invention) The present invention has been made in view of the above drawbacks, and includes an answer request flag flip-flop (hereinafter referred to as an ARP circuit) in the terminal control device, and a process request from the terminal control device to the central control device. By allocating commands and byte length definition information in the answer data, the data can be made variable in length, and cross-command processing is also possible. The content of the invention will be explained in detail below using the drawings.

（発明の構成） 中央制御装置と複数の端末制御装置とを低速バスで接続
してデータの授受を行うゾロセ、す間通信において、要
求された処理の完了をアンサリクエストフラグを立てて
表示するＡＲＰ回路とアンサデータを蓄積するバッファ
レジスタを有する端末制御装置と、該端末制御装置の処
理完了を一定周期で走査することにより検出する中央制
御装置からなるプロセ、す間通信方式である。(Structure of the Invention) An ARP that displays the completion of a requested process by setting an answer request flag in inter-communication that connects a central control unit and a plurality of terminal control units via a low-speed bus to exchange data. This is a process-to-process communication system consisting of a terminal control device having a circuit and a buffer register for accumulating answer data, and a central control device that detects the completion of processing by the terminal control device by scanning at a constant cycle.

（実施例の説明） 第３図は本発明に係るプロセッサ間通信方式の回路（１
１′）成を示すブロック図である。端末制御装置ＴＣＰ
を一定周期で走査する機能を有する中央制御装置ＣＣと
複数の端末制御装置ＴＣＰとを低速パス５ＰＢＵＳで接
続し、前記端末制御装置ＴＣＰはプロセッサＣＰＵと、
入出力装置Ｉ１０と、アンサデータを蓄、債するバッフ
ァレジスタＢＵＦ及びアンサリクエストフラグを設定す
るＡＲＰ回路ＡＲＦ−ＦＦで構成する。(Description of Embodiment) FIG. 3 shows a circuit (1) of an inter-processor communication system according to the present invention.
1') is a block diagram showing the configuration. Terminal control device TCP
A central control unit CC having a function of scanning at a constant cycle and a plurality of terminal control units TCP are connected by a low-speed path 5PBUS, and the terminal control unit TCP is connected to a processor CPU,
It consists of an input/output device I10, a buffer register BUF for storing and transferring answer data, and an ARP circuit ARF-FF for setting an answer request flag.

第４図は本発明のプロセッサ間通信方式の動作シーケン
スを示す第１の実施例である。以下第３図と第４図によ
シ本発明の詳細な説明する。先ず中央制御装置ＣＣから
端末制御装置ＴＣＰに対してオーダを送出すると端末制
御装置ＴＣＩ）のプロセッサＣＰＵはオーダを受信した
旨の応答を中央制御装置ＣＣに返送する。中火制御装置
ＣＣは前記オーダを端末ｉｔｉ制御装置ＴＣＰが正しく
受信したことを確認すると該端末制御装置ＴＣＰのＡＲ
Ｆ回路ＡＲＰ　−ＦＦを一定周期で走査する。FIG. 4 is a first embodiment showing the operation sequence of the inter-processor communication system of the present invention. The present invention will be explained in detail below with reference to FIGS. 3 and 4. First, when an order is sent from the central control unit CC to the terminal control unit TCP, the processor CPU of the terminal control unit (TCI) returns a response indicating that the order has been received to the central control unit CC. When the intermediate fire control device CC confirms that the terminal control device TCP has correctly received the order, it sends the order to the AR of the terminal control device TCP.
F circuit ARP-FF is scanned at a constant cycle.

一方端末制御装置ＴＣＰはオーダによって指定されたジ
ョブを実行し、該ジョブに従って入出力装置■１０を起
動する。前記ジョブの結果または情報に対しプロセッサ
ＣＰＵは前記オーダのコマンド及び情報量が何バイトあ
るかを読取シバイト長定義情報をデータに旬月しアンサ
データを作成する。On the other hand, the terminal control device TCP executes the job specified by the order and activates the input/output device 10 according to the job. Regarding the result or information of the job, the processor CPU reads the command of the order and how many bytes of information there are, uses the byte length definition information as data, and creates answer data.

該アンサデータはバッファレジスタＢＵＦに記１．すし
、ＡＲＰ回路ＡＲＰ−ＦＦはＡＲＰ　＝　１を設定し、
中央制御装置ＣＣからのアンザデータ読取シ待状態に移
行する。The answer data is written in the buffer register BUF.1. Sushi, the ARP circuit ARP-FF sets ARP = 1,
Shifts to a state in which it waits to read answer data from the central control unit CC.

中央制御装置ＣＣばＡＲＰ回路ＡＲＰ−ＦＦを一定周期
で走査し、ＡＲＰ　＝　１を前記ＡＲＰ回路ＡＲＦ−Ｆ
Ｆから読Ｊ１ｖ、Ｚ）　（！：バッファレジスクＢＵＦ
に記憶したアンサデータの読取りを行う。読取ったアン
サデータシこはコマンド情報が旬月されているので中央
２ｂＵ御装置ＣＣは前記オーダに対する応答であること
を知り、又コマンド・１青報の後に続くデータ量はデー
タに付加したバイト長定義情報に従って知ることができ
る。The central control unit CC scans the ARP circuit ARP-FF at a constant cycle, and sets ARP=1 to the ARP circuit ARF-F.
Reading from F J1v, Z) (!: Buffer Regisc BUF
Reads the answer data stored in the . Since the command information in the read answer data file is marked, the central 2bU control unit CC knows that it is a response to the above order, and the amount of data that follows the command/1 blue report is the byte length added to the data. It can be known according to the definition information.

第５図は本発明の第２の実施例である。端末制御装置Ｔ
ＣＰの入出力装置Ｉ１０より処理要求が発生した場合前
記端末制御装置ＴＣＰのプロセッサＣＰＵノ命令でバッ
ファレジスタＢＵＦに処理要求コマンド、データ及びバ
イト長定義情報から成るアンサデータを蓄積する。前記
バッファレジスタＢＵＦ　Ｋ前記アンサデータを蓄積後
、ＡＲＦ回路ＡＲＦ　−ＦＦはＡＲＦ　＝　１を設定す
る。中央制御装置ＣＣはＡＲＦ回路ＡＲＦ−ＦＦを一定
周期で走査し、ＡＲＰ　＝　１を検出し、端末制御装置
ＴＣＰのプロセッサＣＰＵから処理要求が発生したこと
を知る。FIG. 5 shows a second embodiment of the invention. Terminal control device T
When a processing request is generated from the input/output device I10 of the CP, the processor CPU of the terminal control device TCP stores answer data consisting of a processing request command, data, and byte length definition information in the buffer register BUF. After accumulating the answer data in the buffer register BUFK, the ARF circuit ARF-FF sets ARF=1. The central control unit CC scans the ARF circuit ARF-FF at regular intervals, detects ARP=1, and learns that a processing request has been issued from the processor CPU of the terminal control unit TCP.

（発明の効果） 以上説明した如く本発明によれば、中央制御装置は端末
制御装置を一定周期で走査し、ＡＲＰ　＝　１を検出し
てアンサデータを読取るのでオーダに対してバイト長及
び端末制御装置が行うジョブ実行時間の認識が不要とな
る。従ってコマンド増に対する融通性が良く、新サービ
スへの適用が容易となる。又端末制御装置から処理要求
が出せることにより前記端末制御装置への機能分担の制
限が緩和される。更にコマンド情報をデータに含寸ぜる
ことによシフロスコマンド処理か可能であるなど多くの
利点を有する。(Effects of the Invention) As explained above, according to the present invention, the central control unit scans the terminal control unit at a constant cycle, detects ARP = 1, and reads the answer data, so the byte length and terminal control are determined according to the order. There is no need for the device to recognize the job execution time. Therefore, it has good flexibility for increasing commands and can be easily applied to new services. Furthermore, by allowing the terminal control device to issue a processing request, restrictions on the division of functions to the terminal control device are relaxed. Furthermore, it has many advantages, such as the ability to process syphros commands by including command information in the data.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のプロセッサ間通信方式のブ１コック図、
第２図は従来のプロセ、す間通信動作シーケンスの説明
図、第３図は本発明に係るプロセッサ間通信方式のブロ
ック図、第４図は本発明の第１の実施例を示すプロセッ
サ間通信動作シーケンスの説明図、第５図は本発明の第
２の実施例を示すプロセッサ間通信動作シーケンスの説
明図である。 ＣＣ・・中央制御装置、ＴＣＰ・・・端末制御装置、５
ＰＢＵＳ・・低速バス、ＣＰＵ・・・プロセッサ、Ｉｌ
ｏ　−入出力装置、ＢＵＦ・・バッファレジスタ、ＡＲ
Ｆ−ＦＦ・・・アンザリクエストフラグフリッゾフロッ
ゾ。 第２図 第 ５図 （ＴＣＰ）Figure 1 is a block diagram of the conventional inter-processor communication system.
FIG. 2 is an explanatory diagram of a conventional inter-processor communication operation sequence, FIG. 3 is a block diagram of an inter-processor communication method according to the present invention, and FIG. 4 is an inter-processor communication diagram showing a first embodiment of the present invention. FIG. 5 is an explanatory diagram of an inter-processor communication operation sequence showing a second embodiment of the present invention. CC: Central control device, TCP: Terminal control device, 5
PBUS...Low speed bus, CPU...Processor, Il
o - Input/output device, BUF...buffer register, AR
F-FF... Anza Request Flag Frizzo Frozzo. Figure 2 Figure 5 (TCP)

Claims (4)

【特許請求の範囲】[Claims] （１）　中央制御装置と複数の端末制御装置とを低速パ
スで接続してデータの授受を行うプロセッサ間通信にお
いて、要求された処理の完了を表示する手段とアンサデ
ータの蓄積手段を有する端末制御装置と、該端末制御装
置の処理完了を検出する検出手段を有する中央制御装置
からなることを特徴としたプロセッサ間通信方式。(1) Terminal control having means for displaying completion of requested processing and means for accumulating answer data in inter-processor communication in which a central control unit and a plurality of terminal control units are connected via a low-speed path to exchange data. 1. An inter-processor communication system comprising a central control device having a central control device and a detection means for detecting completion of processing by the terminal control device. （２）　アンサデータにコマンドとバイト長を定義した
ことを特徴とする特許請求の範囲第１項記載のプロセ、
す間通借方式。(2) The process according to claim 1, characterized in that a command and a byte length are defined in the answer data;
Interchange rental method. （３）中央制御装置から要求された処理の完了をアンサ
リクエストフラグで表示することを特徴とする特許請求
の範囲第１項記載のプロセッサ間通信方式。(3) The inter-processor communication system according to claim 1, characterized in that completion of processing requested by the central control unit is indicated by an answer request flag. （４）端末制御装置からの処理要求をアンプリクエスト
フラグで表示することを特徴とする特許請求の範囲第１
項記載のプロセッサ間通信方式。(4) Claim 1 characterized in that a processing request from a terminal control device is displayed with an amplifier request flag.
Inter-processor communication method described in section.
JP17632583A 1983-09-26 1983-09-26 Interprocessor communication system Granted JPS6069766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17632583A JPS6069766A (en) 1983-09-26 1983-09-26 Interprocessor communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17632583A JPS6069766A (en) 1983-09-26 1983-09-26 Interprocessor communication system

Publications (2)

Publication Number Publication Date
JPS6069766A true JPS6069766A (en) 1985-04-20
JPH0113140B2 JPH0113140B2 (en) 1989-03-03

Family

ID=16011607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17632583A Granted JPS6069766A (en) 1983-09-26 1983-09-26 Interprocessor communication system

Country Status (1)

Country Link
JP (1) JPS6069766A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007112156A (en) * 2005-10-17 2007-05-10 Toyota Motor Corp Braking control device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489455A (en) * 1977-12-27 1979-07-16 Toshiba Corp Control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489455A (en) * 1977-12-27 1979-07-16 Toshiba Corp Control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007112156A (en) * 2005-10-17 2007-05-10 Toyota Motor Corp Braking control device

Also Published As

Publication number Publication date
JPH0113140B2 (en) 1989-03-03

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