JPS6066861A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6066861A JPS6066861A JP17536483A JP17536483A JPS6066861A JP S6066861 A JPS6066861 A JP S6066861A JP 17536483 A JP17536483 A JP 17536483A JP 17536483 A JP17536483 A JP 17536483A JP S6066861 A JPS6066861 A JP S6066861A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- gate electrode
- electrode
- dirt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 37
- 239000007772 electrode material Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 235000009508 confectionery Nutrition 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- BVKZGUZCCUSVTD-UHFFFAOYSA-L Carbonate Chemical compound [O-]C([O-])=O BVKZGUZCCUSVTD-UHFFFAOYSA-L 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- -1 Si2 film Chemical compound 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に微細なMO
8型半導体装置の製造方法に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing an 8-type semiconductor device.
従来のMO3型トランノスタでは微細化がitむにつれ
、ドレイン領域近傍のチャネル領域で電界集中が起こり
、アバランンエ現象により発生したホットキャリア(%
にNチャネルトランノスタの場合のホットエレクトロ/
)がダーr−rqi。As the conventional MO3 type transnostar becomes smaller, electric field concentration occurs in the channel region near the drain region, and hot carriers (%) generated due to the avalanche phenomenon occur.
In the case of N-channel transnostar, hot electro/
) is da r-rqi.
圧によりダート絶縁膜中に注入されてドラッグされ易く
なるだめ、しきい値電圧のシフトなど、信頼性上重大な
問題を引き起こす。このような問題は微細化に対して大
きな障害となる。The dirt is easily injected into the insulating film and dragged due to the pressure, causing serious reliability problems such as a shift in threshold voltage. Such problems pose a major obstacle to miniaturization.
そこで、ホットエレイ′トロンの問題を解消−ノ′るた
めに、いわゆるLDD (Lightly Doped
I)rain−8ource)構造が提案されている
(例えば、S。Therefore, in order to solve the problem of hot array trons, so-called LDD (Lightly Doped
I) rain-8source) structures have been proposed (e.g., S.
Ogura et al、、 Trans、Elec、
l)e v 、 + El)−27(1980)135
9)。Ogura et al., Trans. Elec.
l) e v , + El) -27 (1980) 135
9).
こうしたLDDg造のへ10Sトランノスタの製造方法
の一例を第1図を8照して説明する。nず、例えばP型
シリコン基板l上にダート酸化膜2を介してダート電極
3を形成し7だイA1グ〜l”lli極3をマスクとし
てN型不純物を低ドーズ量でイオン注入する。次に、全
面に例えばCVD酸化膜を堆積した後、反応性イオンエ
ツチングによりダート電極3の側壁に残存CVD酸化膜
4,4を形成し、ダート電極3及び残存CVD酸化膜4
4をマスクとしてN型不純物を高ドーズ量でイオン注入
する。次いで、熱処理によシネMJ物を拡散させて、チ
ャネル領域近傍の低濃度のn−型不純物領域5a、6a
とこれらの領域に瞬接する高濃度のn型不純物領域5b
、6bとからなるソース、ドレイン領域5,6を形成す
る。An example of a method for manufacturing such a 10S transnostar made of LDDg will be explained with reference to FIG. First, a dirt electrode 3 is formed on, for example, a P-type silicon substrate 1 via a dirt oxide film 2, and N-type impurities are ion-implanted at a low dose in seven days using the electrode 3 as a mask. Next, after depositing, for example, a CVD oxide film on the entire surface, residual CVD oxide films 4, 4 are formed on the side walls of the dirt electrode 3 by reactive ion etching.
Using No. 4 as a mask, N-type impurities are ion-implanted at a high dose. Next, the cine MJ material is diffused by heat treatment to form low concentration n-type impurity regions 5a and 6a near the channel region.
and a high concentration n-type impurity region 5b that is in instant contact with these regions.
, 6b are formed.
この構造ではチャネル領域近傍のドレイン領域6が低濃
度のn−型不純物領域6aで構成されているため、逆バ
イアスされたドレイン−11合での′「(を界が緩和さ
れ、ホットエレクトロンが発生しにくい。In this structure, since the drain region 6 near the channel region is composed of a lightly doped n-type impurity region 6a, the field of It's hard to do.
しかし、従来のLDD構造では、特にインバータ回路等
のように電流の流れる方向が一定しているトランジスタ
において、ドレイン領域6側と対称的に形成されたソー
ス領域5側の低濃度のn−型不純物領域5aがノート抵
抗の上昇によって増幅率gを低下させるだけで何らメリ
ットをもたらさないという問題がある。However, in the conventional LDD structure, especially in a transistor in which the direction of current flow is constant, such as in an inverter circuit, a low concentration n-type impurity is added to the source region 5 side, which is formed symmetrically to the drain region 6 side. There is a problem in that the region 5a only lowers the amplification factor g due to an increase in note resistance, but does not bring any benefit.
このため、ソース、ドレイン領域の低12I4度不純物
領域の寸法を任意に制御し得る技術が要望されている。Therefore, there is a need for a technology that can arbitrarily control the dimensions of the low 12I4 degree impurity regions in the source and drain regions.
一方、菓子の微細化に対しては現在の光露光による写真
蝕刻法で対応することも内側となっている。すなわち、
光露光によって線@数千X以下のホトレジストパターン
を形成することは極めて田畑であり、写真蝕刻法により
例えば倣細なダート電極を形成しようとすると、露光の
過不足によりダート電極の寸法が増減し、例えば短チヤ
ネル効果によるしきい値゛111、圧の変動というよう
な問題が生じる。On the other hand, the current photo-etching method using light exposure is also being used to miniaturize confectionery. That is,
It is extremely difficult to form a photoresist pattern with lines of less than a few thousand square meters by light exposure, and if you try to form, for example, a fine dirt electrode by photolithography, the dimensions of the dirt electrode will increase or decrease due to overexposure or underexposure. For example, problems such as threshold value 111 and pressure fluctuations due to short channel effects arise.
そこで、微細なダート電極を形成する/こめに、例えば
第2図(a)及び(b)に示すような方法が報告されて
いる。まず、例えばP型シリコン屑板1ノ上に例えばC
VD酸化膜12を堆積した後、菓子領域の一部が露出す
るようにCVD 酸化1iQ 12 k選択的にエツチ
ング除去する。次に、露出した素子領域表面にゲート酸
化膜13を形成する。Therefore, a method as shown in FIGS. 2(a) and 2(b), for example, has been reported for forming fine dart electrodes. First, for example, on a P-type silicon scrap plate 1,
After depositing the VD oxide film 12, the CVD oxide 1iQ 12k is selectively etched away so that a portion of the confectionery region is exposed. Next, a gate oxide film 13 is formed on the exposed surface of the element region.
つづいて、全面に例えば多結晶シリコン膜14(図中破
線で図示)を堆積した後、異方性エツチングによシ多結
晶シリコン膜ノ40ジャストエツチング以上の時間エツ
チングし、cvoH化膜ノ化膜側2に非対称形のダート
電極15を形成する(第2図(、)図示)。次いで、前
記CVO酸化膜12を除去した後、ゲート電極15をマ
スクとしてn型不純物をイオン注入し、熱処理を行って
n型ンース、ドレイン領域16.17f形成する(同図
(b)図示)。Subsequently, after depositing, for example, a polycrystalline silicon film 14 (indicated by a broken line in the figure) on the entire surface, the polycrystalline silicon film is etched by anisotropic etching for a time of 40 minutes or more, and the CVOH film is etched. An asymmetric dart electrode 15 is formed on the side 2 (as shown in FIG. 2(a)). Next, after removing the CVO oxide film 12, n-type impurities are ion-implanted using the gate electrode 15 as a mask, and heat treatment is performed to form n-type source and drain regions 16 and 17f (as shown in FIG. 4B).
上記方法では写真蝕刻技術はCVDM化膜ノ化膜上2チ
ングの際に使用されるだけであり、ゲート電極15の寸
法は多結晶シリコン膜14の膜厚と異方性エツチングの
エツチング時間によって決定される。したがって、露光
の過不足はCVD 酸化膜12の側壁の位置をわずかに
左右させるだけで、ダート電極15の寸法には影響を与
えず、r )電極15を微細化することができる。In the above method, the photolithography technique is only used when etching the CVDM film, and the dimensions of the gate electrode 15 are determined by the thickness of the polycrystalline silicon film 14 and the etching time of the anisotropic etching. be done. Therefore, overexposure or underexposure only slightly changes the position of the side wall of the CVD oxide film 12, but does not affect the dimensions of the dirt electrode 15, and r) the electrode 15 can be miniaturized.
しかし、上記方法ではドレイ/領域17近賛のチャネル
領域における電界集中によるホットエレクトロンの発生
を防止することはできず、しきい値電圧の変動などの問
題を引き起こすととに変わシはない。However, the above method cannot prevent the generation of hot electrons due to electric field concentration in the channel region near the drain/region 17, and still causes problems such as threshold voltage fluctuation.
本発明は上記事情に鑑みてなされたものであり、微細な
ダート電極を有し、しかもソース、ドレイ/領域の寸法
を適当に制御してドレイン領域近傍における電界集中と
ソース領域近傍における増幅率の低下を有効に防止でき
るMO8型半導体装置を製造し得る方/I!、:全提供
しようとするものである。The present invention has been made in view of the above circumstances, and has a fine dart electrode and appropriately controls the dimensions of the source and drain/regions to reduce electric field concentration near the drain region and amplification factor near the source region. Those who can manufacture MO8 type semiconductor devices that can effectively prevent degradation/I! ,: This is what we are trying to provide.
本願用1の発明の半導体装置の製コム方法は、半導体基
板の一47電型の素子領域」−に被119Sを堆積した
後、素子管を域の一部が露出するように該被膜の一部を
選択的にエツチング除去する工程と、露出した素子領域
表面にケ゛−ト絶縁I+’λ全ル成する工程と、全面に
ケ9−ト電極材料を堆積した後、異方性エツチングによ
り残存した被膜の側壁に非対称形のダート電極を形成す
る工程と、残存し/ζζ脱膜除去した後、ダート電極を
マスクとして利用し、素子領域と逆4電九2の不純物を
低ドーズ量でイオン注入する工程と、全面に絶縁膜を堆
積した後、異方性エツチングにより前記ケ゛−ト電極の
側壁に絶縁膜全残存させる工程と、ダート成極及びその
側壁に残存した絶縁膜をマスクとして利用し素子領域と
逆導電型の不純物を高ドーズ量でイオン注入する工程と
、熱処理により不純物を拡散させ、チャネル領域近傍の
低濃度不純物領域とこれらの領域に隣接する高濃度不純
物領域とからなるソース、ト°レイン領域を形成する工
程とを具備したことを%徴とするものである。The method for manufacturing a semiconductor device according to the invention of Application No. 1 includes depositing a coating 119S on one 47-electrode type element region of a semiconductor substrate, and then removing the coating so that a part of the region is exposed. A process of selectively etching away parts of the electrode, a process of completely forming a gate insulator I+'λ on the surface of the exposed element region, and a process of depositing a gate electrode material on the entire surface, and then anisotropic etching to remove the remaining gate electrode material. After the step of forming an asymmetrical dirt electrode on the side wall of the coated film and removing the remaining / a step of implanting, a step of depositing an insulating film on the entire surface and then anisotropic etching to leave the entire insulating film on the side wall of the gate electrode, and a step of dirt polarization and using the insulating film remaining on the side wall as a mask. A process of ion-implanting impurities of a conductivity type opposite to that of the device region at a high dose and diffusing the impurities through heat treatment creates a source consisting of a low-concentration impurity region near the channel region and a high-concentration impurity region adjacent to these regions. , and a step of forming a train region.
このような方法(〆こよれば、ケ゛−ト慮極を写真たl
j刻法を用いずに形成することができるので、r−)電
極を微細化することができる。また、ケ゛−ト電極の非
対称性を利用し、ケ゛−ト電儲材料あるいはその側壁に
残存させる絶紅膜の膜ノlや工、チング時fjJJを設
定することによりLl)D rig造のソース、ドレイ
ン領域の低ilu度不純物1與城を任意に制御すること
ができ2.。したがって、ホットエレクトロンの発生等
分有効に防止することができる等の効果を得ることがで
き、2答r−の微細化を達成することができる。This method (if you prefer, take a photo of the Kate consideration)
Since it can be formed without using the J-cutting method, the r-) electrode can be made finer. In addition, by taking advantage of the asymmetry of the gate electrode and setting fjJJ at the time of coating and cutting the red film remaining on the gate electrode material or its side wall, it is possible to 1. Low-intensity impurities in the drain region can be controlled arbitrarily; 2. . Therefore, effects such as being able to effectively prevent the generation of hot electrons can be obtained, and miniaturization of the 2-resistance r- can be achieved.
また、本願用2の発明の半導体装1dの製散方法は1.
半導体基板の一導電型の素子領域表面にゲート絶縁膜を
形成した後、全面に第1のケ゛−ト電極材料を堆積し、
素子領域上の第1のケ゛−ト電極材料の一部と露出させ
るように被j臭を残存させ、次に第2のケ゛−ト″市:
イ梶拐本[を堆村(しで異方性エツチングにより残存し
/こ被膜の側壁に第2のダート電極材料を残存烙せ、次
いで残fJ。Further, the method for manufacturing the semiconductor device 1d of the invention of the second aspect of the present application is as follows: 1.
After forming a gate insulating film on the surface of an element region of one conductivity type of a semiconductor substrate, a first gate electrode material is deposited on the entire surface,
The odor is left so as to expose a portion of the first gate electrode material on the element region, and then the second gate electrode material is exposed:
A second dirt electrode material is deposited on the sidewalls of the film by anisotropic etching, and then a second dirt electrode material is deposited on the sidewall of the film.
した被膜を除去した後、第1のゲート電極月科を異方性
エツチングによりエツチングして弁文・[称形のr−ト
電極を形成し、すJに本願用10)1″。After removing the coated film, the first gate electrode was etched by anisotropic etching to form a nominal r-shaped electrode.
明と同様にダート電極をマスクとする低ドース最のイオ
ン注入、ゲート亀使とそのjlll壁に残存させた絶縁
膜をマスクとする島1゛−ズ量のイオン注入及び熱処理
による不純物の拡散を行ないr=DD4H造のソース、
ドレイン領域を形成するものである。As in the prior art, low-dose ion implantation was performed using the dirt electrode as a mask, ion implantation was carried out in an island-sized amount using the insulating film left on the gate shell and its wall as a mask, and impurity diffusion was performed by heat treatment. Conduct r = DD4H source,
This forms a drain region.
こうした方法によれば、本願第1の発明とほぼ同様な効
果を得ることができる。According to such a method, substantially the same effect as the first invention of the present application can be obtained.
実力ll1例1
以下、本願第1の発明に係るP/IQs )ランノスタ
の製造方法を第3図(a) 〜(f)、第4図(a)
、 (b)、第5図(a) 、 (b) 、第6図及び
第7図を参照して説明する。Ability ll1 Example 1 Below, the method for manufacturing P/IQs) Lannostar according to the first invention of the present application is shown in Figs. 3(a) to (f) and Fig. 4(a).
, (b), FIGS. 5(a), (b), and FIGS. 6 and 7.
寸ず、P型シリコン基板21表面に選択酸化法によりフ
ィールド酸rヒ膜22を形成した後、全面にCVD H
化膜(被膜)23を堆積し、素子領域の一部が霧出する
ようにCVD酸化膜23の一部を反応付イオンエツチン
グ(RIE )にヨリ選択的にエツチング除去する。次
に、露出した集子領域表i」iiにケ゛−ト酸fヒ膜2
4を形成した後、全面に多結晶ソリコノ膜25を堆積す
る(第3図(a)図示)。つづいて、反応性イオンエツ
チング(RIE )により、多結晶シリコンI模25を
その膜厚のジャストエツチング以上の1時間エツチング
し、残存しているCVI) l教化膜23のij+1壁
に非対称形のダート電極26を形成する(同図(b)図
示)。つづいて、残存しているCVD酸化膜23及びダ
ート酸化膜24の露出している部分をフッ酸またはフン
化アンモニウムを用いてエツチング除去した後、ダート
電極26を・マスクと1〜て例えばAs を低ドーズ量
でイオン注入する(同図(c)図示)。After immediately forming a field oxide film 22 on the surface of the P-type silicon substrate 21 by selective oxidation, CVD H is applied to the entire surface.
A chemical film (film) 23 is deposited, and a part of the CVD oxide film 23 is selectively etched away using reactive ion etching (RIE) so that a part of the device region is exposed. Next, a carbonate film 2 is applied to the exposed collector region surface i"ii.
4, a polycrystalline silicon film 25 is deposited on the entire surface (as shown in FIG. 3(a)). Next, by reactive ion etching (RIE), the polycrystalline silicon I pattern 25 was etched for 1 hour beyond just etching of its film thickness, and the remaining CVI) was etched into an asymmetrical dirt on the ij+1 wall of the indoctrination film 23. An electrode 26 is formed (as shown in FIG. 3(b)). Subsequently, the exposed portions of the remaining CVD oxide film 23 and dirt oxide film 24 are etched away using hydrofluoric acid or ammonium fluoride, and then the dirt electrode 26 is etched using a mask and etched with, for example, As. Ion implantation is performed at a low dose (as shown in FIG. 3(c)).
次いで、全面にCVD^り化j換2zを堆積する(同図
(d)図示)。つづいて、反応性イオンエツチングによ
りCVD を変化膜27をそのIj%厚のツヤストエツ
チング以上の時間エツチングし、タート電極26の側壁
に残存CVD酸化欣27’、27’を形成する。つづい
て、デートηj、極26及び残存CVD e化膜27’
、27’をマスクとしてAS k 1i−711゜−ズ
量でイオン注入する(同図(e)図示)。つづいて、熱
処理により不純物を拡散させ、チイネル領域近傍のn−
型不純物領域28a、29a とこれらの領域に隣接す
るn十製不純物領域28b229bとからなるソースド
レイン領域28.29を形成する。つづいて、全面にP
SG膜30を堆積した後、コンタクトホール、? 1
、31を開孔する。つづいて、全面にAt膜を蒸着した
後、・ぞターニングしてAt配線s2,32を形成し、
nチャネルMO8)ランソスタを製造する(同図(f)
図示)。Next, CVD dichloromethane 2z is deposited on the entire surface (as shown in FIG. 4(d)). Subsequently, the CVD modified film 27 is etched by reactive ion etching for a time longer than the gloss etching of its Ij% thickness to form residual CVD oxide scum 27', 27' on the side wall of the starter electrode 26. Next, the date ηj, the pole 26 and the remaining CVD e-coated film 27'
, 27' as a mask, ions are implanted at an amount of AS k 1i-711° (as shown in FIG. 2(e)). Next, the impurities are diffused by heat treatment, and the n-
Source/drain regions 28 and 29 are formed of type impurity regions 28a and 29a and n0 type impurity regions 28b and 229b adjacent to these regions. Next, P on the whole page
After depositing the SG film 30, a contact hole, ? 1
, 31 are drilled. Subsequently, after depositing an At film on the entire surface, turning is performed to form At wirings s2 and 32,
n-channel MO8) Manufacture a lansostar ((f) in the same figure)
(Illustrated).
しかして上記方法、によれば、ゲート電極26を写真蝕
刻法を用いずに、反応性イオンエツチングにより形成し
ているので、その寸法を多結晶シリコン膜25の膜厚以
下に微細化することができる。However, according to the above method, since the gate electrode 26 is formed by reactive ion etching without using photolithography, the dimensions of the gate electrode 26 can be made smaller than the thickness of the polycrystalline silicon film 25. can.
1だ、基板2ノ上に堆積される各種の膜の膜厚とそのエ
ツチング時間を設定することによシ、グーl−電極26
の非対称性を利用してLDD構造のソース、ドレイン領
域28.29のn−型不純物領域28a、29aの寸法
を任意、に制御することができる。このこと?史に詳細
に説明する。1. By setting the film thickness and etching time of various films deposited on the substrate 2, the glue electrode 26
The dimensions of the n-type impurity regions 28a and 29a of the source and drain regions 28 and 29 of the LDD structure can be arbitrarily controlled by utilizing the asymmetry. this thing? History will be explained in detail.
い寸、第3図(a)図示のCVI) r+≧、化膜23
の膜厚をdos多結晶シリコン脱25の膜)lをrl、
同し1(d)図示のCVD 酸化膜27の脱J!’lを
(r2−「I)とし、同図(e)の工程におけるCVD
C12化11Q 27の反応性イオンエツチングに関
してはツヤストエツチング、すなわち平坦部分がちょう
ど除去さね−る必吸最小限のエツチング時間でのエツチ
ングを行なうものとする。(CVI shown in Fig. 3(a)) r+≧, chemical film 23
The film thickness of dos polycrystalline silicon film (25) l is rl,
Same 1(d) De-J of the CVD oxide film 27 shown in the figure! 'l is (r2-'I), and CVD in the process of (e) in the same figure
Regarding the reactive ion etching of C12 11Q27, it is assumed that bright etching is performed, that is, etching is carried out with the minimum necessary etching time so that the flat portions are not completely removed.
ここで、CVI)酸化膜23の膜厚か多結晶シリコン膜
25の膜厚より厚い場合、すなわちdo)rlの場合、
多結晶シリコン脱25を反応性−イオンエツチングによ
りエツチングしてダート電極26全形成する際、ノ11
.ストエツチングあるいに、少々のオーバーエツチング
であハ、げ、第4図(a)においてdl〉0となる。こ
の際、少k A−パーエツチングしてもチャネル長はほ
とんど変化しない。なお、第4図(a)ではCVD酸化
膜27の膜厚(r2 rl )> a、としている。そ
して、CVD 酸化11127のツヤストj−ッチング
全イゴなつと、エツチング後の形状は同図(b)のよう
になる。Here, in the case of CVI) which is thicker than the film thickness of the oxide film 23 or the film thickness of the polycrystalline silicon film 25, that is, in the case of do)rl,
When etching the polycrystalline silicon layer 25 by reactive ion etching to form the entire dart electrode 26, No. 11 is performed.
.. Stretching or a slight overetching results in dl>0 in FIG. 4(a). At this time, even if a small k A-par etching is performed, the channel length hardly changes. Note that in FIG. 4(a), the film thickness of the CVD oxide film 27 (r2 rl)>a. When the CVD oxidized 11127 is completely etched by gloss J-etching, the shape after etching becomes as shown in FIG. 2(b).
この場合、ドレイ/側の残存CVD酸化膜27′の横方
向の寸法(低濃度のn−型不純物領域の寸法に対応する
)LDはLo”” rz ’ rlsソース側の残存C
VD酸化膜27′の横方向の寸法LsはLs = 、、
、z−(rz rl a、 )2 rlとなる。In this case, the lateral dimension of the remaining CVD oxide film 27' on the drain/side (corresponding to the dimension of the lightly doped n-type impurity region) LD is Lo"" rz 'rls, the remaining C on the source side.
The lateral dimension Ls of the VD oxide film 27' is Ls = ,
, z−(rz rl a, )2 rl.
一方、do<rl あるいけ多結晶シリコン膜25をか
なりオーバーエツチングした場合、第5図(a)に示す
如(d、(0となる。そして、CVD酸化脱270ノヤ
ストエ、チングを行ナウト、エツチング後の形状は同図
(b)のようになる。この場合、rl>(l d+ H
−rz−rl)であれば、LD ”” rz −rl
+
となる。On the other hand, if the polycrystalline silicon film 25 is considerably over-etched, as shown in FIG. The subsequent shape is as shown in the same figure (b). In this case, rl>(l d+ H
-rz-rl), then LD "" rz -rl
+.
以上の結果にもとづいて、多結晶シリコン膜25の膜厚
r1−=5000X(チャネル長”s 0.5 μm)
、CVI)酸化膜27の膜厚(rz rl)==200
0Xとし、ソース側の残存CVD酸化yA27′の横方
向の寸法14.3をdlの関数として表わすと第6図中
の実線ノヨうKfzる。す’lbち、LD =r2−r
l””2000Xであるのに対してdl〉0の場合はり
、をそれほど短くすることができないが、dlくoの場
合はLsを100OX以下まで短くすることができる。Based on the above results, the film thickness of the polycrystalline silicon film 25 r1-=5000X (channel length "s" 0.5 μm)
, CVI) Film thickness of oxide film 27 (rz rl)==200
0X, and the lateral dimension 14.3 of the remaining CVD oxidized yA27' on the source side is expressed as a function of dl as shown by the solid line Kfz in FIG. S'lbchi, LD = r2-r
When dl>0, Ls cannot be made so short as compared to 2000X, but when dl>0, Ls can be shortened to 100OX or less.
なお、dlく0の場合は多結晶シリコン膜25のエツチ
ング時間を長くすれば、ダート電極26の寸法をよシ小
さくすることができるので微細化には有利であるが、エ
ツチング時間とともにチャネル長が変化するのでエツチ
ング時間は厳密に制御する必要がある。Note that when dl is 0, if the etching time of the polycrystalline silicon film 25 is increased, the dimensions of the dart electrode 26 can be further reduced, which is advantageous for miniaturization, but the channel length increases with the etching time. Since the etching time varies, the etching time must be strictly controlled.
更に、CVD酸化膜27を50%オーバーエツチングす
ればLsは第6図中破線で示すようになシ、才だ、10
0係オーバーエツチングすればLsは第6図中一点鎖線
で示すようになり、Lsを0とすることもできる。ただ
し、長時間のオー・ぐ−エツチングを行なう場合には基
板に対するCVD酸化膜のエツチングの選択的が大きく
なるようにエツチング条件を設定する必要がある。例え
ば、第7図に第5図(b)から更に50%オーバーエツ
チングした後の形状を示す。第7図ではソース側の残存
cvD酸化膜27′の横方向の寸法が非常に小さいので
、その下に形成されるソース領域28内のれ一型不純物
領域28aの寸法を小さくすることができる。第7図図
示のようなMOS トランジスタではソース側の直列抵
抗の増加をほとんど無視することができるので、インバ
ータ回路等のように電流の流れる方向が一定しているト
ランジスタでは増幅率Qmの低下を防止することができ
る。勿論、ドレイン領域29側のn−型不純物領域29
aによる耐ホツトエレクトロン性は従来のLDf) 、
?74’造と同、様に有している。Furthermore, if the CVD oxide film 27 is over-etched by 50%, Ls becomes 10 as shown by the broken line in FIG.
If 0-related overetching is performed, Ls will become as shown by the dashed line in FIG. 6, and Ls can also be set to 0. However, when long-term etching is performed, etching conditions must be set so that the CVD oxide film is etched more selectively with respect to the substrate. For example, FIG. 7 shows the shape after further over-etching by 50% from FIG. 5(b). In FIG. 7, since the lateral dimension of the remaining CVD oxide film 27' on the source side is very small, the dimension of the L-type impurity region 28a in the source region 28 formed thereunder can be made small. In a MOS transistor like the one shown in Figure 7, the increase in series resistance on the source side can be almost ignored, so in a transistor where the current flows in a constant direction, such as in an inverter circuit, a decrease in the amplification factor Qm can be prevented. can do. Of course, the n-type impurity region 29 on the drain region 29 side
The hot electron resistance due to a is that of conventional LDf),
? It has the same characteristics as the 74' construction.
なお、上記実施例1では第3図(a)の工程でCVD1
’jffi化$23のエツチングを行なった後、素子領
域表面にダート酸化膜24全形成しだが、これに限らず
、素子領域表面にダート絶縁膜を形成した後、ケ゛−ト
絶縁膜に対して選択エツチング性の大きい被膜を堆積し
、その一部を選択的にエツチングしてもよい。こうした
方法によれば被膜の反応性イオンエツチング時に基板表
面にダート絶縁膜が存在し、基板が露出していないので
、基板のダメーゾを防止することができる。In addition, in the above Example 1, the CVD 1 was
After performing the etching step 23, the entire dirt oxide film 24 is formed on the surface of the element region. A film with high selective etching properties may be deposited and a portion thereof may be selectively etched. According to this method, a dirt insulating film is present on the substrate surface during reactive ion etching of the film, and the substrate is not exposed, so that damage to the substrate can be prevented.
また、上記実施例1ではケ゛−ト″lTL極拐料として
多結晶シリコン膜25のみを用いたが、これに限らず、
ゲート電極拐料として例えば多結晶シリコン膜とMo
S i2膜のような高融点金属シリサイドとを用い、第
8図に示すように多結晶シリコン膜・やクー741とM
oSi2!を艷・ぞターフ42とが積層されたいわゆる
ポリサイド構造のダート電極43と形成してもより0こ
うした構造によれば、ダート電極43の比抵抗を低下す
ることができる。In addition, in the first embodiment, only the polycrystalline silicon film 25 was used as the substrate for the cathode 1TL, but the present invention is not limited to this.
For example, a polycrystalline silicon film and Mo
Using a high melting point metal silicide such as Si2 film, as shown in FIG.
oSi2! According to such a structure, the specific resistance of the dart electrode 43 can be lowered even if the dart electrode 43 is formed with a so-called polycide structure in which the turf 42 is laminated.
実施例2
以下、本願第2の発明に係るIViO8+−ランノスタ
の製造方法を嬉9図(a)〜(d)をム照して説明する
。Example 2 Hereinafter, a method for manufacturing IViO8+-lannostar according to the second invention of the present application will be explained with reference to Figures 9 (a) to (d).
まず、P型シリコン基板51表ii’riにフィールド
酸化膜52を形成した後、フィールド°敲イヒ1摸52
によって囲まれた素子領域表面にゲート酸化膜53を形
成し、更に全m1に多結晶シリコン膜(第1のケ゛−ト
電極材料)54を堆積する。次に、全面にCVD酸化膜
55を堆積した後、素子領域上の前記多結晶シリコン膜
54の一部が露出するように前記CVD酸化脱55の一
部を反応性イオンエツチング(4thg)により選択的
にエツチング除去する。First, after forming the field oxide film 52 on the surface of the P-type silicon substrate 51, the field oxide film 52 is
A gate oxide film 53 is formed on the surface of the element region surrounded by , and a polycrystalline silicon film (first gate electrode material) 54 is further deposited over the entire m1. Next, after depositing a CVD oxide film 55 on the entire surface, a part of the CVD oxidation film 55 is selected by reactive ion etching (4thg) so that a part of the polycrystalline silicon film 54 on the element region is exposed. Remove by etching.
つづいて、全面に例えばMOS i 2 III (第
2のダート電極イイ科)56を堆積する(第9図(a)
図示)。Subsequently, for example, MOS i 2 III (second dart electrode family) 56 is deposited on the entire surface (FIG. 9(a)).
(Illustrated).
つづいて、反応性イオンエツチングにより Mo S
j□膜56をその膜厚のジャストエツチング以上の時間
エツチングし、残存しているCVD(9)化膜55の側
壁にMo S i 2膜・ぞター156′を形成する(
同図(b)図示)。次いで、残存しているCVD酸化膜
55を除去した後、前記多結晶シリコン膜54を反応性
イオンエツチングによシエッチングし、多結晶シリコン
膜ノターン54’ トMO!l) 12 BHパターン
56′とを積層L/こ月eリザイド構造のケ9−ト電(
ヴ57を形成する。つづいて、ダート電極57をマスク
としてダートe化1換53の露出している部分をエツチ
ング除去する(同図(c)図示)。以下、上記実施例1
と同様にまず、ゲート′電極57をマスクとしてAs+
を低ドーズ量でイオン注入する。つづいて、全面にCV
D (H化膜を堆M シだ後−反応性イオンエツチング
によりダート電極57の側壁に残存CVD酸化%s8.
58を形成する。つづいて、ケ゛−ト電極57及び残存
CVD酸化膜58.58をマスクとしてAS を高ドー
ズ量でイオン注入した後、熱処理により不純物を拡散さ
せ、チャネル領域近傍のn−型不純物領域59a、60
thとこれらの領域に隣接する討型不純物領域59b、
60bとからなるソース、ドレイン領域59.60を形
成する。更に、PSG膜61の堆積、コンタクトホール
62 、62の開孔、At配線6 、? 、 63の形
成を行ないnチャネルMO3+・う/マスクを製造する
(同図(d)図示)。Next, by reactive ion etching, MoS
The J□ film 56 is etched for a time longer than the just etching time for its film thickness, and a MoSi 2 film 156' is formed on the side wall of the remaining CVD (9) film 55 (
Figure (b) shown). Next, after removing the remaining CVD oxide film 55, the polycrystalline silicon film 54 is etched by reactive ion etching to form a polycrystalline silicon film notation 54'. l) 12 BH pattern 56' is laminated with a gate electrode (
form V57. Subsequently, using the dirt electrode 57 as a mask, the exposed portion of the dirt e-condenser 53 is removed by etching (as shown in FIG. 3(c)). Below, the above Example 1
Similarly, first, As+ is applied using the gate' electrode 57 as a mask.
ions are implanted at a low dose. Next, the entire CV
D (After depositing the hydride film - Reactive ion etching removes residual CVD oxidation %s8. on the side wall of the dirt electrode 57.
form 58. Subsequently, AS is ion-implanted at a high dose using the gate electrode 57 and the remaining CVD oxide films 58 and 58 as masks, and then the impurities are diffused by heat treatment to form the n-type impurity regions 59a and 60 near the channel region.
th and a depressed impurity region 59b adjacent to these regions,
60b, source and drain regions 59 and 60 are formed. Furthermore, the PSG film 61 is deposited, the contact holes 62, 62 are opened, the At wirings 6, ? , 63 are formed to manufacture an n-channel MO3+ mask (as shown in FIG. 4(d)).
しかして、上記方法によっても」二記実施例】と同様に
ダート電極57を微細化でき、しかもLDD構造のソー
ス、ドレイン領域59.60のn−型不純物領域59g
、60aの寸法全制御することができ、耐ホ、トエレク
トロン性を維持しつつソース側の増幅率の低下を防止す
ることができる。Therefore, by the above method, the dart electrode 57 can be made finer in the same manner as in Embodiment 2, and moreover, the n-type impurity region 59g of the source and drain regions 59 and 60 of the LDD structure can be made fine.
, 60a can be completely controlled, and a decrease in the amplification factor on the source side can be prevented while maintaining resistance to electrons.
寸だ、第9図(a)の工程におけるCVD 酸化膜55
の反応性エツチング時に基板51は多結晶シ1ノコ/膜
54及びダート酸化膜53に覆われているため、基板5
1がダメージを受けることはない。CVD oxide film 55 in the process of FIG. 9(a)
During reactive etching, the substrate 51 is covered with the polycrystalline saw/film 54 and the dirt oxide film 53.
1 will not take any damage.
更に、実施例1の方法でポリサイド構造のダート電極を
形成した場合(第8図図示)と比較して、ゲート電極5
7のうち比抵抗の大きい多結晶シリコン膜・母ターン5
4′の占める部分を少なくすることができるので、ダー
ト電極57の低抵抗化に有利となる。一般的に第10ケ
゛−ト電極材料が第2のケ゛−ト電極材料より比抵抗が
大きい場合に実施例2の方法が有利となる。Furthermore, compared to the case where a dirt electrode with a polycide structure was formed by the method of Example 1 (as shown in FIG. 8), the gate electrode 5
Polycrystalline silicon film/mother turn 5 with high resistivity among 7
Since the portion occupied by 4' can be reduced, it is advantageous for lowering the resistance of the dart electrode 57. Generally, the method of Example 2 is advantageous when the tenth gate electrode material has a higher resistivity than the second gate electrode material.
なお、上記実施例2では第1のケ゛−ト電極材利として
多結晶シリコン膜、第2のデート電極旧料としてMoS
i 膜を用いたが、これに限らず他の拐料を用いてもよ
いし、第1及び第2のケゝ−ト電極材料が同−利料であ
ってもよい。In Example 2, a polycrystalline silicon film was used as the first date electrode material, and MoS was used as the second date electrode material.
Although the i film is used, the present invention is not limited to this, and other materials may be used, and the first and second gate electrode materials may be made of the same material.
また、上記実施例1及び2ではnチャネルMO8トラン
ジスタについて説明したが、PチャネルMO8トランジ
スタあるいidCMO8にも同様に適用できることけ勿
論である。Further, in the first and second embodiments described above, an n-channel MO8 transistor has been described, but it goes without saying that the present invention can be similarly applied to a P-channel MO8 transistor or an idCMO8 transistor.
以上詳述した如く、本発明の半導体装面の製造方法によ
れば、微細なゲート電イタを形成できるとともにLDD
構造のソース、ドレイン領域を制御性よく形成でき、素
子の1晟細化に極めて大きく寄力するものである。As detailed above, according to the method of manufacturing a semiconductor device surface of the present invention, it is possible to form a fine gate electrode and to
The source and drain regions of the structure can be formed with good controllability, which greatly contributes to the miniaturization of the device.
第1図は従来のLl)D Nrc造のMO8+・ランマ
スクの断面図、第2図(a)及び(b)は従来のMO3
t□ランジスタの製造方法を示す断面図、第3図(Il
)〜(f)は本発明の実施例1におけるMO8+−ラン
ソスクの製造方法を示す断面図、第4図(a) p (
b)及び第5図(a) 、 (b)は本発明の実施例J
で〜製造されるMO8)ランマスクの寸法を説1y1す
るだ、Vンの1説明図、第6図は本発明の実施例1で製
造されるMO3l−ランマスクの寸法の計算例を示−4
〜iW図、第7図及び第8図は本発明の変形例を示す断
面図、第9図(a)〜(d)は本発明の実施例2におけ
るMOS )ランノスクの製造方法を示す断面図である
。
21.51・・・P捜シリコン基板、22.52・・・
フィールド酸化膜、23.55・・・CVD j波化膜
(被膜)、24,53・・・ゲート酸化膜、25゜54
・・・多結晶シリコン膜、26,43.57・・・r−
)電極、27・・・CvD酸化j摸、27’ 、 5
B −・残存CVD酸化膜、28.59・・・ソース領
域、29.60・・・ドレイン領域、28a、29a。
59a、60a=・n−型不純物領域、28b。
29b、59b、60b−−−n型不純物領域、30.
61・・・PSG膜、31,62・・・コンタクトホー
ル、32.63・・・AA配線、41.54’・・・多
結晶/リコン膜・ぐターン、56・・・Mo S i
2膜、42H56’ ・・・MoSi21W) z’P
ターン。
出願人代理人 弁理士 鈴 工 武 診第 11”
第21昭
@3図
(d)
2
第3図
第4図
笥5図
第61¥I
ch(入)
第 71シ1
6
ro D
(’%Jr
)凸 の
へ 。Figure 1 is a cross-sectional view of a conventional Ll)D Nrc MO8+ run mask, and Figures 2 (a) and (b) are conventional MO3
t□ Cross-sectional view showing the method of manufacturing a transistor, FIG. 3 (Il
) to (f) are cross-sectional views showing the manufacturing method of MO8+-lansosc in Example 1 of the present invention, FIG. 4(a) p (
b) and FIGS. 5(a) and (b) are Example J of the present invention.
Figure 6 shows an example of calculating the dimensions of the MO3l-run mask manufactured in Example 1 of the present invention.
~iW Figures, Figures 7 and 8 are cross-sectional views showing modified examples of the present invention, and Figures 9 (a) to (d) are cross-sectional views showing a method for manufacturing a MOS (Rannosk) in Example 2 of the present invention. It is. 21.51...P silicon substrate, 22.52...
Field oxide film, 23.55...CVD J-wave conversion film (film), 24,53...Gate oxide film, 25°54
...Polycrystalline silicon film, 26,43.57...r-
) Electrode, 27... CvD oxidation model, 27', 5
B--Remaining CVD oxide film, 28.59... Source region, 29.60... Drain region, 28a, 29a. 59a, 60a = n-type impurity region, 28b. 29b, 59b, 60b---n type impurity region, 30.
61...PSG film, 31,62...contact hole, 32.63...AA wiring, 41.54'...polycrystalline/recon film/guttern, 56...Mo Si
2 films, 42H56'...MoSi21W) z'P
turn. Applicant's agent Patent attorney Suzu Ko Takeshi No. 11" No. 21 Sho @ Figure 3 (d) 2 Figure 3 Figure 4 Figure 5 Figure 61\I ch (in) No. 71 Si1 6 ro D ('% Jr.) Convex.
Claims (4)
した後、素子領域の一部が露出するように該被膜の一部
を選択的にエツチング除去する工程と、露出した素子領
域表面にダート絶縁膜を形成する工程と、全面にダート
電極材料を堆積した後、異方性エツチングによシ残存し
た被膜の側壁に非対称形のケ゛−ト電極を形成する工程
と、残存した被膜を除去した後、ダート電極をマスクと
して利用し、前記素子領域と通導/、IE型の不純物を
低ドーズ量でイオン注入する工程と、全面に絶縁膜を堆
積した後、異方性工。 チングにより1)ロ記ゲート電極の側壁に絶縁膜を残存
させる工程と、ダート電極及びその側壁に残存した絶縁
膜をマスクとして利用し素子領域と通導′K Nの不純
物を高ドーズ量でイオン注入する工程と、熱処理によυ
不純物を拡散させ、チャネル領域近傍の低濃度不純物領
域ととり、らの領域に隣接する高襄度不純物領域とから
なるソース、ドレイン領域を形成する工程とを具備した
ことを特徴とする半導体装置の製造方法。(1) After a film is deposited on an element region of one conductivity type of a semiconductor substrate, a part of the film is selectively etched away so that a part of the element region is exposed, and the surface of the exposed element region a step of forming a dirt insulating film on the surface of the substrate, a step of depositing a dirt electrode material on the entire surface, and then forming an asymmetric gate electrode on the side wall of the remaining film by anisotropic etching; After removal, using the dirt electrode as a mask, there is a step of conducting with the element region, and ion implantation of IE type impurities at a low dose. After depositing an insulating film on the entire surface, an anisotropic process is performed. 1) The step of leaving an insulating film on the sidewalls of the gate electrode as described in (b) and using the insulating film remaining on the dirt electrode and its sidewalls as a mask to ionize impurities in the element region and the conductive 'KN' at a high dose. The injection process and heat treatment
A semiconductor device comprising the step of diffusing impurities to form source and drain regions consisting of a low concentration impurity region near a channel region and a high concentration impurity region adjacent to these regions. Production method.
サイド、金属のうち少なくとも1釉であること?特徴と
する特許請求の範囲第1項記載の半導体装置の製造方法
。(2) Is the dirt electrode material at least one of polycrystalline silicon, gold IJK silicide, and metal glaze? A method for manufacturing a semiconductor device according to claim 1.
絶縁膜を形成した後、全面に第1のダート電極材料を堆
積する工程と、全面に被膜を堆積した後、素子領域上の
第1のダート・t+U極拐料の一部を露出させるようK
M H’Aの一部を選択的にエツチング除去する工程
と、全面に第2のダート電4夕材料を堆積した後、異方
性エツチングにより残存した被膜の側壁に第2のデート
’I’=i: イ=材料を残存させる工程と、残存した
被膜を除去した後、前記第1のダート電極材料を異方性
エツチングによりエツチングし、第J及び第2のダート
電極材料からなる非対称形のケ゛−) ’f(j 4(
1=を形成する工程と、り9−ト電極をマスクとして利
用し素子領域と逆導電型の不純物を低ドーズ量でイオン
注入する工程と、全面に絶縁膜を堆積した後、異方性工
、チ/グにより前記ケ9−ト電極の側壁に絶縁膜を残存
させる工程と、ゲート電極及びその側壁に残存した絶縁
膜をマスクとして利用し素子領域と逆導電型の不純物を
高ドーズ量でイオン注入する工程と、熱処理により不純
物を拡散させ、チャネル領域近傍の低濃度不純物領域と
これらの領域に@接する高濃度不純物領域とからなるソ
ース、ドレイン領域を形成する工程と4具(+ifi
したととを特徴とする半導体装置の製造方法。(3) After forming a thin insulating film on the surface of an element region of one conductivity type of the semiconductor substrate, a step of depositing a first dirt electrode material on the entire surface, and after depositing a film on the entire surface, K to expose a part of the first dirt t + U superfine charge.
After selectively etching away a portion of M H'A and depositing a second dart material on the entire surface, a second date 'I' is etched on the sidewall of the remaining film by anisotropic etching. =i: After leaving the material and removing the remaining film, the first dart electrode material is etched by anisotropic etching to form an asymmetrical shape made of the J-th and second dart electrode materials. K-) 'f(j 4(
1=, a step of ion-implanting an impurity of a conductivity type opposite to that of the element region at a low dose using the gate electrode as a mask, and an anisotropic process after depositing an insulating film on the entire surface. , a step of leaving an insulating film on the sidewalls of the gate electrode by checking/checking, and using the insulating film remaining on the gate electrode and its sidewalls as a mask to remove impurities of a conductivity type opposite to that of the device region at a high dose. A process of implanting ions, a process of diffusing impurities by heat treatment, and forming source and drain regions consisting of a low concentration impurity region near the channel region and a high concentration impurity region in contact with these regions.
A method for manufacturing a semiconductor device characterized by a dot.
シリコン、金屑シリザイド、金属のうち少なくとも1種
であることを特徴とする特H′F請求の範囲第3項記載
の半導体装置の製造方法。(4) Claim 3, characterized in that the first and second housings are orange (the three materials are at least one of polycrystalline silicon, gold scrap silicide, and metal). A method of manufacturing the semiconductor device described above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17536483A JPS6066861A (en) | 1983-09-22 | 1983-09-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17536483A JPS6066861A (en) | 1983-09-22 | 1983-09-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6066861A true JPS6066861A (en) | 1985-04-17 |
Family
ID=15994789
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17536483A Pending JPS6066861A (en) | 1983-09-22 | 1983-09-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6066861A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0675544A1 (en) * | 1994-03-31 | 1995-10-04 | France Telecom | Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor |
WO1997012390A1 (en) * | 1995-09-29 | 1997-04-03 | Siemens Aktiengesellschaft | Method of producing a gate electrode |
WO1998052215A1 (en) * | 1997-05-16 | 1998-11-19 | Advanced Micro Devices, Inc. | Spacer structure as transistor gate |
US5866934A (en) * | 1997-06-20 | 1999-02-02 | Advanced Micro Devices, Inc. | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure |
US5950091A (en) * | 1996-12-06 | 1999-09-07 | Advanced Micro Devices, Inc. | Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material |
US6066534A (en) * | 1996-07-31 | 2000-05-23 | Lg Semicon Co., Ltd. | Method of manufacturing a field effect transistor |
US6638801B2 (en) | 2001-03-29 | 2003-10-28 | Nec Corporation | Semiconductor device and its manufacturing method |
DE10260234A1 (en) * | 2002-12-20 | 2004-07-15 | Infineon Technologies Ag | Method for producing a sublithographic gate structure for field effect transistors, an associated field effect transistor, an associated inverter and an associated inverter structure |
JP2010267964A (en) * | 2009-05-14 | 2010-11-25 | Internatl Business Mach Corp <Ibm> | Asymmetric semiconductor device, and method of manufacturing the same |
-
1983
- 1983-09-22 JP JP17536483A patent/JPS6066861A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0675544A1 (en) * | 1994-03-31 | 1995-10-04 | France Telecom | Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor |
FR2718287A1 (en) * | 1994-03-31 | 1995-10-06 | Straboni Alain | Method for manufacturing an insulated gate field effect transistor, in particular of reduced channel length, and corresponding transistor. |
WO1997012390A1 (en) * | 1995-09-29 | 1997-04-03 | Siemens Aktiengesellschaft | Method of producing a gate electrode |
US6066534A (en) * | 1996-07-31 | 2000-05-23 | Lg Semicon Co., Ltd. | Method of manufacturing a field effect transistor |
US5950091A (en) * | 1996-12-06 | 1999-09-07 | Advanced Micro Devices, Inc. | Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material |
WO1998052215A1 (en) * | 1997-05-16 | 1998-11-19 | Advanced Micro Devices, Inc. | Spacer structure as transistor gate |
US6124174A (en) * | 1997-05-16 | 2000-09-26 | Advanced Micro Devices, Inc. | Spacer structure as transistor gate |
US5866934A (en) * | 1997-06-20 | 1999-02-02 | Advanced Micro Devices, Inc. | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure |
US6638801B2 (en) | 2001-03-29 | 2003-10-28 | Nec Corporation | Semiconductor device and its manufacturing method |
DE10260234A1 (en) * | 2002-12-20 | 2004-07-15 | Infineon Technologies Ag | Method for producing a sublithographic gate structure for field effect transistors, an associated field effect transistor, an associated inverter and an associated inverter structure |
WO2004057660A3 (en) * | 2002-12-20 | 2005-03-31 | Infineon Technologies Ag | Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure |
JP2010267964A (en) * | 2009-05-14 | 2010-11-25 | Internatl Business Mach Corp <Ibm> | Asymmetric semiconductor device, and method of manufacturing the same |
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