JPS6066861A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6066861A
JPS6066861A JP17536483A JP17536483A JPS6066861A JP S6066861 A JPS6066861 A JP S6066861A JP 17536483 A JP17536483 A JP 17536483A JP 17536483 A JP17536483 A JP 17536483A JP S6066861 A JPS6066861 A JP S6066861A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
film
gate electrode
oxide film
gt
lt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17536483A
Inventor
Toshiharu Watanabe
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

PURPOSE:To obtain a transistor of a fine structure by obtaining a fine gate electrode by a method wherein an asymmetric gate electrode is formed by anisotropic etching by the use of polycrystalline Si as the material, when the gate electrode of an MOS type transistor is prepared. CONSTITUTION:A thick field oxide film 22 is formed in the periphery of a P type Si substrate 21, and an oxide film 23 is provided from the part of gate electrode formation of the substrate 21 surrounded by that film to on the film 22. Next, a thin gate oxide film 24 is adhered to the exposed part remaining of the substrate 21, the asymmetric gate electrode 26 made of polycrystalline Si in contact with the end of the film 23 is mounted on the end of the oxide film. Thereafter, the film 23 is removed, and As<+> ions are implanted to the surface layer part of the substrate 1 with the electrode 26 as a mask, resulting in the deposit of an oxide film 27' on the side surface of the electrode 26. A deep implanted region connected to the implanted region provided previously is then formed by another time of As<+> ion implantation. The source region 28 consisting of a shallow N<-> region 28a and a deep N<+> type region 28b is generated by elongation diffusion, and the drain region 29 is formed in the same manner.
JP17536483A 1983-09-22 1983-09-22 Manufacture of semiconductor device Pending JPS6066861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17536483A JPS6066861A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17536483A JPS6066861A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6066861A true true JPS6066861A (en) 1985-04-17

Family

ID=15994789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17536483A Pending JPS6066861A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6066861A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0675544A1 (en) * 1994-03-31 1995-10-04 France Telecom Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor
WO1997012390A1 (en) * 1995-09-29 1997-04-03 Siemens Aktiengesellschaft Method of producing a gate electrode
WO1998052215A1 (en) * 1997-05-16 1998-11-19 Advanced Micro Devices, Inc. Spacer structure as transistor gate
US5866934A (en) * 1997-06-20 1999-02-02 Advanced Micro Devices, Inc. Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure
US5950091A (en) * 1996-12-06 1999-09-07 Advanced Micro Devices, Inc. Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material
US6066534A (en) * 1996-07-31 2000-05-23 Lg Semicon Co., Ltd. Method of manufacturing a field effect transistor
US6638801B2 (en) 2001-03-29 2003-10-28 Nec Corporation Semiconductor device and its manufacturing method
DE10260234A1 (en) * 2002-12-20 2004-07-15 Infineon Technologies Ag A process for preparing a sublithographic gate structure for field effect transistors, of an associated field effect transistor, an associated inverter and associated inverter structure
JP2010267964A (en) * 2009-05-14 2010-11-25 Internatl Business Mach Corp <Ibm> Asymmetric semiconductor device, and method of manufacturing the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0675544A1 (en) * 1994-03-31 1995-10-04 France Telecom Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor
FR2718287A1 (en) * 1994-03-31 1995-10-06 Straboni Alain A method of manufacturing an insulated gate field effect transistor, in particular of reduced channel length and transistor matching.
WO1997012390A1 (en) * 1995-09-29 1997-04-03 Siemens Aktiengesellschaft Method of producing a gate electrode
US6066534A (en) * 1996-07-31 2000-05-23 Lg Semicon Co., Ltd. Method of manufacturing a field effect transistor
US5950091A (en) * 1996-12-06 1999-09-07 Advanced Micro Devices, Inc. Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material
WO1998052215A1 (en) * 1997-05-16 1998-11-19 Advanced Micro Devices, Inc. Spacer structure as transistor gate
US6124174A (en) * 1997-05-16 2000-09-26 Advanced Micro Devices, Inc. Spacer structure as transistor gate
US5866934A (en) * 1997-06-20 1999-02-02 Advanced Micro Devices, Inc. Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure
US6638801B2 (en) 2001-03-29 2003-10-28 Nec Corporation Semiconductor device and its manufacturing method
DE10260234A1 (en) * 2002-12-20 2004-07-15 Infineon Technologies Ag A process for preparing a sublithographic gate structure for field effect transistors, of an associated field effect transistor, an associated inverter and associated inverter structure
WO2004057660A3 (en) * 2002-12-20 2005-03-31 Infineon Technologies Ag Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure
JP2010267964A (en) * 2009-05-14 2010-11-25 Internatl Business Mach Corp <Ibm> Asymmetric semiconductor device, and method of manufacturing the same

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