JPS6066861A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a transistor of a fine structure by obtaining a fine gate electrode by a method wherein an asymmetric gate electrode is formed by anisotropic etching by the use of polycrystalline Si as the material, when the gate electrode of an MOS type transistor is prepared. CONSTITUTION:A thick field oxide film 22 is formed in the periphery of a P type Si substrate 21, and an oxide film 23 is provided from the part of gate electrode formation of the substrate 21 surrounded by that film to on the film 22. Next, a thin gate oxide film 24 is adhered to the exposed part remaining of the substrate 21, the asymmetric gate electrode 26 made of polycrystalline Si in contact with the end of the film 23 is mounted on the end of the oxide film. Thereafter, the film 23 is removed, and As<+> ions are implanted to the surface layer part of the substrate 1 with the electrode 26 as a mask, resulting in the deposit of an oxide film 27' on the side surface of the electrode 26. A deep implanted region connected to the implanted region provided previously is then formed by another time of As<+> ion implantation. The source region 28 consisting of a shallow N<-> region 28a and a deep N<+> type region 28b is generated by elongation diffusion, and the drain region 29 is formed in the same manner.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing an 8-type semiconductor device.

[Technical background of the invention and its problems]

As the conventional MO3 type transnostar becomes smaller, electric field concentration occurs in the channel region near the drain region, and hot carriers (%) generated due to the avalanche phenomenon occur.
In the case of N-channel transnostar, hot electro/
) is da r-rqi.

The dirt is easily injected into the insulating film and dragged due to the pressure, causing serious reliability problems such as a shift in threshold voltage. Such problems pose a major obstacle to miniaturization.

Therefore, in order to solve the problem of hot array trons, so-called LDD (Lightly Doped
I) rain-8source) structures have been proposed (e.g., S.

Ogura et al., Trans. Elec.
l) e v , + El) -27 (1980) 135
9).

An example of a method for manufacturing such a 10S transnostar made of LDDg will be explained with reference to FIG. First, a dirt electrode 3 is formed on, for example, a P-type silicon substrate 1 via a dirt oxide film 2, and N-type impurities are ion-implanted at a low dose in seven days using the electrode 3 as a mask. Next, after depositing, for example, a CVD oxide film on the entire surface, residual CVD oxide films 4, 4 are formed on the side walls of the dirt electrode 3 by reactive ion etching.
Using No. 4 as a mask, N-type impurities are ion-implanted at a high dose. Next, the cine MJ material is diffused by heat treatment to form low concentration n-type impurity regions 5a and 6a near the channel region.
and a high concentration n-type impurity region 5b that is in instant contact with these regions.
, 6b are formed.

In this structure, since the drain region 6 near the channel region is composed of a lightly doped n-type impurity region 6a, the field of It's hard to do.

However, in the conventional LDD structure, especially in a transistor in which the direction of current flow is constant, such as in an inverter circuit, a low concentration n-type impurity is added to the source region 5 side, which is formed symmetrically to the drain region 6 side. There is a problem in that the region 5a only lowers the amplification factor g due to an increase in note resistance, but does not bring any benefit.

Therefore, there is a need for a technology that can arbitrarily control the dimensions of the low 12I4 degree impurity regions in the source and drain regions.

On the other hand, the current photo-etching method using light exposure is also being used to miniaturize confectionery. That is,
It is extremely difficult to form a photoresist pattern with lines of less than a few thousand square meters by light exposure, and if you try to form, for example, a fine dirt electrode by photolithography, the dimensions of the dirt electrode will increase or decrease due to overexposure or underexposure. For example, problems such as threshold value 111 and pressure fluctuations due to short channel effects arise.

Therefore, a method as shown in FIGS. 2(a) and 2(b), for example, has been reported for forming fine dart electrodes. First, for example, on a P-type silicon scrap plate 1,
After depositing the VD oxide film 12, the CVD oxide 1iQ 12k is selectively etched away so that a portion of the confectionery region is exposed. Next, a gate oxide film 13 is formed on the exposed surface of the element region.

Subsequently, after depositing, for example, a polycrystalline silicon film 14 (indicated by a broken line in the figure) on the entire surface, the polycrystalline silicon film is etched by anisotropic etching for a time of 40 minutes or more, and the CVOH film is etched. An asymmetric dart electrode 15 is formed on the side 2 (as shown in FIG. 2(a)). Next, after removing the CVO oxide film 12, n-type impurities are ion-implanted using the gate electrode 15 as a mask, and heat treatment is performed to form n-type source and drain regions 16 and 17f (as shown in FIG. 4B).

In the above method, the photolithography technique is only used when etching the CVDM film, and the dimensions of the gate electrode 15 are determined by the thickness of the polycrystalline silicon film 14 and the etching time of the anisotropic etching. be done. Therefore, overexposure or underexposure only slightly changes the position of the side wall of the CVD oxide film 12, but does not affect the dimensions of the dirt electrode 15, and r) the electrode 15 can be miniaturized.

However, the above method cannot prevent the generation of hot electrons due to electric field concentration in the channel region near the drain/region 17, and still causes problems such as threshold voltage fluctuation.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and has a fine dart electrode and appropriately controls the dimensions of the source and drain/regions to reduce electric field concentration near the drain region and amplification factor near the source region. Those who can manufacture MO8 type semiconductor devices that can effectively prevent degradation/I! ,: This is what we are trying to provide.

[Summary of the invention]

The method for manufacturing a semiconductor device according to the invention of Application No. 1 includes depositing a coating 119S on one 47-electrode type element region of a semiconductor substrate, and then removing the coating so that a part of the region is exposed. A process of selectively etching away parts of the electrode, a process of completely forming a gate insulator I+'λ on the surface of the exposed element region, and a process of depositing a gate electrode material on the entire surface, and then anisotropic etching to remove the remaining gate electrode material. After the step of forming an asymmetrical dirt electrode on the side wall of the coated film and removing the remaining / a step of implanting, a step of depositing an insulating film on the entire surface and then anisotropic etching to leave the entire insulating film on the side wall of the gate electrode, and a step of dirt polarization and using the insulating film remaining on the side wall as a mask. A process of ion-implanting impurities of a conductivity type opposite to that of the device region at a high dose and diffusing the impurities through heat treatment creates a source consisting of a low-concentration impurity region near the channel region and a high-concentration impurity region adjacent to these regions. , and a step of forming a train region.

This method (if you prefer, take a photo of the Kate consideration)
Since it can be formed without using the J-cutting method, the r-) electrode can be made finer. In addition, by taking advantage of the asymmetry of the gate electrode and setting fjJJ at the time of coating and cutting the red film remaining on the gate electrode material or its side wall, it is possible to 1. Low-intensity impurities in the drain region can be controlled arbitrarily; 2. . Therefore, effects such as being able to effectively prevent the generation of hot electrons can be obtained, and miniaturization of the 2-resistance r- can be achieved.

Further, the method for manufacturing the semiconductor device 1d of the invention of the second aspect of the present application is as follows: 1.
After forming a gate insulating film on the surface of an element region of one conductivity type of a semiconductor substrate, a first gate electrode material is deposited on the entire surface,
The odor is left so as to expose a portion of the first gate electrode material on the element region, and then the second gate electrode material is exposed:
A second dirt electrode material is deposited on the sidewalls of the film by anisotropic etching, and then a second dirt electrode material is deposited on the sidewall of the film.

After removing the coated film, the first gate electrode was etched by anisotropic etching to form a nominal r-shaped electrode.

As in the prior art, low-dose ion implantation was performed using the dirt electrode as a mask, ion implantation was carried out in an island-sized amount using the insulating film left on the gate shell and its wall as a mask, and impurity diffusion was performed by heat treatment. Conduct r = DD4H source,
This forms a drain region.

According to such a method, substantially the same effect as the first invention of the present application can be obtained.

[Embodiments of the invention]

Ability ll1 Example 1 Below, the method for manufacturing P/IQs) Lannostar according to the first invention of the present application is shown in Figs. 3(a) to (f) and Fig. 4(a).
, (b), FIGS. 5(a), (b), and FIGS. 6 and 7.

After immediately forming a field oxide film 22 on the surface of the P-type silicon substrate 21 by selective oxidation, CVD H is applied to the entire surface.
A chemical film (film) 23 is deposited, and a part of the CVD oxide film 23 is selectively etched away using reactive ion etching (RIE) so that a part of the device region is exposed. Next, a carbonate film 2 is applied to the exposed collector region surface i"ii.
4, a polycrystalline silicon film 25 is deposited on the entire surface (as shown in FIG. 3(a)). Next, by reactive ion etching (RIE), the polycrystalline silicon I pattern 25 was etched for 1 hour beyond just etching of its film thickness, and the remaining CVI) was etched into an asymmetrical dirt on the ij+1 wall of the indoctrination film 23. An electrode 26 is formed (as shown in FIG. 3(b)). Subsequently, the exposed portions of the remaining CVD oxide film 23 and dirt oxide film 24 are etched away using hydrofluoric acid or ammonium fluoride, and then the dirt electrode 26 is etched using a mask and etched with, for example, As. Ion implantation is performed at a low dose (as shown in FIG. 3(c)).

Next, CVD dichloromethane 2z is deposited on the entire surface (as shown in FIG. 4(d)). Subsequently, the CVD modified film 27 is etched by reactive ion etching for a time longer than the gloss etching of its Ij% thickness to form residual CVD oxide scum 27', 27' on the side wall of the starter electrode 26. Next, the date ηj, the pole 26 and the remaining CVD e-coated film 27'
, 27' as a mask, ions are implanted at an amount of AS k 1i-711° (as shown in FIG. 2(e)). Next, the impurities are diffused by heat treatment, and the n-
Source/drain regions 28 and 29 are formed of type impurity regions 28a and 29a and n0 type impurity regions 28b and 229b adjacent to these regions. Next, P on the whole page
After depositing the SG film 30, a contact hole, ? 1
, 31 are drilled. Subsequently, after depositing an At film on the entire surface, turning is performed to form At wirings s2 and 32,
n-channel MO8) Manufacture a lansostar ((f) in the same figure)
(Illustrated).

However, according to the above method, since the gate electrode 26 is formed by reactive ion etching without using photolithography, the dimensions of the gate electrode 26 can be made smaller than the thickness of the polycrystalline silicon film 25. can.

1. By setting the film thickness and etching time of various films deposited on the substrate 2, the glue electrode 26
The dimensions of the n-type impurity regions 28a and 29a of the source and drain regions 28 and 29 of the LDD structure can be arbitrarily controlled by utilizing the asymmetry. this thing? History will be explained in detail.

(CVI shown in Fig. 3(a)) r+≧, chemical film 23
The film thickness of dos polycrystalline silicon film (25) l is rl,
Same 1(d) De-J of the CVD oxide film 27 shown in the figure! 'l is (r2-'I), and CVD in the process of (e) in the same figure
Regarding the reactive ion etching of C12 11Q27, it is assumed that bright etching is performed, that is, etching is carried out with the minimum necessary etching time so that the flat portions are not completely removed.

Here, in the case of CVI) which is thicker than the film thickness of the oxide film 23 or the film thickness of the polycrystalline silicon film 25, that is, in the case of do)rl,
When etching the polycrystalline silicon layer 25 by reactive ion etching to form the entire dart electrode 26, No. 11 is performed.
．． Stretching or a slight overetching results in dl>0 in FIG. 4(a). At this time, even if a small k A-par etching is performed, the channel length hardly changes. Note that in FIG. 4(a), the film thickness of the CVD oxide film 27 (r2 rl)>a. When the CVD oxidized 11127 is completely etched by gloss J-etching, the shape after etching becomes as shown in FIG. 2(b).

In this case, the lateral dimension of the remaining CVD oxide film 27' on the drain/side (corresponding to the dimension of the lightly doped n-type impurity region) LD is Lo"" rz 'rls, the remaining C on the source side.
The lateral dimension Ls of the VD oxide film 27' is Ls = ,
, z−(rz rl a, )2 rl.

On the other hand, if the polycrystalline silicon film 25 is considerably over-etched, as shown in FIG. The subsequent shape is as shown in the same figure (b). In this case, rl>(l d+ H
-rz-rl), then LD "" rz -rl
+.

Based on the above results, the film thickness of the polycrystalline silicon film 25 r1-=5000X (channel length "s" 0.5 μm)
, CVI) Film thickness of oxide film 27 (rz rl)==200
0X, and the lateral dimension 14.3 of the remaining CVD oxidized yA27' on the source side is expressed as a function of dl as shown by the solid line Kfz in FIG. S'lbchi, LD = r2-r
When dl>0, Ls cannot be made so short as compared to 2000X, but when dl>0, Ls can be shortened to 100OX or less.

Note that when dl is 0, if the etching time of the polycrystalline silicon film 25 is increased, the dimensions of the dart electrode 26 can be further reduced, which is advantageous for miniaturization, but the channel length increases with the etching time. Since the etching time varies, the etching time must be strictly controlled.

Furthermore, if the CVD oxide film 27 is over-etched by 50%, Ls becomes 10 as shown by the broken line in FIG.
If 0-related overetching is performed, Ls will become as shown by the dashed line in FIG. 6, and Ls can also be set to 0. However, when long-term etching is performed, etching conditions must be set so that the CVD oxide film is etched more selectively with respect to the substrate. For example, FIG. 7 shows the shape after further over-etching by 50% from FIG. 5(b). In FIG. 7, since the lateral dimension of the remaining CVD oxide film 27' on the source side is very small, the dimension of the L-type impurity region 28a in the source region 28 formed thereunder can be made small. In a MOS transistor like the one shown in Figure 7, the increase in series resistance on the source side can be almost ignored, so in a transistor where the current flows in a constant direction, such as in an inverter circuit, a decrease in the amplification factor Qm can be prevented. can do. Of course, the n-type impurity region 29 on the drain region 29 side
The hot electron resistance due to a is that of conventional LDf),
? It has the same characteristics as the 74' construction.

In addition, in the above Example 1, the CVD 1 was
After performing the etching step 23, the entire dirt oxide film 24 is formed on the surface of the element region. A film with high selective etching properties may be deposited and a portion thereof may be selectively etched. According to this method, a dirt insulating film is present on the substrate surface during reactive ion etching of the film, and the substrate is not exposed, so that damage to the substrate can be prevented.

In addition, in the first embodiment, only the polycrystalline silicon film 25 was used as the substrate for the cathode 1TL, but the present invention is not limited to this.
For example, a polycrystalline silicon film and Mo
Using a high melting point metal silicide such as Si2 film, as shown in FIG.
oSi2! According to such a structure, the specific resistance of the dart electrode 43 can be lowered even if the dart electrode 43 is formed with a so-called polycide structure in which the turf 42 is laminated.

Example 2 Hereinafter, a method for manufacturing IViO8+-lannostar according to the second invention of the present application will be explained with reference to Figures 9 (a) to (d).

First, after forming the field oxide film 52 on the surface of the P-type silicon substrate 51, the field oxide film 52 is
A gate oxide film 53 is formed on the surface of the element region surrounded by , and a polycrystalline silicon film (first gate electrode material) 54 is further deposited over the entire m1. Next, after depositing a CVD oxide film 55 on the entire surface, a part of the CVD oxidation film 55 is selected by reactive ion etching (4thg) so that a part of the polycrystalline silicon film 54 on the element region is exposed. Remove by etching.

Subsequently, for example, MOS i 2 III (second dart electrode family) 56 is deposited on the entire surface (FIG. 9(a)).
(Illustrated).

Next, by reactive ion etching, MoS
The J□ film 56 is etched for a time longer than the just etching time for its film thickness, and a MoSi 2 film 156' is formed on the side wall of the remaining CVD (9) film 55 (
Figure (b) shown). Next, after removing the remaining CVD oxide film 55, the polycrystalline silicon film 54 is etched by reactive ion etching to form a polycrystalline silicon film notation 54'. l) 12 BH pattern 56' is laminated with a gate electrode (
form V57. Subsequently, using the dirt electrode 57 as a mask, the exposed portion of the dirt e-condenser 53 is removed by etching (as shown in FIG. 3(c)). Below, the above Example 1
Similarly, first, As+ is applied using the gate' electrode 57 as a mask.
ions are implanted at a low dose. Next, the entire CV
D (After depositing the hydride film - Reactive ion etching removes residual CVD oxidation %s8. on the side wall of the dirt electrode 57.
form 58. Subsequently, AS is ion-implanted at a high dose using the gate electrode 57 and the remaining CVD oxide films 58 and 58 as masks, and then the impurities are diffused by heat treatment to form the n-type impurity regions 59a and 60 near the channel region.
th and a depressed impurity region 59b adjacent to these regions,
60b, source and drain regions 59 and 60 are formed. Furthermore, the PSG film 61 is deposited, the contact holes 62, 62 are opened, the At wirings 6, ? , 63 are formed to manufacture an n-channel MO3+ mask (as shown in FIG. 4(d)).

Therefore, by the above method, the dart electrode 57 can be made finer in the same manner as in Embodiment 2, and moreover, the n-type impurity region 59g of the source and drain regions 59 and 60 of the LDD structure can be made fine.
, 60a can be completely controlled, and a decrease in the amplification factor on the source side can be prevented while maintaining resistance to electrons.

CVD oxide film 55 in the process of FIG. 9(a)
During reactive etching, the substrate 51 is covered with the polycrystalline saw/film 54 and the dirt oxide film 53.
1 will not take any damage.

Furthermore, compared to the case where a dirt electrode with a polycide structure was formed by the method of Example 1 (as shown in FIG. 8), the gate electrode 5
Polycrystalline silicon film/mother turn 5 with high resistivity among 7
Since the portion occupied by 4' can be reduced, it is advantageous for lowering the resistance of the dart electrode 57. Generally, the method of Example 2 is advantageous when the tenth gate electrode material has a higher resistivity than the second gate electrode material.

In Example 2, a polycrystalline silicon film was used as the first date electrode material, and MoS was used as the second date electrode material.
Although the i film is used, the present invention is not limited to this, and other materials may be used, and the first and second gate electrode materials may be made of the same material.

Further, in the first and second embodiments described above, an n-channel MO8 transistor has been described, but it goes without saying that the present invention can be similarly applied to a P-channel MO8 transistor or an idCMO8 transistor.

〔Effect of the invention〕

As detailed above, according to the method of manufacturing a semiconductor device surface of the present invention, it is possible to form a fine gate electrode and to
The source and drain regions of the structure can be formed with good controllability, which greatly contributes to the miniaturization of the device.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional Ll)D Nrc MO8+ run mask, and Figures 2 (a) and (b) are conventional MO3
t□ Cross-sectional view showing the method of manufacturing a transistor, FIG. 3 (Il
) to (f) are cross-sectional views showing the manufacturing method of MO8+-lansosc in Example 1 of the present invention, FIG. 4(a) p (
b) and FIGS. 5(a) and (b) are Example J of the present invention.
Figure 6 shows an example of calculating the dimensions of the MO3l-run mask manufactured in Example 1 of the present invention.
~iW Figures, Figures 7 and 8 are cross-sectional views showing modified examples of the present invention, and Figures 9 (a) to (d) are cross-sectional views showing a method for manufacturing a MOS (Rannosk) in Example 2 of the present invention. It is. 21.51...P silicon substrate, 22.52...
Field oxide film, 23.55...CVD J-wave conversion film (film), 24,53...Gate oxide film, 25°54
...Polycrystalline silicon film, 26,43.57...r-
) Electrode, 27... CvD oxidation model, 27', 5
B--Remaining CVD oxide film, 28.59... Source region, 29.60... Drain region, 28a, 29a. 59a, 60a = n-type impurity region, 28b. 29b, 59b, 60b---n type impurity region, 30.
61...PSG film, 31,62...contact hole, 32.63...AA wiring, 41.54'...polycrystalline/recon film/guttern, 56...Mo Si
2 films, 42H56'...MoSi21W) z'P
turn. Applicant's agent Patent attorney Suzu Ko Takeshi No. 11" No. 21 Sho @ Figure 3 (d) 2 Figure 3 Figure 4 Figure 5 Figure 61\I ch (in) No. 71 Si1 6 ro D ('% Jr.) Convex.

Claims (4)

[Claims] (1) After a film is deposited on an element region of one conductivity type of a semiconductor substrate, a part of the film is selectively etched away so that a part of the element region is exposed, and the surface of the exposed element region a step of forming a dirt insulating film on the surface of the substrate, a step of depositing a dirt electrode material on the entire surface, and then forming an asymmetric gate electrode on the side wall of the remaining film by anisotropic etching; After removal, using the dirt electrode as a mask, there is a step of conducting with the element region, and ion implantation of IE type impurities at a low dose. After depositing an insulating film on the entire surface, an anisotropic process is performed. 1) The step of leaving an insulating film on the sidewalls of the gate electrode as described in (b) and using the insulating film remaining on the dirt electrode and its sidewalls as a mask to ionize impurities in the element region and the conductive 'KN' at a high dose. The injection process and heat treatment
A semiconductor device comprising the step of diffusing impurities to form source and drain regions consisting of a low concentration impurity region near a channel region and a high concentration impurity region adjacent to these regions. Production method. (2) Is the dirt electrode material at least one of polycrystalline silicon, gold IJK silicide, and metal glaze? A method for manufacturing a semiconductor device according to claim 1. (3) After forming a thin insulating film on the surface of an element region of one conductivity type of the semiconductor substrate, a step of depositing a first dirt electrode material on the entire surface, and after depositing a film on the entire surface, K to expose a part of the first dirt t + U superfine charge.
After selectively etching away a portion of M H'A and depositing a second dart material on the entire surface, a second date 'I' is etched on the sidewall of the remaining film by anisotropic etching. =i: After leaving the material and removing the remaining film, the first dart electrode material is etched by anisotropic etching to form an asymmetrical shape made of the J-th and second dart electrode materials. K-) 'f(j 4(
1=, a step of ion-implanting an impurity of a conductivity type opposite to that of the element region at a low dose using the gate electrode as a mask, and an anisotropic process after depositing an insulating film on the entire surface. , a step of leaving an insulating film on the sidewalls of the gate electrode by checking/checking, and using the insulating film remaining on the gate electrode and its sidewalls as a mask to remove impurities of a conductivity type opposite to that of the device region at a high dose. A process of implanting ions, a process of diffusing impurities by heat treatment, and forming source and drain regions consisting of a low concentration impurity region near the channel region and a high concentration impurity region in contact with these regions.
A method for manufacturing a semiconductor device characterized by a dot. (4) Claim 3, characterized in that the first and second housings are orange (the three materials are at least one of polycrystalline silicon, gold scrap silicide, and metal). A method of manufacturing the semiconductor device described above.