JPS59119740A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of currents by a parasitic MOS transistor by obviating the formation of a path, through which currents are easy to flow to the side surface of an element section from the surface, without adding an impurity to the side surface. CONSTITUTION:Recessed sections 22 are formed to a p type Si substrate 21, an SiO2 thin-film 24 and a p type poly Si layer 25 are superposed, the film 24 is exposed onto a projecting section 23 through reactive ion etching, poly Si 26 is left on the side surface, and the surface is coated with SiO2 27. SiO2 28 is left in the recessed sections 22 through an etch-back. A first gate electrode 291 in MoSi extending on the layers 26, 28 is manufactured. The layer 26 of the side surface functions as a second gate electrode 292. n<+> Layers 31, 32 are formed to the element section 23 while using the electrodes 291, 292 as masks, the surface is coated with SiO2 33, and electrodes 351, 352 are formed. Since a work function of the electrode 292 to the Si substrate 21 is larger than that of the electrode 291, Vth of a parasitic MOS element generated on the longitudinal side surface of the electrode 291 of the n<+> layers 31, 32 can be made higher than that of the element of the surface, and a current increase by the parasitic element can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device in which the generation of parasitic transistors is suppressed.

[Technical background of the invention and its problems]

As is well known, electrical isolation technology between elements is a very important technology in integrated circuits, and various proposals have been made regarding this technology.

Conventionally, semiconductor devices using element isolation technology can be broadly classified as shown in FIG. A structure in which a dirt insulating film 4 is provided on the sapphire substrate 11 and a dirt electrode 5 is provided on the dirt insulating film 4 so as to partially extend over the 5in2 film 2, as shown in FIG. An island-shaped element portion (semiconductor layer) 12 is provided on the semiconductor layer 12, and a dirt electrode 14 is provided on the semiconductor layer 12 via a dirt insulating film 13.
on on 5apphire) structure.

However, the above-described semiconductor device shown in FIG. 1 has a drawback in that a path through which current flows more easily is generated on the longitudinal side surface of the dart electrode 5 of the element portion 3 than on the surface of the element portion 3. This will be explained with reference to FIG. 3, which is a perspective view of the semiconductor device shown in FIG. 1, and FIG. 4, which is a circuit diagram thereof. That is, a source region (S) is formed on the surface of the element section 3.
, a drain region (D) 7, and a gate electrode (G) 5. However, since the thickness of the 5io2 film 2 is thicker than the ketone insulating film 4, the threshold voltage (V, H) may decrease due to the influence of positive charges in the S]O02 film 2, or Since the shape of the side surface of the SiO2 film 2 in the longitudinal direction of the dirt electrode 4 of the element section 3 is nearly vertical, the electric field distribution under the gate insulating film 4 may be different at the end of the first transistor 81. For this reason, a second transistor (parasitic MO8 transistor) 82 is also formed on the longitudinal side surface of the dirt electrode 4 of the element section 3 in parallel with the first transistor 81. The parasitic MO3) transistor 82 is
Under the same dart breakdown voltage, current generally flows more easily than in the first transistor 81, and the dart voltage (V
G) - As shown in the drain current (more) characteristic diagram, a six-bump-like current increase phenomenon is shown in the low current region. Note that (,) in the figure indicates the characteristic curve of the first transistor 81, and (b)
1 and 2 show characteristic curves of the parasitic MO3 transistor 82, respectively.

This goes against the need for integrated circuits to keep the current at a dart voltage OV lower.

On the other hand, also in the SOS type semiconductor device shown in FIG.
00), the vTH decreases, or, as in the semiconductor device shown in FIG. For different reasons, a problem arises in that a parasitic MO8) runnostar is formed, similar to the semiconductor device shown in FIG.

For this reason, conventionally, the following measures have been taken to suppress the generation of current due to the parasitic MO8) runnostar. A case where the present invention is applied to the semiconductor device shown in FIG. 1 using a Si substrate will be described below. That is, in this method, as shown in FIG. 6, an impurity layer 9 having a higher impurity concentration than the surface of the element part 3 is formed by adding impurities to the side surface of the element part 3 closer to the SIO2 film 2. parasitic M
O8) The vTH of the transistor is made higher than that of the transistor on the surface of the element section 3. According to this semiconductor device, since the highly-concentrated impurity layer 9 is formed on the side surface of the element portion 3 closer to the SiO2 film 2, more current flows to the side surface of the element portion 3 closer to the SiO2 film 2 than on the surface of the element portion 3. It is possible to prevent the occurrence of a path through which water easily flows. However, the above-mentioned device requires a complicated technique to form the impurity layer 9, and as the device becomes smaller, the adverse effects of the impurity layer 9 on the terminal characteristics cannot be ignored, and fluctuations in the transistor vTH on the surface of the device section 3, etc. invite

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a semiconductor device that prevents the generation of a path through which current flows more easily on the side surface of the element portion than on the surface of the element portion, without adding impurities to the side surface of the element portion. This is what we provide.

[Summary of the invention]

The present invention provides an island-shaped element portion on an insulating substrate or a semiconductor substrate surface, a first dirt electrode is provided on this element portion via a first dirt insulating film, and a first dirt electrode of the element portion A second gate electrode electrically connected to the first gate electrode via a second insulating film is provided on a longitudinal side surface of the gate electrode, and the second gate electrode is connected to the element portion. By making the work function of the first gate electrode larger than the work function of the first gate electrode for the same element part, it is possible to prevent the generation of a path on the side of the element part where current flows more easily than on the surface of the element part. It is intended to do so.

Hereinafter, the progress leading to the present invention will be explained in detail.

The present inventor has discovered the material and V of the dart electrode of the semiconductor device shown in FIG. 1 or 2. -I, characteristics were investigated for n-channel and n-channel cases, and the results were as shown in FIG. Note that (a), (b), (
C) is the case where gate electrodes are made of (n+ type) polycrystalline silicon containing a high concentration of n-type impurity, Mo512, and C single-layer type polycrystalline silicon containing a high concentration of p-type impurity, respectively. vG-tag characteristic diagram of the semiconductor device of the channel, (a'
)+(b') and (c') are cases made of nj-type polycrystalline silicon, MO3+2, and p++ polycrystalline silicon, respectively.
(2) of an n-channel semiconductor device using a gate electrode. −
■ Show the characteristic diagram. From the same figure, the VTH of the n-channel semiconductor device for a certain concentration of axef.
(■o=0) is p-type polycrystalline silicon, MoSi, , n
The values are higher in the order of +-type packed crystalline silicon, and for a certain donor concentration, ■ for n-channel semiconductor devices, and H (more -0) for n-type polycrystalline silicon, MoS+2, and P'' type polycrystalline silicon. It is clear that the values increase in descending order.

The above-mentioned difference in vTH results from the difference in work function between the silicon of the element portion and the material of the dart electrode. For these reasons, the inventors have determined that the VT of the parasitic MO3) transistor is
In order to make H higher than the original vTH of the transistor, we have found that it is effective to select a material with a large difference in work function as the material for the dart electrode of the parasitic MO8) transistor.

[Embodiments of the invention]

Hereinafter, an n-channel Mo8) transistor, which is an embodiment of the present invention, will be described with reference to a manufacturing method shown in FIGS. 8(a) to 8(g).

[1] First, a portion of the surface of the p-type Si substrate 21 shown in FIG. 8(a) corresponding to the element isolation region was removed by etching to form the openings 22 . Note that 23 in the figure indicates an element portion (as shown in FIG. 8(b)).

Subsequently, thermal oxidation treatment was performed to form a thin oxide film 24 with a thickness of ~500X over the entire surface. Furthermore, p is formed on this oxide film 24.
A polycrystalline silicon layer 25 having a thickness of 2000× and doped with a type impurity such as zero was formed (as shown in FIG. 8(c)).

Next, the polycrystalline silicon layer 25 is etched anisotropically by, for example, reactive ion etching until the oxide film 22 is exposed, and the oxide film 22 is formed on the side surface of the confectionery part 23.
The polycrystalline silicon nozzle 26 was left through.

Further, a CVD-5in2 film 27 was formed on the entire surface (as shown in FIG. 8(d)).

[l;] Next, CVD −
8r 07 Oxide film 24 only in the opening part 22 of the film 27
, remain through the polycrystalline silicon pattern 26, and CV
D-5j02 film Lean 28 was formed (Fig. 8(e)
) diagram). Next, MoSi2 with a film thickness of 3000X was applied to the entire surface.
After forming a film (not shown), this Mo812 film is patterned by photolithography, so that a portion of the Mo812 film is formed into the polycrystalline silicon groove 26'I CVD-5to2 film layer.
A first gate '1 pole 29 .of Mo Si2 extending into the turn 28 . was formed. Note that the oxide film under the gate electrode 291 is the first dirt insulating film so.
It becomes 1. Further, the oxide film 7 on the side surface of the element portion 23 in the direction in which the dart electrode 291 extends. No.l becomes the second dirt insulating film 3o2, and the polycrystalline silicon pattern 5 on the same side
°! , becomes the second gate electrode 292 (Fig. 8(f)
(Illustrated). Next, using the first dirt electrode 291 as a mask, an n-type impurity such as phosphorus is ion-implanted into the element portion 23 of the Si substrate 21, heat-treated to form i-type source and drain regions 31 and 32, and then the entire surface is subjected to CVD. 51 by law
02 film 33 is formed, and then contact holes 341s342 are opened in portions of this SiO2 film 33 corresponding to the source and drain regions 31 and 32, and the source and drain regions 3'l, An n-channel Mo3 transistor having a channel region 36 was manufactured by providing a lead-out electrode 351r352 connected to the channel region 32 (as shown in FIGS. 8(g) and 9).

Note that FIG. 9 is a cross-sectional view of FIG. 8(g) taken perpendicular to the longitudinal direction of the dart electrode.

The Mo8) transistor manufactured as described above has source and drain regions 31 and 32 provided on the surface of a p-type Si substrate 21, as shown in FIGS. 8(g) and 9, and these source and drain regions 31.32. A first gate electrode 29 □ made of MoS 12 is provided on the channel region 36 between the source and drain regions 31 and 32 via the first gate insulating film 30 . 1 dart electrode 291
It has a structure in which a second gate electrode 292 made of a square polycrystalline silicon pattern is provided on the side surface in the longitudinal direction with a second dart insulating film 302 interposed therebetween.

Therefore, in the Mo8) run zoster having the above-described structure, the second gate electrode 292 made of polycrystalline silicon i+ turns has a work function for the Si substrate 2 of M
Si substrate 2 of first dirt electrode 291 made of o8i2
Since the work function for the source and drain regions 31 and 32 is larger than the work function for 1, the VTH of the transistor (parasitic MO8 runnostar) generated on the longitudinal side surface of the first dirt electrode 291 of the source and drain regions 31 and 32 is 3, about 0.5 more than vTH of the transistor on the 32 surface.
Can be increased by 5V. Therefore, the device characteristics are V of the transistor on the surface of the source and drain regions 31 and 32. -ID characteristics, and it is possible to prevent the current increase due to the conventional parasitic MO8) transistor. Note that (,) in the figure indicates the characteristic curve of the parasitic transistor occurring on the longitudinal side surface of the first dart electrode in the source and drain regions 31.32, and (b) indicates the characteristic curve of the parasitic transistor on the surface of the source and drain region 31.32. The characteristic curves of

Furthermore, according to the present invention, unlike conventional improved semiconductor devices, a highly concentrated impurity layer is not formed on the side surface of the SiO2 film in the element portion, so there is no need for any complicated impurity implantation techniques. Manufacture is simple and manufacturing yield can be increased, and even if the collectors are made finer, the device characteristics will not be adversely affected.

In the above embodiment, n-type polycrystalline silicon and MoSi2 were used as the materials for the first and second dirt electrodes, respectively, but the present invention is not limited to this. Any type of dirt electrode can be used as long as its distance from the Si substrate is larger. However, a certain amount of high temperature processing (500℃) is required in the process.
8) When polycrystalline silicon is used in the transistor section, it is necessary to form an open junction with the polycrystalline silicon.

High melting point metal such as TQ, Ta, Co, or T
Intermetallic semiconductor compounds such as 15I2+Cadi, etc. are desirable.

Further, in the above embodiment, the case of an n-channel Mos transistor has been described, but the case is not limited to this.
It can be similarly applied to an OS transistor or a CMo8) transistor. Furthermore, although the above embodiments have described the case of a transistor using an S+ substrate, the present invention is not limited to this. For example, as shown in FIG.
An island-shaped element portion 42 is provided on the parenthesized element portion 42, source and drain regions (none of which are shown) are provided on the surface of the parenthesized element portion 42, and a channel region 4 between these source and drain regions is provided.
A first dirt electrode 45.3 made of layered polycrystalline silicon is disposed on the first dirt insulating film 44. A first dirt electrode 45.f is provided in the source and drain regions. A second dirt electrode 452 made of MoS+2 is provided on the side surface in the longitudinal direction of the S.
It can be applied to semiconductor devices with an OS structure. Other So■(5
It can also be applied to semiconductor devices of the iliconon inverter) type.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device with good element characteristics that can prevent the generation of paths in the sides of the element part where current flows more easily than the surface of the element part.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional semiconductor device having 81 substrates.
Figure 2 is a cross-sectional view of a conventional SOS structure semiconductor device;
The figure is a perspective view of the semiconductor device shown in FIG. 1, FIG. 4 is a circuit diagram of FIGS. 1 and 3, and FIG. 5 is a vo-ID characteristic diagram of the semiconductor device shown in FIGS. 1 and 3. FIG. 6 is a sectional view of a semiconductor device improved from the semiconductor devices shown in FIGS. 1 and 3;
FIG. 7 is a characteristic diagram showing the relationship between the material of the dirt electrode and the VG-ID characteristics of the semiconductor device shown in FIG. 1 or FIG. 2, and FIGS. 8(a) to (g) are one embodiment of the present invention M as an example
9 is a cross-sectional view showing the manufacturing process for obtaining an O8 type transformer, and FIG. 9 is a cross-sectional view of FIG. 8th
V of the MO8 type trannostar shown in Figure (g) and Figure 9. −■. It is a characteristic diagram. FIG. 11 is a sectional view of an SO8 type semiconductor device showing another embodiment of the present invention. 2no...p-type St substrate, 22...opening portion, 23°42...island-shaped element portion, 24...thin oxide film, 25
...Polycrystalline silicon layer, 26...Polycrystalline silicon pattern (electrode material layer), 27...CvD-8IO2 film, 2B...(-VD-8102 film pattern, 29
1.292. 451.452...Gate electrode, 13y 301g
3 (72H"Ir442... dirt insulating film, 31.
...n type source region, 32...n+ type drain region, 33...Si02 film, "1+342...contact hole, 351°352...extracting electrode, 3
6.43...Channel region, 4]...Sapphire substrate. Applicant's agent Patent attorney Takehiko Suzue <s 3
rq Figure 4 Figure 5 Figure 7 Figure 8 Prisoner 8 Figure 9 P21

Claims (2)

[Claims] (1) An island-shaped element portion provided on an insulating substrate or the surface of a semiconductor substrate, a first r-to electrode provided on this element portion via a first dirt insulating film, and the same element. A semiconductor device comprising: a second dirt electrode provided on a longitudinal side surface of the first dirt electrode of the part via a second dirt insulating film and electrically connected to the first gate electrode. 2. A semiconductor device according to claim 1, wherein the work function of the second dirt electrode relative to the element portion is larger than the work function of the first dirt electrode relative to the element portion. (2) The first dirt electrode is made of polycrystalline silicon containing a high concentration of n-type impurity, and the second dirt electrode is made of an intermetallic semiconductor compound. Semiconductor equipment.