WO1997012390A1 - Method of producing a gate electrode - Google Patents

Method of producing a gate electrode Download PDF

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Publication number
WO1997012390A1
WO1997012390A1 PCT/DE1996/001845 DE9601845W WO9712390A1 WO 1997012390 A1 WO1997012390 A1 WO 1997012390A1 DE 9601845 W DE9601845 W DE 9601845W WO 9712390 A1 WO9712390 A1 WO 9712390A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate electrode
spacer
producing
polysilicon
Prior art date
Application number
PCT/DE1996/001845
Other languages
German (de)
French (fr)
Inventor
Gerhard Enders
Gerhard Rauter
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1997012390A1 publication Critical patent/WO1997012390A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating

Definitions

  • the invention relates to a method for producing a gate electrode in an integrated circuit.
  • undesirable fluctuations in the width of the photoresist generally occur when structuring the individual levels of a semiconductor circuit. Such fluctuations can be caused by fluctuations in the layer thickness of the photoresist, fluctuations in the light sensitivity of the photoresist, a non-optimal focus setting on the exposure device, or slight fluctuations in the layer thickness of layers under the photoresist. Fluctuations in the layer reflection of the layer under the photoresist and, in general, excessive reflectivity of the layer under the photoresist can also lead to inaccuracies in the structuring.
  • the invention is based on the object of creating a method of the type mentioned at the beginning with which sublithographic structures and in particular gate electrodes can be created in a particularly simple and precise manner. This object is achieved with the features of claim 1. Advantageous developments of the invention are described in the subclaims.
  • a gate oxide is produced on a substrate, an auxiliary layer is deposited and structured at the point at which the gate electrode is to be produced, a layer of a material which forms the gate electrode is deposited, a spacer is etched from this layer, the auxiliary layer is removed and the spacer is used as the gate electrode.
  • the method according to the invention enables the production of sublithographic structures.
  • the size of the spacer and thus the gate electrode now only depends on the thickness fluctuation of the deposited layer. Since the layer thickness fluctuations can be controlled within narrower limits than the fluctuations of a photographic lacquer measure, a narrower distribution of the structure widths is obtained. In particular, this method also ensures that the structure width fluctuation is also reduced as structures become smaller and smaller, regardless of topographical requirements.
  • the spacer thus produced could also be used as an etching mask for producing sublithographic structures.
  • An advantage of the invention is, however, that the spacer forms the structure to be produced directly, which simplifies and particularly precisely carries out the method.
  • the layer used for spacer formation and gate electrode production usually consists of polysilicon.
  • silicide is used to form spacers.
  • a thin layer of polysilicon with a thickness of approximately 100 nm is first applied to the gate oxide. This serves as an etching stop when removing the auxiliary layer, which usually consists of CVD oxide, in order to protect the gate oxide lying under the polysilicon layer.
  • plasma-CVD deposition or in ⁇ tzmode is particularly preferable because the method can also be applied to NIE drigen temperatures of about 400 * C.
  • the method is also suitable for structuring multilayer layers such as 4M, 16M or 64M memory chips.
  • the method according to the invention allows the use of expensive mask material, such as Phase masks to be dispensed with. Furthermore, very expensive lithography processes, e.g. X-ray lithography to be replaced.
  • a gate oxide 2 is produced on a silicon substrate 1 in a preliminary process.
  • a thin polysilicon layer 3 of approximately 100 nm is deposited. This can also be deposited using the plasma CVD process.
  • a relatively thick oxide layer 4 with a thickness of approximately 0.5 to 1 ⁇ m is deposited. This is also done in the CVD (chemical vapor deposition) process.
  • the oxide layer 4 is structured photolithographically in the next step, in particular the locations at which the gate is to be produced being structured. Spacers 5 are formed on the flanks of the oxide layer 4 structured in this way by conformal deposition of a polysilicon layer and closing anisotropic etching. This process status is shown in the figure.
  • the thin polysilicon layer 3 When etching the spacers 5, care must be taken that the thin polysilicon layer 3 is not etched through. In the next step, free areas are covered with a photo technique.
  • the thin polysilicon layer 3 serves as an etch stop and as protection for the underlying gate oxide layer 2.
  • the free areas previously covered with the photo technology are protected against unintentional etching.
  • the lacquer applied in the photographic technology is removed again.
  • the spacer 5 formed from polysilicon is now used as the gate electrode and structured accordingly. In areas where no polysilicon should remain, this is removed.
  • the polysilicon layer 3 can be removed without any problems since it is very thin in comparison to the gate electrode and the gate electrode only becomes insignificantly smaller in the case of anisotropic etching.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention concerns a method of producing a gate electrode in a microelectronic circuit. According to the invention, an auxiliary layer (14) is applied and structured. On the resultant flanks a spacer (5) is produced which is used directly to form the gate electrode.

Description

Beschreibungdescription
Verfahren zur Herstellung einer GateelektrodeMethod of manufacturing a gate electrode
Die Erfindung betrifft ein Verfahren zur Herstellung einer Gateelektrode in einer integrierten Schaltung.The invention relates to a method for producing a gate electrode in an integrated circuit.
Bei Halbleiterprodukten mit extrem hoher Integrationsdichte, beispielsweise bei integrierten Halbleiterspeichern, ist vielfach die Strukturfeinheit der Fotolithographie der limi¬ tierende Faktor.In the case of semiconductor products with an extremely high integration density, for example in the case of integrated semiconductor memories, the fineness of structure in photolithography is often the limiting factor.
Zudem treten bei der Strukturierung der einzelnen Ebenen einer Halbleiterschaltung in der Regel unerwünschte Schwan- kungen der Breite des Fotolacks auf. Solche Schwankungen können durch Schichtdickenschwankungen des Fotolacks, Schwan¬ kungen der Lichtempfindlichkeit des Fotolacks, einer nicht optimalen Fokuseinstellung am Belichtungsgerät, oder gering¬ fügigen Schichtdickenschwankungen von Schichten unter dem Fotolack hervorgerufen werden. Ebenso können Schwankungen der Schichtreflexion der unter dem Fotolack liegenden Schicht so¬ wie generell eine zu hohe Reflektivität der Schicht unter dem Fotolack zu Ungenauigkeiten bei der Strukturierung führen.In addition, undesirable fluctuations in the width of the photoresist generally occur when structuring the individual levels of a semiconductor circuit. Such fluctuations can be caused by fluctuations in the layer thickness of the photoresist, fluctuations in the light sensitivity of the photoresist, a non-optimal focus setting on the exposure device, or slight fluctuations in the layer thickness of layers under the photoresist. Fluctuations in the layer reflection of the layer under the photoresist and, in general, excessive reflectivity of the layer under the photoresist can also lead to inaccuracies in the structuring.
Daher werden die Schwankungen der oben genannten Parameter mit hohem Kontrollaufwand möglichst klein gehalten. Weiterhin ist es nötig einen Sicherheitsvorhalt in der Strukturgröße einzubauen, um bei den unvermeidlichen Schwankungen keine Ausfälle oder Beeinträchtigungen der elektrischen Funktion zu erhalten.Therefore, the fluctuations in the above parameters are kept as small as possible with a high level of control. Furthermore, it is necessary to install a safety reserve in the structure size in order to avoid failures or impairments of the electrical function in the event of the inevitable fluctuations.
Der Erfindung liegt die A u f g a b e zugrunde, ein Verfah¬ ren der eingangs genannten Art zu schaffen, mit dem auf be¬ sonders einfache und präzise Weise sublithographische Struk- turen und insbesondere Gateelektroden geschaffen werden können. Die Lösung dieser Aufgabe erfolgt mit den Merkmalen des An¬ spruchs 1. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen beschrieben.The invention is based on the object of creating a method of the type mentioned at the beginning with which sublithographic structures and in particular gate electrodes can be created in a particularly simple and precise manner. This object is achieved with the features of claim 1. Advantageous developments of the invention are described in the subclaims.
Nach dem Grundgedanken der Erfindung wird auf einem Substrat ein Gateoxid erzeugt, eine Hilfsschicht abgeschieden und an der Stelle, an der die Gateelektrode erzeugt werden soll, strukturiert, eine Schicht eines Materials, das die Gateelektrode bildet, abgeschieden, aus dieser Schicht ein Spacer geätzt, die Hilfsschicht entfernt und der Spacer als Gateelektrode verwendet.According to the basic idea of the invention, a gate oxide is produced on a substrate, an auxiliary layer is deposited and structured at the point at which the gate electrode is to be produced, a layer of a material which forms the gate electrode is deposited, a spacer is etched from this layer, the auxiliary layer is removed and the spacer is used as the gate electrode.
Das erfindungsgemäße Verfahren ermöglicht die Herstellung von sublithographischen Strukturen. Die Größe des Spacers und da- mit der Gateelektrode hängt nun nur von der Dickenschwankung der abgeschiedenen Schicht ab. Da sich die Schichtdicken¬ schwankungen in engeren Grenzen beherrschen lassen als die Schwankungen eines Fototechnik-Lackmaßes, erhält man eine schmalere Verteilung der Strukturbreiten. Insbesondere ist durch dieses Verfahren auch gewährleistet, daß mit immer kleiner werdenden Strukturen unabhängig von topographischen Voraussetzungen auch die Strukturbreitenschwankung reduziert wird.The method according to the invention enables the production of sublithographic structures. The size of the spacer and thus the gate electrode now only depends on the thickness fluctuation of the deposited layer. Since the layer thickness fluctuations can be controlled within narrower limits than the fluctuations of a photographic lacquer measure, a narrower distribution of the structure widths is obtained. In particular, this method also ensures that the structure width fluctuation is also reduced as structures become smaller and smaller, regardless of topographical requirements.
Weiterhin ist herauszustellen, daß zur Erzeugung von subli¬ thographischen Strukturen der so erzeugte Spacer auch als Ätzmaske verwendet werden könnte. Ein Vorteil der Erfindung liegt jedoch darin, daß der Spacer direkt die zu erzeugende Struktur bildet, wodurch eine Vereinfachung und eine beson- ders präzise Durchführung des Verfahrens erreicht wird.It should also be pointed out that the spacer thus produced could also be used as an etching mask for producing sublithographic structures. An advantage of the invention is, however, that the spacer forms the structure to be produced directly, which simplifies and particularly precisely carries out the method.
Die zur Spacerbildung und Gateelektrodenherstellung ver¬ wendete Schicht besteht üblicherweise aus Polysilizium. In einer Weiterbildung der Erfindung wird zur Spacerbildung Silizid eingesetzt. Auf das Gateoxid wird in einer besonders günstigen Ausfüh¬ rungsform des Verfahrens zunächst eine dünne Schicht Poly¬ silizium mit einer Dicke von ca. 100 nm aufgebracht. Diese dient als Ätzstop bei der Entfernung der Hilfsschicht, die üblicherweise aus CVD-Oxid besteht, um das unter der Poly- siliziumschicht liegenden Gateoxid zu schützen.The layer used for spacer formation and gate electrode production usually consists of polysilicon. In a further development of the invention, silicide is used to form spacers. In a particularly advantageous embodiment of the method, a thin layer of polysilicon with a thickness of approximately 100 nm is first applied to the gate oxide. This serves as an etching stop when removing the auxiliary layer, which usually consists of CVD oxide, in order to protect the gate oxide lying under the polysilicon layer.
Die Verwendung von Plasma-CVD im Abscheide- oder Ätzmode ist besonders bevorzugt, da dadurch das Verfahren auch bei nie- drigen Temperaturen von ungefähr 400*C angewandt werden kann.The use of plasma-CVD deposition or in Ätzmode is particularly preferable because the method can also be applied to NIE drigen temperatures of about 400 * C.
Auch zur Strukturierung von Mehrlagenschichten wie bei 4M, 16M oder 64M Speicherbausteinen ist das Verfahren geeignet.The method is also suitable for structuring multilayer layers such as 4M, 16M or 64M memory chips.
Zudem kann durch das erfindungsgemäße Verfahren auf den Einsatz von teurem Maskeninaterial, wie z.B. Phasenmasken, verzichtet werden. Weiterhin können sehr kostenaufwendige Lithographieverfahren, wie z.B. Röntgenlithographie, ersetzt werden.In addition, the method according to the invention allows the use of expensive mask material, such as Phase masks to be dispensed with. Furthermore, very expensive lithography processes, e.g. X-ray lithography to be replaced.
Nachfolgend wird das erfindungsgemäße Verfaliren unter Bezug¬ nahme auf die Zeichnung näher erläutert. Die einzige Figur zeigt den Schichtaufbau nach Ablauf eines Teils des Herstel¬ lungsverfahrens.The procedure according to the invention is explained in more detail below with reference to the drawing. The single figure shows the layer structure after the end of part of the production process.
Auf einem Siliziumsubstrat 1 wird in einem Vorprozeß ein Gateoxid 2 erzeugt. Im nächsten Schritt wird eine dünne Poly- siliziumschicht 3 von ca. 100 nm abgeschieden. Diese kann eventuell auch im Plasma-CVD-Verfahren abgeschieden werden. Im nächsten Schritt wird eine relativ dicke Oxidschicht 4 mit einer Dicke von ca. 0,5 bis 1 μm abgeschieden. Dies erfolgt ebenfalls im CVD-Verfahren (chemical vapor deposition) . Die Oxidschicht 4 wird im nächsten Schritt fotolithographisch strukturiert, wobei insbesondere die Stellen strukturiert werden, an denen das Gate erzeugt werden soll. An den Flanken der so strukturierten Oxidschicht 4 werden Spacer 5 durch konforme Abscheidung einer Polysiliziumschicht und an- schließende anisotrope Ätzung erzeugt. Dieser Verfahrensstand ist in der Figur dargestellt. Beim Ätzen der Spacer 5 ist darauf zu achten, daß die dünne Polysiliziumschicht 3 nicht durchgeätzt wird. Mit einer Fototechnik werden im nächsten Schritt freie Gebiete abgedeckt. Die Oxidschicht 4, die nur hilfsweise aufgebracht wurde, um an den in ihr erzeugten Flanken die Spacer 5 ätzen zu können, wird durch einen Ätz- schritt entfernt. Die dünne Polysiliziumschicht 3 dient dabei als Ätzstop und als Schutz für die darunter liegende Gate- oxidschicht 2. Ebenso werden die zuvor mit der Fototechnik abgedeckten freien Gebiete vor einer unbeabsichtigten Ätzung geschützt. Nach dem Ätzen der Oxidschicht 4 wird der bei der Fototechnik aufgebrachte Lack wieder entfernt. Der aus Poly¬ silizium gebildete Spacer 5 wird jetzt als Gateelektrode ver- wendet und entsprechend durchstrukturiert. In Bereichen, an denen kein Polysilizium bleiben soll, wird dieses entfernt. Die Polysiliziumschicht 3 kann problemlos entfernt werden, da diese im Vergleich zu der Gateelektrode sehr dünn ist und bei einer anisotropen Ätzung die Gateelektrode nur unwesentlich kleiner wird.A gate oxide 2 is produced on a silicon substrate 1 in a preliminary process. In the next step, a thin polysilicon layer 3 of approximately 100 nm is deposited. This can also be deposited using the plasma CVD process. In the next step, a relatively thick oxide layer 4 with a thickness of approximately 0.5 to 1 μm is deposited. This is also done in the CVD (chemical vapor deposition) process. The oxide layer 4 is structured photolithographically in the next step, in particular the locations at which the gate is to be produced being structured. Spacers 5 are formed on the flanks of the oxide layer 4 structured in this way by conformal deposition of a polysilicon layer and closing anisotropic etching. This process status is shown in the figure. When etching the spacers 5, care must be taken that the thin polysilicon layer 3 is not etched through. In the next step, free areas are covered with a photo technique. The oxide layer 4, which was only applied as an aid in order to be able to etch the spacers 5 on the flanks generated in it, is removed by an etching step. The thin polysilicon layer 3 serves as an etch stop and as protection for the underlying gate oxide layer 2. Likewise, the free areas previously covered with the photo technology are protected against unintentional etching. After the oxide layer 4 has been etched, the lacquer applied in the photographic technology is removed again. The spacer 5 formed from polysilicon is now used as the gate electrode and structured accordingly. In areas where no polysilicon should remain, this is removed. The polysilicon layer 3 can be removed without any problems since it is very thin in comparison to the gate electrode and the gate electrode only becomes insignificantly smaller in the case of anisotropic etching.
Im folgenden kann der Prozeß in üblicher Weise fortgesetzt werden. Hier bietet sich auch das CMP-Verfahren an. In the following the process can be continued in the usual way. The CMP process is also suitable here.

Claims

Patentansprüche claims
1. Verfahren zur Herstellung einer Gateelektrode in einer mikroelektronischen Schaltung bei dem auf einem Substrat (1) ein Gateoxid (2) erzeugt wird, eine Hilfsschicht abgeschieden und an der Stelle, an der die Gateelektrode erzeugt werden soll, strukturiert wird, eine Schicht eines Materials, das die Gateelektrode bildet, abgeschieden wird, aus dieser Schicht ein Spacer (5) geätzt wird, die Hilfsschicht entfernt wird, und der Spacer (5) als Gateelektrode verwendet wird.1. A method for producing a gate electrode in a microelectronic circuit in which a gate oxide (2) is produced on a substrate (1), an auxiliary layer is deposited and a layer of a material is structured at the point at which the gate electrode is to be produced , which forms the gate electrode, is deposited, a spacer (5) is etched from this layer, the auxiliary layer is removed, and the spacer (5) is used as the gate electrode.
2. Verfahren nach Anspruch 1, dadurch g e k e n n z e i c h n e t, daß Silizid zur Spacerbildung eingesetzt wird.2. The method according to claim 1, characterized in that silicide is used for spacer formation.
3. Verfahren nach einem der vorhergehenden Ansprüche, dadurch g e k e n n z e i c h n e t, daß auf die Gateoxidschicht (2) eine Polysiliziumschicht (3) aufgebracht wird.3. The method according to any one of the preceding claims, characterized in that a polysilicon layer (3) is applied to the gate oxide layer (2).
4. Verfahren nach einem der vorhergehenden Ansprüche, dadurch g e k e n n z e i c h n e t, daß Polysilizium im Plasma-CVD-Abscheideverfahren aufge¬ bracht wird. 4. The method according to any one of the preceding claims, characterized in that polysilicon is applied in the plasma CVD deposition process.
PCT/DE1996/001845 1995-09-29 1996-09-26 Method of producing a gate electrode WO1997012390A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19536523.2 1995-09-29
DE1995136523 DE19536523A1 (en) 1995-09-29 1995-09-29 Method of manufacturing a gate electrode

Publications (1)

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WO1997012390A1 true WO1997012390A1 (en) 1997-04-03

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10260234A1 (en) * 2002-12-20 2004-07-15 Infineon Technologies Ag Method for producing a sublithographic gate structure for field effect transistors, an associated field effect transistor, an associated inverter and an associated inverter structure
DE10348007B4 (en) * 2003-10-15 2008-04-17 Infineon Technologies Ag Method for structuring and field effect transistors
DE102005028837B4 (en) * 2005-06-25 2009-07-30 Atmel Germany Gmbh Field effect transistor and method for producing a field effect transistor

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EP0083088A2 (en) * 1981-12-30 1983-07-06 International Business Machines Corporation Method of producing field effect transistors having very short channel length
JPS6066861A (en) * 1983-09-22 1985-04-17 Toshiba Corp Manufacture of semiconductor device
US5306657A (en) * 1993-03-22 1994-04-26 United Microelectronics Corporation Process for forming an FET read only memory device
EP0675544A1 (en) * 1994-03-31 1995-10-04 France Telecom Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor

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US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
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EP0083088A2 (en) * 1981-12-30 1983-07-06 International Business Machines Corporation Method of producing field effect transistors having very short channel length
JPS6066861A (en) * 1983-09-22 1985-04-17 Toshiba Corp Manufacture of semiconductor device
US5306657A (en) * 1993-03-22 1994-04-26 United Microelectronics Corporation Process for forming an FET read only memory device
EP0675544A1 (en) * 1994-03-31 1995-10-04 France Telecom Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor

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DE19536523A1 (en) 1997-04-03

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CR1 Correction of entry in section i

Free format text: PAT.BUL.15/97 UNDER INID(51)"IPC",REPLACE THE EXISTING SYMBOL BY"H01L 21/28,29/423"

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase