JPS6060745A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS6060745A
JPS6060745A JP58169658A JP16965883A JPS6060745A JP S6060745 A JPS6060745 A JP S6060745A JP 58169658 A JP58169658 A JP 58169658A JP 16965883 A JP16965883 A JP 16965883A JP S6060745 A JPS6060745 A JP S6060745A
Authority
JP
Japan
Prior art keywords
lead frame
lead
wire
section
lump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58169658A
Other languages
Japanese (ja)
Inventor
Koji Nose
幸之 野世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58169658A priority Critical patent/JPS6060745A/en
Publication of JPS6060745A publication Critical patent/JPS6060745A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To receive semiconductor chips in size extending over a wide range by a lead frame of one kind by fitting a lump consisting of a conductor or an insulator at the nose section or a section in the vicinity of the nose section of an inner lead on the chip loading side of the lead frame. CONSTITUTION:Pillowy lumps 7 composed of a metal, ceramics or the like are fitted to sections under wires 5 electically connecting inner lead sections 4 in a lead frame 1 and a semiconductor chip 3. The upper surface section of the lump 7 takes a flat or recessed shape, and the wire 5 is fixed to the upper surface section. Semiconductor chips in size extending over a wide range can be received in semiconductor packages of the same external shape by the lead frames of one kind having large die attachments because the long-span wires can be applied, and a process can be standardized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体パッケージに適用するリードフレーム
のインナーリード部の先端部もしくはその近傍のチップ
搭載方向に、導体や絶縁体からなる塊を設けた構造のリ
ードフレームに関する〇従来例の構成とその問題点 従来のリードフレームは、第１図に外観斜視図で示した
ように、リードフレーム１のダイアタッチメント部分２
に半導体チップ３を金−シリコン共晶、導電性ペースト
、錫−鉛ハンダ等の方法で固着していた。さらにこの半
導体チップ３は、チップ上のポンディングパッドと、リ
ードフレームのインナーリード部４を、金もしくはアル
ミニウム細線（ワイヤー）６で接続することで半導体パ
ッケージのアウターリード６と半導体チップ３間の電気
的接続を行っていた。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a structure in which a lump made of a conductor or an insulator is provided in the chip mounting direction at or near the tip of the inner lead portion of a lead frame applied to a semiconductor package. 〇 Conventional structure and problems related to the lead frame The conventional lead frame has a die attachment portion 2 of the lead frame 1, as shown in the external perspective view in Fig. 1.
The semiconductor chip 3 is fixed to the substrate using a method such as gold-silicon eutectic, conductive paste, or tin-lead solder. Furthermore, this semiconductor chip 3 can be electrically connected between the outer leads 6 of the semiconductor package and the semiconductor chip 3 by connecting the bonding pads on the chip and the inner leads 4 of the lead frame with gold or aluminum thin wires (wires) 6. connection was made.

ところがチップ上ポンディングパッドとインナーリード
を接続する金もしくはアルミニウムのリード線６は細線
であるために、径間の長いワイヤーを張った場合、第１
にワイヤーボンディング中にワイヤーのループ形状が乱
れて、チップエッヂやグイアタッチメントのエッヂにワ
イヤーの接触が生じたり、隣りのワイヤーとの間で接触
が生じ、組立規則に、過大な制約を与えるという問題が
あった。また第２に、ワイヤーボンディング後に異常が
生じてなくても、樹脂対土工程での樹脂注入の際に、樹
脂注入圧によってワイヤーが変形し、上述の接触不良が
生じるという問題があった。However, since the gold or aluminum lead wire 6 that connects the bonding pad on the chip and the inner lead is a thin wire, when a long wire is stretched, the first
During wire bonding, the shape of the wire loop becomes disordered, causing the wire to come into contact with the chip edge or the edge of the wire attachment, or with adjacent wires, which places excessive constraints on the assembly rules. was there. Second, even if no abnormality occurs after wire bonding, there is a problem in that the wire is deformed by the resin injection pressure during resin injection in the resin-to-soil process, resulting in the above-mentioned poor contact.

発明の目的 本発明は従来例にみられた上述の問題点を一挙に解消す
るとともに、一種類のリードフレームで広範囲のサイズ
の半導体チップを処理することの出来るリードフレーム
を提供するものである。OBJECTS OF THE INVENTION The present invention solves all the above-mentioned problems seen in the conventional example, and provides a lead frame that can process semiconductor chips of a wide range of sizes with one type of lead frame.

発明の構成 本発明は要約すると、リードフレームのチップ搭載側の
インナーリード先端部もしくはその近傍に、導体又は絶
縁体からなる塊を設けたもので、この構造により径間の
ワイヤーの一部をこの塊上面で支えることができ、上述
の目的が確実に達成される。Components of the Invention To summarize, the present invention provides a lump made of a conductor or an insulator at or near the tip of the inner lead on the chip mounting side of the lead frame, and with this structure, a part of the wire in the span can be connected to this lump. It can be supported on the top surface of the mass, ensuring that the above objectives are achieved.

実施例の説明 以下、本発明を図面の実施例を参照にして詳しくのべる
。DESCRIPTION OF EMBODIMENTS The present invention will now be described in detail with reference to embodiments of the drawings.

第２図は本発明のリードフレームのインナーリード付近
を示す要部拡大斜視図である。FIG. 2 is an enlarged perspective view of essential parts showing the vicinity of the inner leads of the lead frame of the present invention.

本発明のリードフレーム１のアウターリード部６は従来
のｉｔであるが、半導体チップ３とインナーリード部４
を電気的に接続するワイヤー５の下の部分に、金属やセ
ラミック等からなる枕状の塊７を設ける。この塊７の上
面部は平坦もしくは凹形形状をなしており、この部分に
ワイヤー５を固定させる。この塊７のインナーリード４
の先端部への取り付けは、スポット溶接々いしは、耐熱
性接着材８を用いることで達成出来る。これらの加工は
、グイアタッチメント２に半導体チップ３が搭載される
前に行う。この塊７の高さは半導体チップ３の厚みによ
り異るが、一般に４００〜５００μｍとする。The outer lead part 6 of the lead frame 1 of the present invention is a conventional IT, but the semiconductor chip 3 and the inner lead part 4 are
A pillow-shaped mass 7 made of metal, ceramic, etc. is provided below the wire 5 that electrically connects the wires. The upper surface of this mass 7 has a flat or concave shape, and the wire 5 is fixed to this portion. Inner lead 4 of this lump 7
Attachment to the tip can be achieved by spot welding or by using a heat-resistant adhesive 8. These processes are performed before the semiconductor chip 3 is mounted on the guide attachment 2. The height of this lump 7 varies depending on the thickness of the semiconductor chip 3, but is generally 400 to 500 μm.

このようにして半導体チップ３とインナーリード４の先
端を電気的に接続する目的で張られたワイヤー５による
グイアタッチメント２のエッヂや半導体チップ３のエッ
ヂや隣接したワイヤー５間で発生する接触不良が解消さ
れる。In this way, poor contact that occurs between the edge of the wire attachment 2, the edge of the semiconductor chip 3, or between adjacent wires 5 due to the wire 5 stretched for the purpose of electrically connecting the semiconductor chip 3 and the tip of the inner lead 4 can be avoided. It will be resolved.

グイアタッチメント２やインナーリード４の一部は、半
導体チップ３のグイアタッチメント２への取り付は方法
によって表面のメッキ材料に、金や銀を用い、リードフ
レーム１の材料も鉄系や銅系合金等を対象にして上記発
明が実施できる。Depending on the method used to attach the semiconductor chip 3 to the lead attachment 2 and some of the inner leads 4, gold or silver is used as the surface plating material, and the material of the lead frame 1 is also made of iron-based or copper-based alloys. The above invention can be carried out with respect to the following.

発明の効果Effect of the invention

Claims (2)

【特許請求の範囲】[Claims] （１）　リードフレームのチップ搭載側のインナーリー
ドの先端部もしくはその近傍に、導体又は絶縁体からな
る塊を接着固定したリードフレーム。(1) A lead frame in which a lump of a conductor or insulator is adhesively fixed to or near the tip of the inner lead on the chip mounting side of the lead frame. （２）塊が平坦もしくは凹形形状の上面部を有している
特許請求の範囲第１項に記載のリードフレーム０(2) The lead frame 0 according to claim 1, wherein the block has a flat or concave upper surface portion.
JP58169658A 1983-09-14 1983-09-14 Lead frame Pending JPS6060745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58169658A JPS6060745A (en) 1983-09-14 1983-09-14 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58169658A JPS6060745A (en) 1983-09-14 1983-09-14 Lead frame

Publications (1)

Publication Number Publication Date
JPS6060745A true JPS6060745A (en) 1985-04-08

Family

ID=15890534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58169658A Pending JPS6060745A (en) 1983-09-14 1983-09-14 Lead frame

Country Status (1)

Country Link
JP (1) JPS6060745A (en)

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