JPS6060744A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS6060744A
JPS6060744A JP58169654A JP16965483A JPS6060744A JP S6060744 A JPS6060744 A JP S6060744A JP 58169654 A JP58169654 A JP 58169654A JP 16965483 A JP16965483 A JP 16965483A JP S6060744 A JPS6060744 A JP S6060744A
Authority
JP
Japan
Prior art keywords
lead
lead frame
wire
nose
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58169654A
Other languages
Japanese (ja)
Inventor
Koji Nose
幸之 野世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58169654A priority Critical patent/JPS6060744A/en
Publication of JPS6060744A publication Critical patent/JPS6060744A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To load chips in size extending over a wide range by a lead frame of one kind by bending the nose section of an inner lead in the lead frame toward the loading side and supporting a metallic fine wire for a connection by the nose of the inner lead. CONSTITUTION:The noses of inner lead sections 3 in a lead frame 1 are bent toward the direction of loading of a semiconductor chip, and recesses 4 are formed at the nose sections. The height of bending of the nose section differs according to the thickness of the semiconductor chip, but it generally extends over approximately 400-500mum. A wire 6 is laid on the recess 4 at the nose section of the lead and bonded on a wire bonding. Accordingly, semiconductor chips in size extending over a wide range can be received in semiconductor packages of the same external shapes by the lead frames of one kind having large die attachments because a connection by long-span wires can be applied.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体パッケージに適用するリードフレーム、
とくに、そのインナーリード部の先端部もしくけその近
傍を、チップ搭載方向に折曲げた構造のリードフレーム
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to lead frames applied to semiconductor packages;
In particular, the present invention relates to a lead frame having a structure in which the tip end of the inner lead portion or the vicinity thereof is bent in the chip mounting direction.

従来例の構成とその問題点 従来のリードフレームは、中央部の径大なダイアタッチ
メント部分に半導体チップを金−シリコン共晶、導電性
ペースト、錫−鉛ハンダ等の方法で固着し、さらに、こ
の半導体チップは、チップ上のポンディングパッドと、
リードフレームのインナーリード部とを、金もしくはア
ルミニウム細線で接続することで半導体パッケージのア
ウターリードと半導体チップ間の電気的接続釜行なうこ
とができる構造である。Conventional structure and its problems In conventional lead frames, the semiconductor chip is fixed to the large-diameter die attachment part in the center using gold-silicon eutectic, conductive paste, tin-lead solder, etc. This semiconductor chip has a bonding pad on the chip,
This structure allows electrical connection between the outer leads of the semiconductor package and the semiconductor chip by connecting the inner leads of the lead frame with thin gold or aluminum wires.

ところが、チップ上ポンディングパッドとインナーリー
ドとを接続する金もしくはアルミニウムのリード線は、
細線であるために、径間の長いワイヤーを張った場合、
第１にワイヤーボンディング中にワイヤーのループ形状
が乱れて、チップエッヂやダイアタッチメントのエッヂ
にワイヤーの接触が生じたり、隣りのワイヤーとの間で
接触が生じ、組立規則に、過大な制約を与えるという問
題があった。寸だ第２に、ワイヤーボンディングの際に
異常が生じてなくても、樹脂封止工程での樹脂注入の際
に、樹脂注入圧によってワイヤーが変形し、上述の接触
不良が生じるという問題があった０ 発明の目的 本発明は従来例にみられた上述の問題点を一挙に解消す
るとともに、一種類のリードフレームで広範囲のサイズ
の半導体チップを搭載して、結線処理することの可能な
構造のリードフレームを提供するものである。However, the gold or aluminum lead wires that connect the bonding pads on the chip and the inner leads are
Because it is a thin wire, if you stretch a wire with a long span,
First, the shape of the wire loop becomes disordered during wire bonding, causing the wire to come into contact with the edge of the chip or die attachment, or with adjacent wires, which places excessive constraints on the assembly rules. There was a problem. Second, even if no abnormalities occur during wire bonding, there is the problem that the wires are deformed by the resin injection pressure during resin injection during the resin sealing process, causing the contact failure described above. 0 Purpose of the Invention The present invention solves the above-mentioned problems seen in the conventional example at once, and also provides a structure that allows semiconductor chips of a wide range of sizes to be mounted and wired using one type of lead frame. It provides lead frames for

発明の構成 本発明は要約すると、インナーリードの先端部をチップ
を搭載側に向けて折り曲げ、その先端で接続用金属細線
を支承可能になした構造のリードフレームであり、これ
により上述の目的が確実に達成される。Structure of the Invention To summarize, the present invention is a lead frame having a structure in which the tip of the inner lead is bent toward the chip mounting side so that the tip can support a thin metal wire for connection. definitely achieved.

実施例の説明 以下、本発明を１図面の実施例を参照して、詳しくのべ
る。DESCRIPTION OF THE EMBODIMENTS The invention will now be described in detail with reference to an embodiment in one drawing.

第１図は従来のリードフレームの全体外観斜視部を示し
、第２図は本発明のリードフレームのインナーリード付
近を示す。本発明のリードフレーム１のアウターリード
部２は従来のままで、インナーリード部３の先端が半導
体チップ搭載方向に向って折れ曲っておシ、その先端部
に窪み４を有している。この先端部の折り曲げ高さは、
半導体チップ６の厚みによって異るが一般に、４００〜
５００μｍ位とする。FIG. 1 shows a perspective view of the entire appearance of a conventional lead frame, and FIG. 2 shows the vicinity of the inner leads of the lead frame of the present invention. The outer lead portion 2 of the lead frame 1 of the present invention is the same as the conventional one, but the tip of the inner lead portion 3 is bent toward the semiconductor chip mounting direction, and has a recess 4 at the tip. The bending height of this tip is
It varies depending on the thickness of the semiconductor chip 6, but generally 400~
It should be about 500 μm.

ワイヤーボンドの際、このリード先端部窪み４にワイヤ
ー６を掛けてボンディングを行う。なお、この窪みがな
く、平坦構造であっても、接触摩擦でワイヤー６の移動
はかなり防止できる。At the time of wire bonding, the wire 6 is hung over the lead tip recess 4 to perform the bonding. Incidentally, even if there is no recess and the structure is flat, movement of the wire 6 can be considerably prevented due to contact friction.

こうすることで、ワイヤー６がダイアタッチメンドアの
エッヂや半導体チップ５のエッヂと接触する事故、いわ
ゆる、接触不良が解消される。This eliminates the accident that the wire 6 comes into contact with the edge of the die attach door or the edge of the semiconductor chip 5, that is, a so-called contact failure.

また、ダイアタッチメンドアやインナーリード部３の一
部は、半導体チップ５の取り付は方法によって、表面の
メッキ材料に、金や銀を用い、リードフレーム１の材料
も、鉄系や銅系合金等を対象にして上記発明が実施でき
る。In addition, depending on the mounting method of the semiconductor chip 5, the die attach door and a part of the inner lead part 3 use gold or silver as the plating material on the surface, and the material of the lead frame 1 is also made of iron-based or copper-based alloy. The above invention can be carried out with respect to the following.

発明の効果 本発明によれば、長径間ワイヤーによる接続が適用可能
となるため、大きなダイアタッチメントのリードフレー
ム１種類で同一外形の半導体パッケージ中に広範囲のサ
イズの半導体チップが収納でき、工程の標準化が図れる
。さらに近年の大電力半導体の開発に伴い、放熱性の良
い半導体ノ々ツケージ開発の要望が強く、このノクツケ
ージ開発を達成するために、通常封止樹脂中に混ぜられ
ている充填剤の量が増やされる。これによって樹脂注入
時に生じる長径間ワイヤーの変形を、本発明を適用する
ことで解消できる。Effects of the Invention According to the present invention, since connections using long-span wires can be applied, semiconductor chips of a wide range of sizes can be housed in a semiconductor package with the same external shape using one type of large die attachment lead frame, and the process can be standardized. can be achieved. Furthermore, with the development of high-power semiconductors in recent years, there has been a strong demand for the development of semiconductor cages with good heat dissipation.In order to achieve the development of semiconductor cages with good heat dissipation, the amount of filler that is usually mixed in the encapsulating resin has been increased. It will be done. As a result, deformation of the long span wire that occurs during resin injection can be eliminated by applying the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例斜視図、第２図は本発明実施例の要部斜
視図である。 １・・・・・・リードフレーム、２・・・・・・アウタ
ーリード、３・・・・・・インナーリード、４・・・・
・・窪み、５・・・・・・半導体チップ、６・・・・・
・ワイヤー、７・・・・・・ダイアタッチメント。FIG. 1 is a perspective view of a conventional example, and FIG. 2 is a perspective view of essential parts of an embodiment of the present invention. 1...Lead frame, 2...Outer lead, 3...Inner lead, 4...
・・・Recess, 5... Semiconductor chip, 6...
・Wire, 7...Die attachment.

Claims (2)

【特許請求の範囲】[Claims] （１）　インナーリードの先端部をチップ搭載側に向け
て折り曲げ、その先端で接続用金属細線を支承可能にな
した構造のリードフレーム。(1) A lead frame with a structure in which the tip of the inner lead is bent toward the chip mounting side, and the tip can support a thin metal wire for connection. （２）　インナーリードの折り曲げ先端に窪みが設けら
れた特許請求の範囲第１項に記載のリードフレーム。(2) The lead frame according to claim 1, wherein a recess is provided at the bent end of the inner lead.
JP58169654A 1983-09-14 1983-09-14 Lead frame Pending JPS6060744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58169654A JPS6060744A (en) 1983-09-14 1983-09-14 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58169654A JPS6060744A (en) 1983-09-14 1983-09-14 Lead frame

Publications (1)

Publication Number Publication Date
JPS6060744A true JPS6060744A (en) 1985-04-08

Family

ID=15890469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58169654A Pending JPS6060744A (en) 1983-09-14 1983-09-14 Lead frame

Country Status (1)

Country Link
JP (1) JPS6060744A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015026781A (en) * 2013-07-29 2015-02-05 トヨタ自動車株式会社 Lead frame, power conversion device, semiconductor device, and method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015026781A (en) * 2013-07-29 2015-02-05 トヨタ自動車株式会社 Lead frame, power conversion device, semiconductor device, and method of manufacturing semiconductor device

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