JPH05166964A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05166964A JPH05166964A JP3331688A JP33168891A JPH05166964A JP H05166964 A JPH05166964 A JP H05166964A JP 3331688 A JP3331688 A JP 3331688A JP 33168891 A JP33168891 A JP 33168891A JP H05166964 A JPH05166964 A JP H05166964A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- lead
- leads
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は小型面付タイプ樹脂封止
半導体装置の高密度実装に対応できるパッケージ構造に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure that can be used for high-density mounting of a small surface-mount type resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来の面付タイプ半導体装置では、半導
体チップとチップの電極に接続した複数のリードをパッ
ケージング部材である樹脂モールド体により、その外部
端子（アウターリード）が露出する形で封止し、この外
部端子をガルウイング（鳥の翼）状に左右を開いた形に
成形加工し、端子先端をプリント配線に平行な状態で接
触させてハンダ等の導電性接着剤により接着固定するこ
とのできるパッケージング構造が、たとえば日立面実装
形パッケージ実装マニュアル（１９８９年７月発行）に
より知られている。2. Description of the Related Art In a conventional surface-mounted type semiconductor device, a semiconductor chip and a plurality of leads connected to the electrodes of the chip are sealed by a resin molded body, which is a packaging member, so that its external terminals (outer leads) are exposed. Stop, form the gull wing (bird's wing) into a shape with the left and right sides open, and then contact the tip of the terminal in parallel with the printed wiring and bond and fix it with a conductive adhesive such as solder. A packaging structure that can be used is known, for example, from the Hitachi surface mounting type package mounting manual (issued in July 1989).
【０００３】面付タイプ半導体装置のパッケージング構
造では、リード形状が上記のガルウイング状以外は、ア
ウターリードが垂直に延びてその下端でプリント配線に
接続するバット・リード形式や、アウターリードを内側
に曲げるＪベンド・リード形式が知られている。In the packaging structure of a surface-mounted type semiconductor device, except the lead shape other than the gull wing shape described above, the outer lead extends vertically and is connected to the printed wiring at the lower end, or the outer lead is formed inside. The bend J-bend lead format is known.
【０００４】[0004]
【発明が解決しようとする課題】面実装形パッケージを
高密度実装する上で、パッケージの小型化による実装面
積縮小が望まれている。従来のガルウイング・リードを
用いるパッケージでは、配線基板に実装する際にアウタ
ーリードかパッケージ側面より外側方向にはみ出した状
態になり、実装面積縮小が期待できない。また、アウタ
ーリードの配線への位置決めにも問題がある。For high-density mounting of surface mount type packages, it is desired to reduce the mounting area by miniaturizing the packages. In a conventional package using gull wing leads, when mounted on a wiring board, the outer leads protrude outward from the side surface of the package, and a reduction in mounting area cannot be expected. There is also a problem in positioning the outer lead on the wiring.
【０００５】バット・リードを用いるパッケージでは、
配線基板との接触が点になり接続不良を生じる不安があ
る。また、Ｊベンド・リードを用いるパッケージでは、
リードの位置決めが難しく、配線上でリードの曲面での
接触であり、接続不良の不安がある。In the package using the butt lead,
There is a concern that contact with the wiring board may become a point and connection failure may occur. Also, for packages that use J-bend leads,
It is difficult to position the leads, and there is a concern about poor connection because the leads are in contact with each other on the curved surface.
【０００６】解決しようとする問題点は、従来、半導体
装置において、外部接続用端子リードのパッケージ部材
からの突出部分をなくして実装面積を小さくし、リード
と配線基板との接続の際において、位置決めの不安や接
続不良をなくしたパッケージ構造を提供することであ
る。A problem to be solved is to reduce the mounting area by eliminating the protruding portion of the external connection terminal lead from the package member in the conventional semiconductor device, and to position the lead and the wiring board at the time of positioning. It is to provide a package structure that eliminates the anxiety and poor connection.
【０００７】[0007]
【課題を解決するための手段】本発明は、半導体チップ
とチップに接続された接続用端子（リード）がパッケー
ジ部材（樹脂成形体）により包囲され封止された半導体
装置であって、リードの外端部はパッケージ部材の側面
よりも突出していることを特徴とするものである。この
ようなパッケージ構造とすることにより、リードがパッ
ケージ外郭内に限られ、実装面積を縮小し、配線基板へ
の実装時の位置決めの不安定や接続不良が解消できる。
また、外部に突出するリード部分が存在しないから、リ
ードの変形等のトラブルをなくすことができる。SUMMARY OF THE INVENTION The present invention is a semiconductor device in which a semiconductor chip and connection terminals (leads) connected to the chip are surrounded and sealed by a package member (resin molding). The outer end portion is characterized in that it projects beyond the side surface of the package member. With such a package structure, the leads are confined to the inside of the package, the mounting area can be reduced, and unstable positioning and poor connection at the time of mounting on the wiring board can be eliminated.
Further, since there is no lead portion protruding to the outside, trouble such as lead deformation can be eliminated.
【０００８】本発明は、上記したパッケージ構造におい
て、パッケージのリード露出部を形成する凹部を１つの
リードごとに、または複数のリードを共有して設けるも
のである。これにより配線基板への実装時の位置決めの
不安や接続不良を解消できる。According to the present invention, in the above-mentioned package structure, a recess forming a lead exposed portion of the package is provided for each lead or for sharing a plurality of leads. As a result, it is possible to eliminate anxiety about positioning during mounting on a wiring board and connection failure.
【０００９】本発明は、上記したパッケージ構造の半導
体装置の実装にあたり、パッケージ凹部に露出するリー
ドの下面部分にハンダ等の導電性の接着剤を付着し、加
熱することにより、表面張力で球状化した状態の導電性
接着剤を介してパッケージと配線基板との接続を行なう
ものであり、これにより接続作業を容易にし、自動化を
可能ならしめる。In mounting the semiconductor device having the above-mentioned package structure, the present invention attaches a conductive adhesive such as solder to the lower surface of the lead exposed in the recess of the package and heats it to make it spherical by surface tension. The package and the wiring board are connected to each other through the conductive adhesive in the above state, which facilitates the connection work and enables automation.
【００１０】[0010]
【実施例】図１は、本発明の一実施例である半導体装置
ＦＰＰＩＣ（ＦＬＡＴーＰＬＡＳＴＩＣーＰＡＣＫＡＧ
ＥーＩＣ）の原理的構造を示す縦断面図である。１は金
属板よりなるタブ（またはダイ）で、周辺を取り囲む複
数のリード３とともにリードフレームを構成する。２は
半導体チップ（ＩＣ本体）で、タブ上に接続される。チ
ップの各電極は金線（ワイヤ）５を介して複数のリード
３に電気的に接続される。６は樹脂成形体でチップやリ
ードを包囲し封止してパッケージ構造をつくる。４は凹
部でパッケージ下面にリードの一部を露出するように設
けられる。上記リード（リードフレーム）の外端部（ア
ウターリード）はパッケージの側面より突出することが
なく、その下面のみが凹部４によって露出する。FIG. 1 shows a semiconductor device FPPIC (FLAT-PLASTIC-PACKAG) which is an embodiment of the present invention.
It is a longitudinal cross-sectional view showing the principle structure of (E-IC). Reference numeral 1 denotes a tab (or die) made of a metal plate, which constitutes a lead frame together with a plurality of leads 3 surrounding the periphery. A semiconductor chip (IC body) 2 is connected to the tab. Each electrode of the chip is electrically connected to a plurality of leads 3 via a gold wire (wire) 5. 6 is a resin molded body that surrounds and seals the chips and leads to form a package structure. Denoted at 4 is a recess so as to expose a part of the lead on the lower surface of the package. The outer ends (outer leads) of the leads (lead frame) do not protrude from the side surfaces of the package, and only the lower surface thereof is exposed by the recesses 4.
【００１１】図２は図１の半導体装置の底面を上にした
斜視図を示すものである。樹脂からなるパッケージの底
面に複数の凹部４がリードに対応して設けられ、リード
３の底面がそれぞれに露出する。このような半導体装置
をプリント配線基板に実装する場合、パッケージ側の接
続用端子（リード）面が凹部により互いに離隔されてい
るから配線との接続部分で充分の量のハンダ（導電性接
着剤）を使用することができ、接続不良となることはな
い。FIG. 2 is a perspective view of the semiconductor device of FIG. 1 with the bottom surface up. A plurality of recesses 4 are provided on the bottom surface of the package made of resin so as to correspond to the leads, and the bottom surfaces of the leads 3 are exposed. When such a semiconductor device is mounted on a printed wiring board, since the connecting terminal (lead) surfaces on the package side are separated from each other by the recesses, a sufficient amount of solder (conductive adhesive) is used at the connecting portion with the wiring. Can be used without causing a poor connection.
【００１２】図３は本発明の他の実施例の半導体装置の
底面を上にした斜視図を示すものである。この実施例で
は複数のリード３に対して一つの連続する凹部４を対応
させたものである。この場合、凹部が連続しているか
ら、横方向からリードの位置を確認でき、実装作業が容
易となる。FIG. 3 is a perspective view showing a semiconductor device according to another embodiment of the present invention with its bottom surface facing upward. In this embodiment, one continuous concave portion 4 is made to correspond to a plurality of leads 3. In this case, since the recesses are continuous, the position of the lead can be confirmed from the lateral direction, and the mounting work becomes easy.
【００１３】図４は本発明の半導体装置をプリント配線
基板１０上に実装する形態を示す正面断面図である。パ
ッケージ下面の凹部により露出するリード３の下面にハ
ンダ等の導電性接着剤８を付着させておき、ハンダの融
点以上に加熱することによりハンダが表面張力で球状と
なり、パッケージ下面と配線基板表面とが同一面となっ
てリード３と配線９とが、ハンダ８を介して良好な接続
を得る。FIG. 4 is a front sectional view showing a form in which the semiconductor device of the present invention is mounted on the printed wiring board 10. A conductive adhesive 8 such as solder is attached to the lower surface of the lead 3 exposed by the recess on the lower surface of the package and heated to a temperature above the melting point of the solder, so that the solder becomes spherical due to surface tension. Are on the same surface, and the lead 3 and the wiring 9 can obtain a good connection via the solder 8.
【００１４】図５は本発明を４方向にリードを有する正
方形パッケージに適用した場合の一実施例を斜視図で示
すものである。この例では複数のリード３に対して各辺
ごとに共通の連続した凹部４が設けられている。FIG. 5 is a perspective view showing an embodiment in which the present invention is applied to a square package having leads in four directions. In this example, a common continuous recess 4 is provided on each side of the plurality of leads 3.
【００１５】図６は本発明を４方向にリードを有する正
方形パッケージに適用した場合の一実施例を斜視図で示
すものである。この例では複数のリード３の１個１個に
対応して凹部４が設けられている。FIG. 6 is a perspective view showing an embodiment in which the present invention is applied to a square package having leads in four directions. In this example, the recess 4 is provided corresponding to each of the plurality of leads 3.
【００１６】図７は本発明の半導体装置をパッケージン
グする以前の形態を示す正面図である。すなわち、リー
ドフレームの形態でタブ１を取り囲む複数のリード３の
インナーリード側をプレスにより屈曲させておき（チッ
プの高さまで）、半導体チップ２をタブ上に接続（チッ
プボンディング）し、次いでチップの電極とリードとの
間をワイヤ５により接続（ワイヤボンディング）する。FIG. 7 is a front view showing a form before packaging the semiconductor device of the present invention. That is, the inner lead side of the plurality of leads 3 surrounding the tab 1 in the form of a lead frame is bent by pressing (up to the chip height), the semiconductor chip 2 is connected onto the tab (chip bonding), and then the chip The electrodes 5 and the leads are connected by wire 5 (wire bonding).
【００１７】図８は本発明の半導体装置を樹脂成形装置
によりパッケージングする時の正面断面図である。すな
わち、図７で示すリードフレーム構成品を樹脂成形用金
型１１、１２内に挿入した状態を示す。この金型のラン
ナー１３を通じて、チップとリードフレームの隙間に樹
脂１４を注入し、パッケージ成形体（図１の６）をつく
る。この成形金型において、アウターリードの下面に金
型（下型）１２の一部が接触することにより、この部分
でパッケージの凹部４が形成されることになる。樹脂成
形後に離型し、凹部で露出するリード下面にハンダ等の
導電性接着剤８をデイピング等により付着させ、さいご
にＩＣパッケージ個々にリードフレームの不要部分を切
断除去することにより半導体装置の完成品を得る。FIG. 8 is a front sectional view when the semiconductor device of the present invention is packaged by a resin molding device. That is, a state in which the lead frame component shown in FIG. 7 is inserted into the resin molding dies 11 and 12 is shown. The resin 14 is injected into the gap between the chip and the lead frame through the runner 13 of this mold to form a package molded body (6 in FIG. 1). In this molding die, part of the die (lower die) 12 comes into contact with the lower surface of the outer lead, so that the recess 4 of the package is formed at this portion. After the resin is molded, the mold is released, and a conductive adhesive 8 such as solder is attached to the lower surface of the lead exposed in the recess by dipping or the like, and an unnecessary portion of the lead frame is cut and removed for each IC package on the die. Get the finished product.
【００１８】[0018]
【発明の効果】以上説明した本発明によれば、小型面付
タイプ樹脂封止半導体パッケージとして次の効果が得ら
れる。（１）アウターリードの外端部をパッケージの側
面より突出させることなく、リードの下面をパッケージ
下面の凹部に露出することにより、パッケージの実装面
積を小さくすることができ、複数個の電子装置を近接さ
せ高密度実装ができる。（２）実装時のリード位置決め
が容易となる。（３）外部ストレスによるリード変形等
の不良ポテンシャルがなくなり品質向上ができる。
（４）リードに導電性接着剤を付着させ、これを表面張
力による球状化することで配線基板との良好な接続が得
られ、実装の自動化も実現できる。According to the present invention described above, the following effects can be obtained as a small surface-mount type resin-sealed semiconductor package. (1) The mounting area of the package can be reduced by exposing the lower surface of the lead to the concave portion of the lower surface of the package without protruding the outer end portion of the outer lead from the side surface of the package. Allows close proximity and high-density mounting. (2) Lead positioning during mounting becomes easy. (3) It is possible to improve quality by eliminating defective potential such as lead deformation due to external stress.
(4) By attaching a conductive adhesive to the leads and making them spherical by surface tension, good connection with the wiring board can be obtained, and automation of mounting can also be realized.
【図１】本発明の一実施例を示す半導体装置（パッケー
ジ）の断面図である。FIG. 1 is a sectional view of a semiconductor device (package) showing an embodiment of the present invention.
【図２】図１の半導体装置の底面斜視図である。FIG. 2 is a bottom perspective view of the semiconductor device of FIG.
【図３】本発明の他の一実施例を示す半導体装置の底面
斜視図である。FIG. 3 is a bottom perspective view of a semiconductor device according to another embodiment of the present invention.
【図４】本発明の半導体装置を配線基板実装時の形態を
示す断面図である。FIG. 4 is a cross-sectional view showing a form in which the semiconductor device of the present invention is mounted on a wiring board.
【図５】本発明の他の一実施例の半導体装置の底面斜視
図である。FIG. 5 is a bottom perspective view of a semiconductor device according to another embodiment of the present invention.
【図６】本発明のさらに他の一実施例の半導体装置の底
面斜視図である。FIG. 6 is a bottom perspective view of a semiconductor device according to still another embodiment of the present invention.
【図７】本発明の半導体装置のパッケージング前のリー
ドフレーム構成品の形態を示す正面図である。FIG. 7 is a front view showing the form of a lead frame component before packaging of the semiconductor device of the present invention.
【図８】本発明の半導体装置のパッケージングのための
成形装置を示す縦断面図である。FIG. 8 is a vertical sectional view showing a molding apparatus for packaging a semiconductor device of the present invention.
１ タブ（リードフレーム） ２ 半導体チップ（ＩＣ） ３ リード（リードフレーム、アウターリード） ４ パッケージの凹部 ５ ワイヤ ６ 樹脂成形体（パッケージ部材） ８ ハンダ（球状化した状態） ９ プリント配線電極 １０ 基板 １１ 成形金型装置（上型） １２ 成形金型装置（下型） １３ ランナー １４ 注入された樹脂 1 Tab (Lead Frame) 2 Semiconductor Chip (IC) 3 Lead (Lead Frame, Outer Lead) 4 Package Recess 5 Wire 6 Resin Molded Body (Package Member) 8 Solder (Sphericalized) 9 Printed Wiring Electrode 10 Substrate 11 Molding mold device (upper mold) 12 Molding mold device (lower mold) 13 Runner 14 Injected resin
Claims (4)
れた複数の接続用端子とが、パッケージング部材により
包囲され封止されている半導体装置であって、接続用端
子の外端部はパッケージ部材の側面よりも突出すること
なく、端子の下面の一部がパッケージ下面の凹部に露出
していることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip and a plurality of connection terminals connected to electrodes of the chip are surrounded and sealed by a packaging member, and an outer end portion of the connection terminal is a package. A semiconductor device, wherein a part of the lower surface of the terminal is exposed in a concave portion of the lower surface of the package without protruding from the side surface of the member.
ッケージの接続用端子露出部を形成する凹部は１つの端
子ごとに設けられる2. The semiconductor device according to claim 1, wherein a recess forming the connection terminal exposed portion of the package is provided for each terminal.
ケージの接続用端子露出部を形成する凹部は複数の端子
を共有して設けられる。3. The semiconductor device according to claim 3, wherein the recess forming the connection terminal exposed portion of the package is provided so as to share a plurality of terminals.
装するにあたって、上記パッケージ下面凹部に露出する
接続用端子の下面にハンダ等の導電性接着剤を付着さ
せ、加熱することにより、表面張力で球形化した状態の
導電性接着剤を介して、パッケージ下面の接続用端子と
配線基板との接続を行なう。4. When mounting the semiconductor device according to claim 1 on a wiring board, a conductive adhesive such as solder is attached to the lower surface of the connection terminal exposed in the recess on the lower surface of the package, and the surface is heated. The connection terminals on the lower surface of the package are connected to the wiring board via the conductive adhesive in a spherical shape by tension.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331688A JPH05166964A (en) | 1991-12-16 | 1991-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331688A JPH05166964A (en) | 1991-12-16 | 1991-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05166964A true JPH05166964A (en) | 1993-07-02 |
Family
ID=18246472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3331688A Withdrawn JPH05166964A (en) | 1991-12-16 | 1991-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05166964A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36097E (en) * | 1991-11-14 | 1999-02-16 | Lg Semicon, Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| US5963433A (en) * | 1996-12-28 | 1999-10-05 | Lg Semicon Co., Ltd. | Bottom lead semiconductor package with recessed leads and fabrication method thereof |
| JP2006147972A (en) * | 2004-11-24 | 2006-06-08 | Kyocera Corp | Package for housing electronic part element, electronic device and packaging structure thereof |
| JP2017038051A (en) * | 2015-08-10 | 2017-02-16 | 株式会社ジェイデバイス | Semiconductor package and manufacturing method of the same |
-
1991
- 1991-12-16 JP JP3331688A patent/JPH05166964A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36097E (en) * | 1991-11-14 | 1999-02-16 | Lg Semicon, Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| USRE37413E1 (en) | 1991-11-14 | 2001-10-16 | Hyundai Electronics Industries Co., Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| US5963433A (en) * | 1996-12-28 | 1999-10-05 | Lg Semicon Co., Ltd. | Bottom lead semiconductor package with recessed leads and fabrication method thereof |
| JP2006147972A (en) * | 2004-11-24 | 2006-06-08 | Kyocera Corp | Package for housing electronic part element, electronic device and packaging structure thereof |
| JP4522236B2 (en) * | 2004-11-24 | 2010-08-11 | 京セラ株式会社 | Electronic device and electronic device mounting structure |
| JP2017038051A (en) * | 2015-08-10 | 2017-02-16 | 株式会社ジェイデバイス | Semiconductor package and manufacturing method of the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |