JPS6057107B2 - Erroneous reading detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for reading a plurality of pieces of information recorded on a medium using a common sampling signal, and more specifically,
The present invention relates to an erroneous reading detection circuit that detects erroneous reading due to medium skew, a defect in a medium feeding mechanism, etc.

Conventionally, in cart reading devices and the like that read information using sampling signals, if the sampling signal width is narrow, information is likely to be misread due to mispositioning of the information, skew of the medium, etc. Since the width of the information signal is particularly narrow in devices that handle the information, reading errors tend to occur particularly easily.

As a countermeasure to this problem, it was considered to widen the sampling signal width.

On the other hand, if you read a wide range of information, there is a possibility that you may misread the information in the adjacent position, and if the information code itself does not have a checking function, it will be input to the central processing unit as it is, and the system will not function properly. There were drawbacks that led to a decrease in reliability. SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit for detecting erroneous reading in the above-mentioned apparatus, which can be manufactured at low cost.

To achieve the above object, an erroneous reading detection circuit according to the present invention is used in an apparatus that reads a plurality of pieces of information recorded on a medium using a shared sampling signal, and has a waveform width that is at least longer than a period in which no sampling signal is generated. An AND circuit that takes the AND of the information OR signal and the sampling signal, and uses the output of the AND circuit as an input signal to sequentially output a '1' signal to the first stage output terminal and the second stage output terminal. and a circuit that outputs an error signal when both output terminals of the shift register are output, The configuration is such that erroneous reading can be detected by detecting that the sum signal is synchronized with the two sampling signals. According to the above configuration,
The objectives of the invention are fully achieved.

Hereinafter, the content of the present invention will be explained using an 8L punched card reader as an example.

FIG. 1 is a circuit diagram showing an embodiment of the misreading detection circuit according to the present invention, in which 1'' is an OR circuit, 2'', 3'', 4'' and 6'' are AND circuits, 5'' is a shift register, and 7 ′ is a flip-flop.

First, the case where a card medium having perforations alternately in rows 12 and 19 is normally read will be described using the timing chart of FIG. 2.

The information from 12th row to 9th row on the concave column card is read by a reading element, and furthermore, when there is drilling data, it is formatted by a not-illustrated shaping circuit so that it becomes logic "゜1", and signals 1 to 9 are read by a reading element. 12 and is supplied to the input of the OR circuit 1''.

The OR circuit 1'' generates an OR signal 13 of the information of rows 12 to 9, and the AND circuit 2'' generates the logical sum signal 13 of the information of columns 1 to 80.
It is ANDed with the signal 14 which holds ゛゜1゛ during the reading period of the column to generate the signal 15. Further, the signal 15 is logically ANDed with the information sampling signal 16 and inputted into the clock input of the shift register 5''.In other words, the sampling signal 16 in the column where the information ゛1゛ is present is used in the shift register 5''.
performs a shift operation, and since the data input terminal of the shift register is fixed at logic 66F', the output signal of the first stage of the shift register becomes 20p1. In the case of normal reading, there is always a signal of 15 between the sampling signal and the sampling signal for reading the next column.
Since becomes ゜゜0゛, the shift register reset signal 19 becomes ゜゜0゛ by the AND circuit 4'', and the shift register reset signal 20 also becomes ゜゜0゛.The information OR signal does not shift, As long as normal reading is performed, the signal 20 repeats "゜1゛" and "゜0", and the output signal 21 never becomes ゜゜1゛.Therefore, the output signal 22 of the AND circuit 6'' repeats "0". is maintained, and the output signal 23 of the flip-flop does not generate an erroneous signal.Next, due to an abnormality in the medium feeding frame system, the synchronization between the medium and the sampling signal is deviated, and an erroneous reading occurs at the 8th blank stitch. The process will be explained using the timing chart in Fig. 3.
As shown in the figure, 79, information OR signal 100 in column (a)
, 101 is the sampling signal 110 of 7 bacteria and 8 bacteria
, 111, the information OR signal 10 in the column No.
The shift register clock signal 120 is generated by the product of 0 and the sampling signal 110 in the fourth column, and the first stage output signal 20 of the shift register becomes "1".However, unlike in the case of normal reading, the sampling signal in the seventh column is 1
Since the information OR signal 100 holds "゛1" between the sampling signal 111 in the 79th column and the information OR signal 100 in the 79th column, the shift register 5'' is not reset. ) The shift register clock signal 121 is generated by the AND signal with the sampling signal 111 in the column. This signal causes the shift register to further perform a shift operation, and the first stage output signal 20
Both the second stage output signals become 66r゛. As a result, the output of the AND circuit 6' becomes '6r5', which enters the set clock of the flip-flop 7' for detecting erroneous reading, and the flip-flop outputs the set erroneous signal 23. Erroneous reading is detected in this way. After erroneous reading is detected, if the external reset signal 17, which was 1 during reading, is set to 0, the shift register 5' and flip-flop 7'' are reset, making it possible to detect erroneous reading again. state. As explained in detail above, the erroneous reading detection circuit according to the present invention detects an abnormality in the medium feeding mechanism system in which an information signal that corresponds to a specific sampling signal and should be read by that sampling signal is also read by other sampling signals. If such an error occurs, the circuit is configured to generate a signal to notify that an erroneous reading has occurred by detecting the change in the state of the information signal in relation to the sampling signal, so that the erroneous reading can be reliably detected. Furthermore, it is effective against not only abnormalities in the medium feeding mechanism system but also erroneous readings caused by skew, errors in writing information on the medium, and the like. Next, there is an advantage that adding this amount of circuitry alone does not lead to an increase in cost for the entire device.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the erroneous reading detection circuit according to the invention, Fig. 2 is a timing chart when normal reading is performed using a punched card reader in column a as an example, and Fig. 3 is a circuit diagram showing an example of an erroneous reading detection circuit in column a. FIG. 5 is a timing chart when reading occurs. FIG. 1″...OR circuit, 2″, 3″, 4″, 6″...
...AND circuit, 5Z...shift register,
7ζ・・・Flip-flop.

Claims (1)

[Claims] 1. In a device that reads multiple pieces of information recorded on a medium using a shared sampling signal, an information logical OR signal having a waveform width longer than at least a period in which no sampling signal is generated is ANDed with the sampling signal. The AND circuit and the output of the AND circuit are used as clock input signals to sequentially output a "1" signal to the first stage output terminal and the second stage output terminal, and are reset by the "0" signal of the information OR signal. and a circuit that outputs an error signal when both output terminals of the shift register are output, and detects that the information OR signal is synchronized with the two sampling signals, A misreading detection circuit configured to detect misreading.