JPS6329305B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that reads information recorded on a medium using a sampling signal, and relates to a detection circuit that detects information being omitted due to medium skew, malfunction of the medium feeding mechanism, etc. It is.

Conventionally, in card reading devices and the like that read information using sampling signals, if the sampling signal width is wide, reading errors such as reading adjacent information are likely to occur, while if the sampling signal width is narrow, the information may be misaligned or the media may be misread. Missing reading of information is likely to occur due to skew or failure of the feeding mechanism system.Furthermore, in devices that handle marks, especially since the width of the information signal is narrow, there is a tendency for reading missing to occur even more easily.

For this reason, if the information code itself does not have a check function, the information that has been misread will be input directly to the central processing unit, resulting in a problem with the reliability of the system.

Further, in order to detect such errors such as read omissions, methods of monitoring the time while reading the medium have already been devised, but there remain problems such as inability to reliably detect errors.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the prior art. Therefore, an object of the present invention is to provide a device for reading information recorded on a medium using a sampling signal. An object of the present invention is to provide a novel read-miss detection circuit that can reliably detect read-misses and greatly improve the reliability of an information reading device.

The above-mentioned object of the present invention is to provide a device for reading information recorded on a medium using a sampling signal, which includes a detection means for detecting the presence of information, and a detection means for detecting the presence of information, and a detection means for detecting the presence of information, and an information signal and a sampling signal output from the detection means. This is achieved by a read-miss detection circuit characterized by having means for monitoring that the AND becomes "1".

The principle of the present invention utilizes the fact that when reading information from a medium is omitted, "the information signal is detected, but the AND of the information signal and the sampling signal does not become "1"."

An embodiment in which the content of the present invention is applied to an 80-column punched card reader will be specifically described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, reference numbers 1 and 2 are AND circuits,
3 is a NAND circuit, 4 is an inverter circuit, 5, 6,
7 indicates a D-type flip-flop, respectively. In the flip-flop 5, the signal c is input to the input terminal.
Signal d is connected to the clock input terminal, and signal f is connected to the reset terminal. flipflop 6
, the signal i is connected to the input terminal, the signal j to the clock input terminal, and the signal g to the reset terminal. In the flip-flop 7, the signal m is connected to the input terminal, the signal k to the clock terminal, and the signal g to the reset terminal. The flip-flop 5 has a function of checking the presence or absence of information (data) detected by a reading element (not shown), the flip-flop 6 has a function of detecting whether or not information has been read out, and the flip-flop 7 has a function of checking the presence or absence of information (data) detected by a reading element (not shown). Each has a function of storing the detected state.

First, the case where a punched card is read normally will be explained using the timing diagrams shown in FIGS. 2A to 2I.

When the device is in its initial state, the reset signal g becomes "0" and the flip-flops 5, 6 and 7 are reset. When a card reading command is sent, the information on the punched card is read by a reading element, and is further formatted by a shaping circuit (not shown) so that it is at logic "1" when there is punched data; It is supplied to the input of the AND circuit 1 as the signal b. The AND circuit 1 performs a logical product with the signal a which holds "1" during the reading period, and generates the data signal d during the reading period. When the reading element detects the data signal A1 during the reading period, the input terminal signal e of the flip-flop 5 becomes logic "1".
Therefore, the flip-flop 5 is in the set state and the output signal i becomes "1".
Furthermore, when the sampling signal B1 corresponding to the data signal A1 is generated, the logical product of the signal A1 and the signal B1 becomes "1" due to normal reading, and the output signal h of the NAND circuit 3 becomes "0". "Nimata"
The output signal f of the AND circuit 2 also becomes "0", and the output signal i of the flip-flop 5 becomes "0". At the falling edge of the data signal A1, the data inversion signal j changes from "0" to "1", the state of the signal i at this time ("0" in this case) is stored in the flip-flop 6, and the signal k changes to "0". "become. As a result, since the clock signal k of the flip-flop 7 does not become "1" for the data signal A1, the flip-flop 7 is not set, and the readout detection signal l is not set.
remains at “0”. Further, when there is no data signal, the flip-flop 5 is never set, and the signal 1 remains at "0" as in the case of the data signal A1.

Next, Fig. 3 A to I shows the case where the data signal and the sampling signal are out of synchronization and a readout occurs.
This will be explained using the timing diagrams shown in FIGS.

FIG. 3 shows a case where the data signal A1 is ahead of the corresponding sampling signal B1, and a readout has occurred with respect to the data signal A1. When the data signal A1 is detected, the flip-flop 5 is set and the output signal i becomes "1". However, since the AND of the data signal A1 and the corresponding sampling signal B1 does not become "1", the reset signal f of the flip-flop 5 is
does not become "0", and the flip-flop 5 still maintains the set state. At the fall of the data signal A1, the data inversion signal j becomes "1", the state "1" of the signal i is stored in the flip-flop 6, and the output signal k becomes "1". In addition, since the input signal m of the flip-flop 7 is fixed at logic "1", the flip-flop 7 is also set at the same time as the signal k becomes "1", and the readout detection signal l is set.
becomes “1”. By using this read-miss detection signal l, it becomes possible to process data including read-misses so as to make them normal by some method.

FIG. 4 shows a case where the data signal A1 lags behind the corresponding sampling signal B1, causing data to be read out. Data signal A
When 1 is detected, the flip-flop 5 is set and the output signal i becomes "1". however,
Sampling signal B1 corresponding to data signal A1
has already occurred before data signal A1, data signal A1 and sampling signal B1
The logical product of ``1'' does not result in ``1'', so the flip-flop 5 maintains the set state. Data signal A
At the falling edge of 1, the state "1" of the signal i is stored in the flip-flop 6, and the output signal k becomes "1". At the same time, the flip-flop 7 is also set, and the readout detection signal l becomes "1", indicating that the readout has been missed. Notify that something has occurred.

Once a readout is detected, by setting the reset signal g to "0", the flip-flops 5, 6,
7 is reset, and read-miss detection becomes possible again.

As described above, it is clear that the circuit of the present invention reliably detects data loss due to a synchronization difference between the data signal and the sampling signal. Furthermore, even if the OR signal of all data is used instead of the data signal b, the detection rate will drop slightly due to the effects of skew, etc., but it is possible to detect read omissions without increasing costs. It is clear that misreading can be detected reliably in a mark card or the like in which only one spot is marked in a column.

As explained above, the present invention reliably detects the omission of information by monitoring that the AND of the information signal and the sampling signal always becomes "1" when the presence of information is detected. There is an effect that can be achieved.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an illustrative example, and it goes without saying that the present invention is not limited only to the embodiment described herein.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a timing diagram when normal reading is performed using a column 80 perforation reading device as an example, and FIGS. 3 and 4 are timing diagrams when reading errors occur. 1, 2...AND circuit, 3...NAND circuit, 4
...Inverter circuit, 5, 6, 7...Flip-flop.

Claims (1)

[Claims] 1. Due to the deviation between the information signal and the sampling signal used in a device that reads the information signal having the first and second levels input discretely on the time axis while the sampling signal is output. In a detection circuit for detecting a readout of an information signal, the information signal having a first level is detected and the first level is detected.
display means for outputting a signal; and a reset device for stopping output of the first signal from the display means when the sampling signal is applied during a period in which the information signal having the first level is input. and monitoring means for detecting that the first signal is obtained during a period in which the information signal having the first level is not present and outputting an information signal omission detection signal. Features: Information signal readout detection circuit.