JPH0831064B2 - Memory diagnostic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention stores a parallel signal as well as a parity signal, and when reading a parallel signal, a diagnostic of a memory circuit for performing parity check by the parity signal read at the same time. Regarding the circuit.

(Prior Art) FIG. 3 is a circuit diagram showing an example of a conventional memory diagnostic circuit.

The parallel input signal is stored in the memory circuit 11 and is operated by the parity operation circuit 10 to add one bit of the parity signal according to the rule.

The parity signal of the parity calculation circuit 10 is stored in the memory circuit 11.

The parallel output signal read from the memory circuit 11 is input to the parity error detection circuit 12 and the parity calculation is performed. The parity error detection circuit 12 compares the parity calculation result with the parity signal read from the memory circuit 11 to detect an error in the memory circuit 11.

(Problems to be Solved by the Invention) The conventional memory diagnostic circuit has a drawback that an error cannot be detected when the circuit on the write side of the memory is stopped.

An object of the present invention is to solve the above drawbacks and to provide a memory diagnostic circuit capable of detecting an error in the memory circuit when the circuit on the write side of the memory is stopped.

(Means for Solving the Problem) In order to achieve the above-mentioned object, a memory diagnostic circuit according to the present invention inputs N parallel signals and gives N first signals each having a different delay amount. Shift register circuit, a parity operation circuit for performing a parity operation on the N first shift register circuit outputs, the N parallel input signals and the parity operation circuit output, and the N parallel inputs A memory circuit that writes and reads signals in the same order and continuously and N parallel output signals read from the memory circuit are input, and the N
N second shift register circuits that give the same amount of delay to the respective signals as the delay amounts given by the first shift register circuit, and the N second shift register circuit outputs are subjected to parity calculation, The parity error detection circuit detects an error by comparing the parity-calculated signal with the parity signal read from the memory circuit.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a memory diagnostic circuit according to the present invention. The present embodiment shows an operation in a state where data writing and reading are continuously performed.

The N parallel input signals are delayed by the first shift register circuits 1 and 2 by a predetermined number of bits. Then, the parity calculation circuit 3 performs the parity calculation of the N shift outputs of the first shift register circuits 1 and 2 respectively, and the calculation result is stored in the memory circuit 4.

The N parallel output signals read from the memory circuit 4 have the same rules as the input side, and the second shift register circuits 5 and 6 have the same rule.
Delayed by and the parity calculation is performed. The parity error detection circuit 7 compares the parity calculation result with the parity signal from the memory circuit 4 to determine whether or not there is an error.

Parity calculation uses odd parity, even parity, and odd and even alternation parity.

FIG. 2 is a timing chart when three parallel signals are input.

When the three parallel signals 20 to 22 are input, the three parallel input signals are input to the first shift register circuits 1 and 2, respectively, and the parallel input signal (A) 20 corresponds to 2 bits and the parallel signal (A). B) 21 is delayed by 1 bit, and parallel signal (C) 22 is delayed by 0 bit. Then, the parity calculation (parity calculation of A, B, and C) is performed, and the parity signal 23 is output through the memory circuit 4. The parallel signal read from the memory circuit 4 is given a delay similar to that on the input side by the second shift register circuits 5 and 6, the parity operation is performed by the parity error detection circuit 7, and the parity signal 23 from the memory circuit 4 is supplied. Compared to.

As described above, even when the memory circuit 4 fails and the input side, that is, the writing side is stopped, it is detected as a parity error.

At the start of writing and reading of data, a data error may occur, but it can be monitored in a steady state where data is continuously read and written.

(Effect of the Invention) As described above, according to the present invention, due to the operation check of the memory circuit, the parity calculation is performed by delaying the time by applying an amount of delay that overlaps each signal of the N parallel input signals to perform the parity calculation. By passing the result through the memory circuit, the error can be detected even when the input side of the memory circuit, that is, the writing side circuit is stopped.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a memory diagnosis circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit of the present invention and a conventional circuit, and FIG. 3 is an example of a conventional memory diagnosis circuit. FIG. 1, 2 ... first shift register circuit 3, 10 ... parity operation circuit 4, 11 ... memory circuit 5, 6 ... second shift register circuit 7, 12 ... parity error detection circuit 20 ... Parallel input signal A 21 …… Parallel input signal B 22 …… Parallel input signal C 23 …… Parity signal

Claims (1)

[Claims] 1. N parallel signals are input respectively, and N
N first shift register circuits that give different delay amounts to the respective signals, a parity operation circuit that performs a parity operation on the N first shift register circuit outputs, the N parallel input signals, and the N parallel input signals A parity operation circuit output is input, and a memory circuit that writes and reads the N parallel input signals in the same order and continuously, and N parallel output signals read from the memory circuit are input. The N second shift register circuits that give the same delay amount to the respective signals as the delay amounts given by the first shift register circuit and the N second shift register circuit outputs are subjected to parity calculation, A parity error detection circuit for detecting an error by comparing the parity-calculated signal with the parity signal read from the memory circuit. Memory diagnostic circuit to be.