JPS6057092B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device comprising a plurality of storage units.

In a data processing device in which a main memory device consisting of a plurality of memory units is connected to an arithmetic processing unit (hereinafter abbreviated as BPU), information indicating which part of the main memory device address each memory unit constitutes (hereinafter abbreviated as BPU) is used. This is called a floating address) is set in a register provided for each (hereinafter referred to as a floating address register).

When main memory is accessed by a BPU, a storage unit having a floating address equal to the upper bits of the access address is accessed. Floating addresses are conventionally set as follows.

In FIG. 1, 1 is a BPU, and 2 and 3 are storage units. Each of storage units 2 and 3 has n banks B,
~Bn is included. R, ~Rn are bank averages ~
There are floating address registers provided corresponding to each of Bn. In the data processing apparatus as described above, floating addresses are set as shown in table (a) or (b) of FIG.

(a) first assigns floating addresses 0 to n-1 in order to floating address registers R1 to Rn on the storage unit 2 side, and then assigns floating addresses n in order to floating address registers R1 to Rn on the storage unit 3 side. This is a method of allocating -2n-1. (b) The floating address registers of storage units 2 and 3 are alternately set to floating addresses 0 to 3.
There is a method to allocate 2n-1. Now, the memory area (prefix area) uniquely used by BPUI is
Bank 8 of floating address ■O is used, and if a failure occurs in this bank clearing, bank 8 of floating address 21 is used.

Therefore, with method (a), if a failure occurs in the storage unit 2, the prefix area cannot be secured. In order to eliminate this inconvenience, if method (b) is used, there is a problem that if a failure occurs in one of the storage units, the floating addresses become discontinuous, making it impossible to construct a complete address space. This invention has been made to solve the problems of the prior art as described above.

In this invention, the floating address of the storage unit is set according to the status of other storage units. That is, in the present invention, each storage unit has a circuit that checks whether or not the storage unit itself is operating normally, a signal line for sending the output of the check circuit to other storage units, and a circuit that connects the output of the check circuit and the circuit. Depending on the output from the check circuit of the other memory unit obtained via the signal line, as long as the output of the check circuit is normal, the floating address that is continuous with the floating address of the other normal memory unit is sent to the memory unit. The storage device is characterized by a floating address setting circuit for setting a register in the memory. An embodiment of this invention will be described below.

FIG. 3 is a block diagram of a data processing device according to the present invention. In Figure 3, the same items as in Figure 1 are
The same numbers as in the figure are given. 4 is a signal line provided between storage units 2 and 3.

The status signals of storage units 2 and 3 are each sent to the other through signal line 4. FIG. 4 shows a floating address setting section on the storage unit 2 side.

Components that are the same as in Figure 3 are given the same numbers as in Figure 3. The same circuit is provided on the storage unit 3 side as well. In the figure, 8 is an operation check circuit that checks the power supply status, failure status, etc. of its own storage unit to check whether or not it is operating normally, and outputs a status signal indicating whether or not normal operation is possible to the signal line 4; This floating address setting circuit receives the output from the operation check circuit 8 and the status signal from the other storage unit 3, and sets floating addresses in the floating address registers R1 to Rn according to the contents thereof. The floating address setting circuit 9 of the storage unit 2 sets each of the floating address registers R1 to Rn using a general reset when the power of the storage units 2 and 3 is turned on.
Set the floating address according to (b) to (e) in the table of FIG. That is, if both storage units 2 and 3 can operate normally, the floating address setting circuit 9 sets the floating address registers R1 to RO to 0 and 0, respectively, as shown in (b).
2...Assign a nod of -2. Furthermore, if only the storage unit 2 can operate normally, O-n-1 is assigned to each of the floating address registers R1 to Rn, as shown in (c). Also, if the storage unit 2 cannot operate normally, (d), (
As in e), no floating address is assigned to the floating address register. Needless to say, if the floating address setting unit itself is unable to operate normally, the situation will be exactly the same. On the other hand, the floating address setting circuit of the storage unit 3 also sets floating addresses in accordance with (b) to (e) in the table of FIG. 2 in the same manner as described above.

In the above embodiments, the number of storage units and the number of banks in the storage unit are respectively 2 and n, but
The number of storage units is not limited to this, and the number of storage units may be greater than two, and the number of banks n may be one.

According to the present invention as described above, since the floating address of the unit is automatically set according to the status of other storage units,
As long as all the storage units are not inoperable, a prefix area can be secured, and even if a certain storage unit is inoperable, floating addresses will not become discontinuous and the address space will not be configured.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional data processing device, FIG. 2 is a table for explaining a floating address setting method, FIG. 3 is a block diagram of a data processing device according to the present invention, and FIG.
The figure is a block diagram of a floating address setting section. In Figures 3 and 4, 1...BPU, 2, 3...
...Storage unit, 4...Signal line, B1~
Bn: Bank, R1 to Rn: Floating address register.

Claims (1)

[Claims] 1. In a storage device consisting of a plurality of storage units, each of which is provided with a register for setting a floating address that is the upper bit part of an access address, each of the storage units is configured to check whether or not the storage unit itself can operate normally. a signal line for sending the output of the check circuit of the storage unit itself to another storage unit; and a circuit for checking the other storage unit obtained through the output of the check circuit and the signal line. and a floating address setting circuit that sets in the register a floating address that is continuous with the floating addresses of other normal storage units as long as the output of the check circuit is normal according to the output from the circuit. storage device.